CN104011870A - 减小的接触电阻的自对准接触金属化 - Google Patents

减小的接触电阻的自对准接触金属化 Download PDF

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CN104011870A
CN104011870A CN201180075772.6A CN201180075772A CN104011870A CN 104011870 A CN104011870 A CN 104011870A CN 201180075772 A CN201180075772 A CN 201180075772A CN 104011870 A CN104011870 A CN 104011870A
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drain regions
source
shaped
layer
type
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CN104011870B (zh
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G·A·格拉斯
A·S·默西
T·加尼
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Intel Corp
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Abstract

公开了用于形成低接触电阻晶体管设备的技术。P型锗层设置在p型源极/漏极区和它们相应的接触金属之间，且n型III-V半导体材料层设置在n型源极/漏极区和它们相应的接触金属之间。n型III-V半导体材料层可具有小带隙(例如<0.5eV)和/或否则被掺杂以提供期望导电性，且p型锗层可被掺杂有例如硼。在III-V材料沉积在n型源极/漏极区和锗覆盖的p型源极/漏极区之上之后，回蚀工艺可被执行来利用在n型和p型区之间的高度差以使接触类型自对准并暴露在n型区之上的的p型锗并使在n型区之上的n型III-V材料变薄。所述技术可在平面和非平面晶体管架构上使用。

Description

减小的接触电阻的自对准接触金属化
背景技术
包括晶体管、二极管、电阻器、电容器和在半导体衬底上形成的其它无源和有源电子设备的电路设备的增加的性能一般是在那些设备的设计、制造和操作期间考虑的主要因素。例如，在金属氧化物半导体(MOS)晶体管半导体设备(例如在互补金属氧化物半导体(CMOS)中使用的那些半导体设备)的设计和制造或形成期间，常常希望最小化与否则被称为外部电阻Rext的接触部相关联的寄生电阻。降低的Rext从同样的晶体管设计实现较高的电流。
附图说明
图1A是根据本发明的实施例的用于形成具有低接触电阻的晶体管结构的方法。
图1B是根据本发明的另一实施例的用于形成具有低接触电阻的晶体管结构的方法。
图2A到2I示出根据本发明的实施例的当执行图1A的方法时形成的结构。
图3A到3C示出根据本发明的实施例的当执行图1B的方法时形成的可选结构。
图4A-E各示出根据本发明的一个实施例配置的非平面晶体管架构的透视图。
图5示出根据本发明的示例性实施例的使用一个或多个晶体管结构实现的计算系统。
如将认识到的，附图不一定按比例绘制或用来将所主张的发明限制到所示的特定配置。例如，虽然一些附图通常指示直线、直角和平滑表面，但鉴于所使用的处理设备和技术的实际限制，晶体管结构的实际实现方式可能具有不太完美的直线、直角，且一些特征可具有表面拓扑或否则是不平滑的。简言之，附图仅被提供来显示示例性结构。
具体实施方式
公开了用于形成具有相对于常规设备减小的寄生接触电阻的晶体管设备的技术。在一些示例性实施例中，MOS结构被配置成使得p-MOS源极/漏极区在接触沟槽形成之前或之后覆盖有p型锗，且n型III-V半导体材料层设置在n-MOS区和锗覆盖的p-MOS区之上。因此，覆盖有p型锗的p-MOS源极/漏极区比n-MOS硅源极/漏极区相对更高。回蚀工艺可接着被执行来利用在n型和p型区之间的源极/漏极高度差以使接触类型自对准以暴露在n-MOS区之上的III-V材料和在p-MOS区之上的锗。技术还可包括跟随有锗/III-V化合物形成退火的接触电阻减小金属沉积和然后跟随有抛光以去除过量金属从而隔离每个接触沟槽与相邻的接触沟槽的金属接触插塞的沉积。
总体概述
如前面解释的，可通过减小设备电阻来实现晶体管中的增加的驱动电流。接触电阻是设备的总电阻的一个构成部分。一般晶体管接触叠层包括例如硅或硅锗(SiGe)源极/漏极层、硅化物/锗化物层、氮化钛粘附层和钨接触部/插塞。例如镍、铂、钛、钴等金属的硅化物和锗化物可在钨插塞沉积之前形成在源极-漏极区上。在这样的配置中，接触电阻相对高，且实际上被硅或SiGe价带对准限制到接触金属中的钉扎水平(pinning level)。通常，使用工业标准硅化物，例如镍(或其它适当的硅化物例如钛、钴、铝或铂)，这导致对于n型接触部大约0.5eV或更高的带未对准或对于p型接触部0.3eV或更高的带未对准和相应地高的电阻。
因此且根据本发明的示例性实施例，中间p型锗层设置在p型源极/漏极和接触金属之间，且中间n型III-V金属层设置在n型源极/漏极和接触金属之间。假定p型源极/漏极上的锗足够厚，随后的回蚀工艺于是导致在接触沟槽的底部处的被暴露表面，接触沟槽包括在n型源极/漏极之上的III-V材料区域和在p型源极/漏极之上的锗区域。标准接触部形成工艺流程可从那里继续进行。
在源极/漏极区和接触金属之间的中间III-V材料和锗层明显减小带未对准值和接触电阻。在一些示例性情况下，提供大约3X或更好的接触电阻的减小(相对于类似地配置的常规接触叠层，但没有III-V材料和锗的中间层)。在STEM明视场模式中的这样的接触沟槽的透射电子显微镜(TEM)横截面可用于显示例如通常匹配沟槽的形状(例如沟槽底部的形状)的III-V材料。III-V材料相对于硅或SiGe具有差异。同样，TEM横截面或次级离子质谱分析法(SIMS)分布可用于显示在p型区之上的锗浓度，因为硅和SiGe的外延合金的分布可容易地区别于锗浓度分布。成分分布和映射可用于显示所使用的材料的同一性(identity)。因此，当分析时，根据本发明成分的实施例配置的结构将实际上显示在n型源极/漏极区之上的包括例如铝(Al)、镓(Ga)、铟(In)、磷(P)、砷(As)和/或锑(Sb)连同任何n型掺杂剂(例如硅、锗、碲或其它适当的n型掺杂剂)的组合的额外的一层n型III-V半导体材料，以及在p型区之上的p型锗层(掺硼的或其它适当的p型掺杂剂)，并将展示比使用常规接触过程制造的设备的接触电阻低的接触电阻。如将认识到的，具有对高性能接触部的需要的任何数量的半导体设备或电路可受益于本文提供的低电阻接触技术。
在制造过程期间的p型和n型选择性可以用各种方式实现。在一个实施例中，例如，可通过使那些NMOS区在PMOS区沉积期间被掩蔽来避免在NMOS源极/漏极位置上的沉积。在另一实施例中，NMOS和PMOS区都可同时是敞开的，但沉积只通过对应的沟槽出现在相应的NMOS和PMOS区中。如将根据本公开内容进一步认识到的，选择性可包括自然选择性。例如，虽然p型掺杂的锗(例如以超过1E20cm-3的硼浓度被掺杂)在p型SiGe或硅源极/漏极区上生长，它不在例如二氧化硅(SiO2)或氮化硅(SiN)的绝缘体表面上生长；它也不在例如n型区中的暴露的磷重掺杂的硅上生长。类似地，n型掺杂III-V材料可以是例如Al、Ga、In、P、As和/或Sb(例如在>1E17cm-3的浓度下掺杂有硅、锗、硫、碲等)的任何组合，其将在n型SiGe或硅源极/漏极区和p型锗源极/漏极区上生长，但将不在例如SiO2或SiN的绝缘体表面上生长。在选择性是不可能的或否则不被使用或期望的情况下，则过量的沉积材料可例如使用平面化/抛光和/或蚀刻而被去除。
进一步注意，中间p型锗和n型III-V材料层可用来提高在任何数量的晶体管结构和配置——包括平面、凸起的源极/漏极、非平面(例如纳米线晶体管和鳍式晶体管例如双栅极和三栅极晶体管结构)以及应变和无应变沟道结构——中的接触电阻。此外，晶体管结构可包括被设计成例如降低晶体管的总电阻同时如有时实现的提高短沟道效应(SCR)的源极和漏极尖端区。源极/漏极区本身也可改变。在一些示例性实施例中，晶体管结构包括注入掺杂剂的源极/漏极区或硅、SiGe合金或在MOS结构中的名义上纯的锗膜(例如具有小于10％硅的那些膜)的外延(或多晶)替代源极/漏极区。在任何这样的实现方式中，根据本发明的实施例，例如硼掺杂的锗(或其它适当的p型锗)的层或盖可直接在p型源极/漏极区之上形成，且例如硅掺杂的III-V材料(或其它适当的n型III-V材料)的层或盖可直接在n型源极/漏极区之上形成。接触金属(或一系列金属)可接着被沉积，且随后的反应(退火)可被执行以形成金属锗/III-V化合物源极和漏极接触部。金属插塞沉积可紧接着。如根据本公开内容将认识到的，中间p型锗和/或n型III-V层也可直接在晶体管结构的例如多晶栅极(poly gate)和/或接地分接头(tap)区的其它部分之上形成，如果这么希望的话。任何数量的结构特征可结合如本文所述的p型锗和n型III-V材料层来使用。
在一些实施例中，注意，III-V半导体材料可保持无掺杂，且特别是相对于具有在大约0.5eV之下的带隙的III-V材料，因为在室温下在这样的小带隙材料中的载流子的热生成足以实现高导电性。在使用掺杂的其它实施例中，例如在使用具有任意带隙的III-V材料的那些实施例中，掺杂可以以多种方式执行，包括原位和非原位掺杂技术(例如，类似于在p型区之上的锗层的掺杂技术)。一些这样的实施例使用具有第IV列掺杂剂(例如硼、硅、锗或锡)的足够高的掺杂水平的III-V材料。在非常高的掺杂水平(例如大于1E17原子/cm3代位浓度)下，这些两性掺杂剂贡献在价带和导带中的载流子，从而增加这两种载流子类型的载流子浓度。在一些这样的情况下，掺杂被原位执行。在其它实施例中，本征的III-V材料层被沉积，后面是非原位掺杂过程，例如离子注入或扩散掺杂，以便提供期望的导电性(例如具有例如100到500S/cm的值的导电性)。
方法和架构
图1A是根据本发明的实施例的用于形成具有低接触电阻的晶体管结构的方法。图2A到2I示出当该方法被执行时形成的且根据某些实施例的示例性结构。
示例性方法包括在半导体衬底上形成(102)一个或多个栅极叠层，MOS设备可在该半导体衬底上形成。MOS设备可包括NMOS或PMOS晶体管或NMOS和PMOS晶体管两者(例如对于CMOS设备而言)。图2A示出示例性的所得到的结构，其在这种情况下包括在同一衬底300上形成并被浅沟槽隔离(STI)分离的NMOS和PMOS晶体管两者。也可使用在p型和n型区之间的其它适当形式的隔离。如可看到的，每个栅极叠层在晶体管的沟道区之上形成，并包括栅极电介质层302、栅极电极304、可选的硬掩模306和相邻于栅极叠层而形成的间隔体310。
栅极电介质层302可以是例如任何适当的氧化物例如二氧化硅(SiO2)或高k栅极电介质材料。高k栅极电介质材料的例子包括例如氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。在一些实施例中，当高k材料被使用时，可对栅极电介质层302执行退火工艺以提高它的质量。在一些特定的示例性实施例中，高k栅极电介质层302可具有在到大约(例如)的范围内的厚度。在其它实施例中，栅极电介质层302可具有氧化物材料的一个单层的厚度。通常，栅极电介质302的厚度应足以使栅极电极304与源极和漏极接触部电隔离。在一些实施例中，可对高k栅极电介质层302执行额外的处理(例如退火工艺)以提高高k材料的质量。
栅极电极304的材料可以是例如多晶硅、氮化硅、碳化硅或金属层(例如钨、氮化钛、钽、氮化钽)，虽然也可使用其它适当的栅极电极材料。在一些示例性实施例中，栅极电极304的材料具有在到(例如 )的范围内的厚度，所述材料可以是稍后针对替代金属栅极(RMG)过程去除的牺牲材料。
可选的栅极硬掩模层306可用于在处理——例如保护栅极电极304免受随后的蚀刻和/或离子注入处理——期间提供某些益处或用途。可使用一般硬掩模材料(例如二氧化硅、氮化硅和/或其它常规绝缘体材料)来形成硬掩模层306。
可如照惯例完成的或使用任何适当的定制技术(例如蚀刻掉栅极电极和栅极电介质层的部分以形成栅极叠层的常规图案化工艺，如图2A所示的)来形成栅极叠层。可例如使用常规沉积工艺(例如化学气相沉积(CVD)、原子层沉积(ALD)、旋涂沉积(SOD)或物理气相沉积(PVD))来形成栅极电介质层302和栅极电极304材料中的每个。也可使用备选沉积技术，例如栅极电介质302和栅极电极304的材料可以是热生长的。如根据本公开将认识到的，任何数量的其它适当的材料、几何结构和形成过程可用于实现本发明的实施例，以便提供如本文所述的低接触电阻晶体管设备或结构。
可例如使用常规材料(例如氧化硅、氮化硅或其它适当的间隔体材料)来形成间隔体310。通常可基于对所形成的晶体管的设计要求来选择间隔体310的宽度。然而根据一些实施例，间隔体310的宽度并不受到由源极和漏极epi-尖端的形成强加的设计约束，假定在源极/漏极尖端区中的掺硼的锗的成分足够高。
任何数量的适当衬底可用于实现衬底300，包括体衬底、绝缘体上半导体衬底(XOI，其中X是半导体材料，例如硅、锗或富含锗的硅)以及多层结构——包括鳍状物或纳米线可在随后的栅极图案化工艺之前形成于其上的那些衬底。在一些特定的示例性情况下，衬底300是锗或硅或SiGe体衬底，或在氧化物衬底上的锗或硅或SiGe。虽然这里描述了可形成衬底300的材料的几个例子，可用作基底(低电阻晶体管设备可构建在该基底上)的其它适当的材料落在所要求保护的本发明的精神和范围内。
进一步参考图1A，在一个或多个栅极叠层形成之后，该方法以界定(104)晶体管结构的p型和n型源极/漏极区继续。可使用任何数量的适当工艺和配置来实现源极/漏极区。例如，源极/漏极区可以被注入、蚀刻和epi填充，是凸起的，是硅或锗或SiGe合金，是p型和/或n型的，并具有平面或鳍或线路形扩散区。例如，在一些这样的示例性情况下，可使用注入/扩散工艺或蚀刻/沉积工艺来形成源极和漏极区。在前一工艺中，掺杂剂例如硼、铝、锑、磷或砷可离子注入到衬底300中以形成源极和漏极区。离子注入工艺一般跟随有激活掺杂剂的退火工艺，并且也可使它们进一步扩散到衬底300中。在后一工艺中，衬底300可首先被蚀刻以形成在源极和漏极区的位置处的凹槽。外延沉积工艺可接着被执行以用硅合金(例如硅锗或碳化硅)填充凹槽，从而形成源极和漏极区。在一些实现方式中，可以使用掺杂剂(例如硼、砷或磷)对外延地沉积的硅合金进行原位或非原位掺杂，这取决于所述区用于p型还是n型功能。
在图2A-2I所示的示例性实施例中，衬底300被蚀刻以提供腔以及底切栅极电介质302的相应的尖端区域。腔和尖端区域被填充以提供源极/漏极区和也被称为源极-漏极延伸部的可选的尖端区。根据衬底300是硅体或绝缘体上硅(SOI)衬底的一些特定的示例性实施例，源极和漏极腔连同它们相应的尖端区域一起被填充有原位掺杂硅或SiGe或锗，从而形成源极和漏极区(连同它们相应的epi尖端)。在这里可使用关于材料(例如掺杂或无掺杂的Si、Ge、SiGe)、掺杂剂(例如硼、砷或磷)和几何结构(例如源极/漏极层的厚度范围可例如从50到500nm以便提供齐平或凸起的源极/漏极区)的任何数量的源极/漏极层配置。
如根据本公开内容将认识到的，可使用本发明的实施例实现任何数量的其它晶体管特征。例如，沟道可以是应变或无应变的，且源极/漏极区可以或可以不包括在对应的源极/漏极区和沟道区之间的区域中形成的尖端区。在这个意义上，晶体管结构是否具有应变或无应变沟道或源极-漏极尖端区或不具有源极-漏极尖端区与本发明的各种实施例并不特别相关，且这样的实施例并不意在被限制于任何特定的这样的结构特征。相反，任何数量的晶体管结构和类型且特别是那些同时具有n型和p型源极/漏极晶体管区的结构，可受益于使用小带隙和/或否则是在n型源极/漏极区之上的充分掺杂的III-V材料层和在p型源极/漏极区之上的充分掺杂的锗，如在本文描述的那样。通常，如果III-V材料带隙足够小，则在室温下不需要掺杂剂(虽然掺杂剂可被使用，如果这么希望的话)。在一个特定的示例性情况下，无掺杂锑化铟适合于n型源极/漏极区，而掺硼锗适合于p型源极/漏极区。然而对于较大的带隙III-V材料(>0.5eV)，掺杂可用于提供在n型III-V材料中的期望导电性。
进一步参考图1A，在源极/漏极区被界定之后，这个示例性实施例的方法以沉积(106)绝缘体层322继续。图2B将绝缘体层322示为与栅极叠层的硬掩模306齐平，但它不需要如此。可以用多种方式配置绝缘体。在一些实施例中，使用SiO2或其它低k电介质(绝缘体)材料来实现层322。在更一般的意义上，可按需要选择层322的材料的介电常数。在一些实施例中，绝缘体层322可包括内衬(例如氮化硅)，然后是一层或多层SiO2或氮化物、氧化物、氮氧化物、碳化物、碳氧化物或其它适当的绝缘体材料的任何组合。可被称为层间电介质层(ILD)的绝缘体层322可如通常完成的那样被平面化(例如通过后沉积平面化工艺，例如化学机械平面化或CMP)。可用于形成层322的其它示例性绝缘体材料包括例如掺碳氧化物(CDO)、有机聚合物，例如八氟环丁烷或聚四氟乙烯、氟硅酸玻璃(FSG)和有机硅酸盐，例如倍半硅氧烷、硅氧烷或有机硅酸盐玻璃。在一些示例性配置中，绝缘体层322可包括孔或其它空隙以进一步减小其介电常数。
如根据本公开内容将认识到的且根据使用了替代金属栅极(RMG)工艺的本发明的一些实施例，该方法还可包括使用如照惯例进行的蚀刻工艺来去除栅极叠层(包括高k栅极电介质层302、牺牲栅极电极304和硬掩模层306)。在一些这样的情况下，只有牺牲栅极304和硬掩模层306被去除。如果栅极电介质层302被去除，则该方法可以以将新的栅极电介质层沉积到沟槽开口中继续。可在这里使用任何适当的栅极电介质材料，例如前面描述的那些材料，例如氧化铪。也可使用相同的沉积工艺。例如，栅极电介质层的替代可用于处理在干和湿蚀刻工艺的应用期间原始栅极电介质层可能出现的任何损坏，和/或用于以高k或否则期望的栅极电介质材料代替低k或牺牲电介质材料。在这样的RMG工艺中，该方法还可包括将栅极电极层沉积到沟槽中和栅极电介质层之上。常规沉积工艺(例如CVD、ADL和PVD)可用于形成替代栅极电极。栅极电极层可包括例如p型功函数金属，例如钌、钯、铂、钴、镍和导电金属氧化物，例如氧化钌。在一些示例性配置中，可沉积两个或更多个金属栅极电极层。例如，功函数金属可沉积在栅极沟槽中，然后是适当的金属栅极电极填充金属，例如铝或银。图2B’示出由这样的可选RMG工艺得到的示例性栅极结构，其包括在替代栅极电介质层324之上的替代栅极电极层326。仍然在其它实施例中，这样的RMG处理可在该方法中稍后进行(例如在步骤118之后)，使得替代栅极材料将不受到与步骤118和更早的步骤相关的处理。
进一步参考图1A，在绝缘体层322被设置(以及任何期望的前接触形成RMG工艺)之后，该方法以蚀刻(108)从而形成源极/漏极接触沟槽继续。可使用标准光刻法，而后是任何适当的干和/或湿蚀刻工艺。图2C示出根据一个示例性实施例的在蚀刻完成之后的源极/漏极接触沟槽。
该方法以将p型锗层317选择性地沉积(110)到晶体管结构的沟槽中和p型源极/漏极区之上继续，如在图2D中最佳地示出的。注意，作为这个选择性锗沉积的结果，p型源极/漏极区现在实际上比更短的n型源极/漏极区相对更高。在一些实施例中，p型锗层317包括掺硼锗，虽然也可使用其它适当的p型锗。掺硼锗工艺的益处是，其对于绝缘体322和SiGe源极漏极区的n型硅二者而言都是选择性的。在一些这样的示例性实施例中，可外延地沉积在一层或多层中的掺硼锗层317具有超过90原子％的锗浓度，虽然可使用其它适当的浓度水平，如根据本公开内容将认识到的(例如超过91原子％或92原子％……或98原子％或99原子％或真正纯的锗)。注意，这个锗浓度可以是固定的，或分级的，以便从基本水平(在衬底300附近)增加到高水平(例如超过90原子％)。在一些这样的实施例中，硼浓度可超过1E20cm-3，例如高于2E20cm-3或2E21cm-3，且也可以是分级的，以便从衬底300附近的基本水平增加到高水平(例如超过1E20cm-3或2E20cm-3或3E20cm-3……2E21cm-3)。在下层p型源极/漏极区的锗浓度是固定的或否则相对低的实施例中，分级缓冲层可用于使源极/漏极区与掺硼锗层317更好地接合。根据一些特定的示例性实施例，掺硼锗层317的厚度可具有在例如50到的范围内的厚度，虽然可选的实施例可具有其它层厚度，如根据本公开内容将显而易见的。
在一些实施例中，CVD工艺或其它适当的沉积技术可用于沉积(110)或否则形成掺硼锗层317。例如，可在CVD或快速热CVD(RT-CVD)或低压CVD(LP-CVD)或超高真空CVD(UHV-CVD)或气体源分子束外延(GS-MBE)工具中使用含锗和硼前体(例如锗烷(GeH4)或乙锗烷(Ge2H6)和乙硼烷(B2H6)或二氟化硼(BF2))来执行沉积110。在一些这样的实施例中，可以有载气，例如氢气、氮气或惰性气体(例如前体在1-20％的浓度下被稀释，平衡是载气)。也可以有蚀刻剂气体，例如基于卤素的气体，例如氯化氢(HCl)、氯(Cl)或溴化氢(HBr)。锗以及还有掺硼锗的基本沉积在使用在例如在300℃到800℃的范围内的沉积温度(例如400℃-500℃)和例如在1托到760托的范围内的反应器压力的宽范围条件下是可能的。锗是自然选择性的，因为它沉积在硅或硅-锗合金上，而不沉积在其它材料(例如二氧化硅和氮化硅)上。因为该自然选择性并不是完全完美的，小流量的蚀刻剂可用于增加沉积的选择性，如前面注意到的那样。载体和蚀刻剂中的每个均可具有在10和300SCCM的范围内的流量(一般，需要不大于100SCCM的流量，但一些实施例可能需要更高的流率)。在一个特定的示例性实施例中，使用以1％的浓度并且以范围在100和1000SCCM之间的流率稀释在氢中的GeH4来执行沉积206。对于硼的原位掺杂而言，可使用稀释的B2H6(例如G2H6可以以3％的浓度并且以范围在10和300SCCM之间的流率稀释在H2中)。在一些这样的特定示例性情况下，以范围例如在10和100SCCM之间的流率添加蚀刻剂HCl和Cl2，以增加沉积的选择性。
如根据本公开内容将进一步认识到的，p型锗层317被沉积时的选择性可根据需要改变。在一些情况下，例如p型锗层317只沉积在p型源极/漏极区或那些区的一部分上(而不是遍及整个结构)。任何数量的掩蔽/图案化和/或自然选择性技术可被使用或否则利用来选择性地沉积层317。而且，其它实施例可受益于层317(例如)覆盖被暴露的多晶栅极区或被暴露的接地分接头区。如根据本公开内容将进一步认识到的，根据一些示例性实施例，高锗浓度(例如超过90原子％且一直到纯锗)和高掺杂剂浓度(例如超过2E20cm-3的硼)的组合可用于实现在p型源极和漏极区(以及低接触电阻是期望的其它区域，例如接地分接头区)中的明显更低的接触电阻。此外且如前面解释的，因为硼扩散被纯锗充分抑制，没有不利的SCE劣化使用随后的热退火来实现，尽管有接近沟道的高硼浓度(如果是可应用的)。从在接触表面处的锗的较高浓度也实现阻挡层的高度的降低。在一些示例性实施例中，超过95原子％且一直到纯锗(100原子％)的锗浓度可用于层317以实现这样的益处。
一旦锗层317被设置，该方法就以将III-V半导体材料层沉积(112)在晶体管结构的n型源极/漏极区上以及晶体管结构的锗覆盖的p型源极/漏极区之上继续。图2E示出根据一个示例性实施例的在n型和锗覆盖的p型源极/漏极区之上的III-V材料层319。如将认识到的，可非选择性地执行该沉积112，其中任何过量的III-V沉积随后从绝缘体322(以及栅极叠层，如果必要)的顶部被去除，如在图2F中最佳地示出的那样。在其它实施例中，可选择性地执行沉积112，其中III-V材料沉积只在n型源极/漏极区和锗覆盖的p型源极/漏极区上。例如，沉积112可包括具有Al、Ga、In和对绝缘体322的层(例如SiO2或SiN)有自然选择性的Sb、As、P的任何组合的高度n型(例如Si、Ge、S、Te等)掺杂的(>1E17cm-3)III-V层。在这样的选择性的情况下，层319将在n型SiGe或硅源极/漏极区和p型锗覆盖的源极/漏极区上生长，但将不在绝缘体表面(例如SiO2或SiN)上生长。
在一些实施例中，可在所有源极/漏极区(包括锗覆盖的p型区)上使用掺杂III-V材料的单一成分来进行沉积112。可选地，可在所有源极/漏极区(包括锗覆盖的p型区)上使用无掺杂III-V材料的单一成分来进行沉积112，其中无掺杂III-V材料具有小于0.5eV的带隙(例如InxGa1-xAs的带隙＝0.427eV，其中x＝.9)。在一些这样的小带隙情况下，带隙小于0.4eV(例如InAs的带隙＝0.36eV)。在又一些其它这样的情况下，带隙小于0.3eV。在又一些其它这样的情况下，带隙小于0.2eV(例如InSb的带隙＝0.17eV)。在又一些其它这样的情况下，带隙在例如在0.1eV和0.4eV，或0.1eV和0.25eV，或0.25eV和0.5eV，或0.15eV和0.35eV之间的范围内。然而，注意，III-V材料不需要被限制为具有小于0.5eV的带隙。这是因为III-V材料可使用原位掺杂、扩散掺杂或注入掺杂而被沉积，使得它被调整得适应于下层源极/漏极材料的掺杂类型。
在一些示例性实施例中，III-V材料层319被外延地沉积。根据一些特定的示例性实施例，III-V材料层319的厚度可以在例如50到的范围内，虽然其它实施例可具有其它层厚度，如根据本公开内容将显而易见的那样。用于形成p型锗层317的类似的沉积技术可用于使用III-V材料化合物(例如Al、Ga、In、P、As、Sb的组合和/或其前体)来形成n型III-V材料层319(例如CVD、RT-CVD、LP-CVD、UHV-CVD、PVD、ALD、MBE或GS-MBE)。在一个特定的这样的示例性实施例中，使用无掺杂锑化铟(InSb)来实现III-V材料层319。在另一实施例中，使用掺有Ge的GeAs来实现III-V材料层319以提供1E19原子/cm3或更高的代位Ge浓度，其导致大约5E-3欧姆-cm的电阻率(或大约200Mho/cm的对应的电导率)。在任何这样的实施例中，可以有载气，例如氢气、氮气或惰性气体(例如前体在1-20％的浓度下被稀释，平衡是载气)。在一些示例性情况下，可以有砷前体(例如砷化三氢或TBA)、镓前体(例如TMG)和/或铟前体(例如TMI)。也可以有蚀刻剂气体，例如基于卤素的气体，例如氯化氢(HCl)、氯(Cl)或溴化氢(HBr)。III-V半导体材料层319的基本沉积在使用在例如在300℃到700℃的范围内的沉积温度(例如300℃-500℃)和例如在1托到760托的范围内的反应器压力的宽范围条件下是可能的。载体和蚀刻剂中的每个可具有在10和300SCCM的范围内的流量(一般，需要不大于100SCCM的流量，但一些实施例可能受益于更高的流率)。在一个特定的示例性实施例中，在范围在100和1000SCCM之间的流率下执行沉积112。对于锗的原位掺杂，可使用稀释的锗烷或乙锗烷(例如锗烷可在10％的浓度下和范围在10和300SCCM之间的流率下被稀释在H2中)。
任何数量的掩蔽/图案化技术可用于进一步界定用以选择性地沉积层319的区。而且，其它实施例可受益于层319覆盖例如多晶栅极区或接地分接头区。如根据本公开内容将进一步认识到的，根据一些示例性实施例，III-V材料层319可用于实现在n型源极和漏极区(以及低接触电阻是期望的其它区域，例如接地尖端区)中的明显更低的接触电阻。
进一步参考图1A，该方法以回蚀(114)III-V材料沉积层以暴露在p型源极/漏极区之上的下层锗层317和在n型源极/漏极区之上的III-V材料层319的较小厚度继续。根据III-V沉积的选择性和粗糙度，这个回蚀工艺可包括初始平面化/抛光(例如CMP)以去除过量的III-V材料，随后进行蚀刻(可使用干和/或湿蚀刻)。这个回蚀工艺的示例性的所得到的结构在图2G中示出(图2F示出在图2G所示的蚀刻之前的可选的平面化步骤)。因为III-V沉积通常是粗糙的，它可被沉积到相对大的厚度并接着被使用例如干蚀刻回蚀以平面化且同时使III-V层319变薄。假设在p型源极/漏极区上的初始锗层317足够厚，则回蚀工艺产生在接触沟槽的底部处的被暴露表面，接触沟槽包括在n型源极/漏极区之上的III-V区域319和在p型源极/漏极区之上的锗区域317。因此，回蚀工艺114有效地利用高度差来使接触类型自对准。标准或定制接触部形成工艺流程可从这里继续进行以产生低电阻p和n接触部。
该方法接着以如下操作继续：在p型锗层317和n型III-V材料层319之上沉积(116)接触电阻减小金属并退火以及然后在p型锗层317和n型III-V材料层319中的每个上沉积(118)源极/漏极接触插塞。注意，在这样的实施例中，在n型源极/漏极区之上没有硅化物或锗化物。相反，任何反应均在III-V材料319和金属接触电阻减小层325之间，这通常在本文被称为III-V化合物。图2H示出接触电阻减小金属325，其在一些实施例中包括银、镍、铝、钛、金、金锗、镍铂或镍铝和/或其它这样的电阻减小金属或合金。其它实施例还可包括额外的层，例如在层317和层325之间和/或在层319和层325之间的粘附层，如果这么希望。图2I示出接触插塞金属329，其在一些实施例中包括铝或钨，虽然使用常规沉积工艺，可使用任何适当地导电的接触金属或合金，例如银、镍、铂、钛或其合金。工艺还可包括平面化/抛光以去除过量的金属并隔离每个接触沟槽与相邻的接触沟槽。在一些示例性情况下，具有在对应的源极/漏极区和接触电阻减小金属325之间的界面处配置有锗层317和III-V材料层319的源极/漏极的晶体管可展示小于100欧姆-um及在一些情况下小于90欧姆-um及在一些情况下小于80欧姆-um及在一些情况下小于75欧姆-um或更低的电阻率值。
图1B是根据本发明的另一实施例的用于形成具有低接触电阻的晶体管结构的方法。图3A到3C示出形成的可选的示例性结构。通常，这个方法类似于参考图1A和2A-I描述的方法，除了在绝缘体322的沉积之前执行在p型源极/漏极区上的锗材料层317的沉积以外。这实际上通过将锗材料沉积110移动到在源极/漏极界定104之后和在绝缘体沉积106之前而在图1B中示出。在图3A中示出在绝缘体沉积106之后的这个所得到的结构。注意在这个示例性实施例中锗层317如何完全覆盖每个所示的p型源极/漏极区，而不是仅仅被接触沟槽暴露的部分(如在图2D中最佳地示出的)。图3B示出在108处蚀刻接触沟槽之后的所得到的结构，而图3C示出分别在116和118处在n型III-V材料的沉积112和回蚀刻114之后以及在接触电阻减小金属325和金属接触插塞329的沉积之后的所得到的结构。如将认识到的，关于参考图1A讨论的示例性方法的类似部分的前面的相关讨论同样在这里可适用。
非平面配置
可例如使用FinFET或纳米线配置来实现非平面架构。FinFET是在半导体材料的薄条(通常被称为鳍状物)周围构建的晶体管。晶体管包括标准场效应晶体管(FET)节点，包括栅极、栅极电介质、源极区和漏极区。设备的导电沟道存在于在栅极电介质层之下的鳍状物的外侧上/内。具体地，电流沿着鳍状物的两个侧壁(垂直于衬底表面的侧面)以及沿着鳍状物的顶部(平行于衬底表面的一侧)流动。因为这样的配置的导电沟道本质上沿着鳍状物的三个不同的外部平面区域而存在，这样的FinFET设计有时被称为三栅极FinFET。其它类型的FinFET配置也是可用的，例如所谓的双栅极FinFET，其中导电沟道主要只沿着鳍状物的两个侧壁(而不是沿着鳍状物的顶部)而存在。纳米线晶体管(有时被称为栅绕式(gate-all-around)FET)被非常类似地配置，但代替鳍状物，纳米线(例如硅或SiGe或Ge纳米线)被使用，且栅极材料通常在所有侧面上围绕沟道区。根据特定的设计，纳米线晶体管具有例如四个有效栅极。
图4A-4E每个均示出根据本发明的一个实施例配置的示例性非平面架构的透视图。具体地，图4A-B每个均示出FinFET晶体管结构的透视图，而图4C-E示出示例性纳米线沟道晶体管结构。现在将依次讨论每个图。
如可看到的，图4A所示的示例性非平面配置实现有三栅极设备，其中每个三栅极设备包括具有从衬底600穿过隔离区620延伸的半导体主体或鳍状物660的衬底600。栅极电极640在鳍状物660的三个表面之上形成以形成三个栅极。硬掩模690在栅极电极640的顶部上形成。栅极间隔体670、680在栅极电极640的相对的侧壁处形成。P型源极区包括在凹进的源极界面650上和鳍状物660的一个侧壁上形成的外延区631a，且漏极区包括在凹进的源极界面650上和鳍状物660的相对侧壁(未示出)上形成的外延区631a。此外，n型源极区包括在凹进的源极界面650上和鳍状物660的一个侧壁上形成的外延区631b，且漏极区包括在凹进的源极界面650上和鳍状物660的相对侧壁(未示出)上形成的外延区631b。p型锗盖层641a沉积在源极/漏极区631a之上，且n型III-V盖层641b沉积在源极/漏极区631b之上。注意，锗和III-V材料盖层641a和641b分别可设置在对应的凹进(尖端)区中，但在其它实施例中只设置在源极/漏极区之上(而不是在凹进区中)。在一个实施例中，隔离区620是使用常规技术形成的浅沟槽隔离(STI)区，例如蚀刻衬底600以形成沟槽并接着将氧化物材料沉积在沟槽上以形成STI区。隔离区620可由任何适当的电介质/绝缘材料(例如SiO2)制成。关于衬底300的前面的讨论在这里同样可适用(例如衬底600可以是硅衬底，或XOI衬底例如SOI衬底，或多层衬底)。如根据本公开内容将认识到的，常规工艺和形成技术可用于制造FinFET晶体管结构。然而并且根据本发明的一个示例性实施例，可例如使用覆盖有p型锗层(用于641a)的原位p型硅或SiGe(用于631a)来实现p型源极/漏极区631a和相应的盖层641a，且可例如使用覆盖有n型III-V材料层(用于641b)的原位p型硅或SiGe(用于631b)来实现n型源极/漏极区631b和对应的盖层641b。如将进一步认识到的，注意，三栅极配置的替换方案是包括在鳍状物660的顶部上的电介质/隔离层的双栅极架构。进一步注意，图4A所示的源极/漏极区631(a和b)的示例性形状并不打算将所要求保护的本发明限制到任何特定的源极/漏极类型或形成过程，且其它源极/漏极形状(对于n和p两者而言)根据本公开内容将是明显的(例如圆形、正方形或矩形p和n型源极/漏极区可被实现)。
如将认识到的，使用替代工艺(例如蚀刻、外延沉积等)来形成图4A所示的源极/漏极区631(a和b)。然而，在其它实施例中，源极/漏极区631可以是由衬底600的材料本身形成的鳍状物660的部分，如在图4B中最佳地示出的。只示出一个源极/漏极区631，但很多这样的区可以用类似的方式(包括n型和p型S/D区)实现。盖层641以与前面参考图4A讨论的类似的方式(包括在n型S/D区之上的n型III-V材料和在p型S/D区之上的p型锗)沉积在源极/漏极区631之上。关于图4A提供的其它相关的讨论也同样在这里可适用，如将认识到的。
另一可选方案是可包括例如衬底600的材料的基底的纳米线沟道架构，纳米线660(例如硅或SiGe)生长或否则设置在衬底600的材料上，如在图4C中最佳地示出的。类似于图4B所示的鳍状物结构，纳米线660包括源极/漏极区631(只示出一个，但可实现多个这样的区，包括p型和n型，如前面解释的)。恰好如同鳍状物结构一样，源极/漏极区631可由衬底600的材料或者一种或多种替代材料(例如硅或SiGe)形成。材料641可设置在例如纳米线600的所有源极/漏极区631或纳米线660的仅仅一部分(例如除了在基底上的部分以外的所有部分)周围。如前面解释的，材料641可以是例如在n型S/D区之上的n型III-V材料和在p型S/D区之上的p型锗。图4D示出具有多个纳米线660(在这个示例性情况下是两个)的纳米线配置。如可看到的，一个纳米线660设置在衬底600的凹槽中，而另一纳米线660实际上在材料641的层中浮动。相应的源极/漏极区631被示出有垂直交叉影线，且可以是p型和/或n型源极/漏极区。图4E还示出具有多个纳米线660的纳米线配置，但在这个示例性情况下，非活性材料632在可使用各种常规技术执行的纳米线形成过程期间不从单独的纳米线去除，如根据本公开内容将认识到的。因此，一个纳米线660设置在衬底600的凹槽中，而其它纳米线660实际上位于材料632的顶部上。注意，穿过沟道的纳米线660是活性的，而632材料不是。641材料设置在纳米线660的所有其它被暴露表面周围。如前面解释的，相应的源极/漏极区631被示出有垂直交叉影线，且可以是p型和/或n型源极/漏极区。
示例性系统
图5示出根据本发明的示例性实施例配置的实现有一个或多个晶体管结构的计算系统100。如可看到的，计算系统1000容纳母板1002。母板1002可包括多个部件，包括但不限于处理器1004和至少一个通信芯片1006，其中每个均可物理地和电气地耦合到母板1002或否则集成在其中。如将认识到的，母板1002可例如是任何印刷电路板，不管是主板或安装在主板上的子板还是系统1000的唯一的板等。根据其应用，计算系统1000可包括可以或可以不物理地和电气地耦合到母板1002的一个或多个其它部件。这些其它部件可包括但不限于易失性存储器(例如DRAM)、非易失性存储器(例如ROM)、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机和大容量存储设备(例如硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等)。包括在计算系统1000中的任何部件可包括如本文所述的一个或多个晶体管结构(例如具有在n型源极/漏极区之上的n型III-V材料层和在p型源极/漏极区之上的p型锗以提供较低接触电阻/提高的导电性)。这些晶体管结构可例如用于实现板载处理器高速缓冲存储器或存储器阵列。在一些实施例中，多种功能可集成到一个或多个芯片中(例如，注意，通信芯片1006可以是处理器1004的部分或否则集成到处理器1004中)。
通信芯片1006实现用于数据往返于计算系统1000的传输的无线通信。术语“无线”及其派生词可用于描述可通过使用经由非固体介质的经调制电磁辐射来传递数据的电路、设备、系统、方法、技术、通信信道等。该术语并不暗示相关联的设备不包含任何电线，虽然在一些实施例中它们可以不包含电线。通信芯片1006可实现多种无线标准或协议中的任一个，包括但不限于Wi-Fi(IEEE802.11族)、WiMAX(IEEE802.16族)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算系统1000可包括多个通信芯片1006。例如，第一通信芯片1006可专用于较短距离无线通信(例如Wi-Fi和蓝牙)，而第二通信芯片1006可专用于较长距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算系统1000的处理器1004包括封装在处理器1004内的集成电路管芯。在本发明的一些实施例中，处理器1004的集成电路管芯包括使用具有在n型源极/漏极区之上的n型III-V材料层和在p型源极/漏极区之上的p型锗的一个或多个CMOS晶体管结构实现的板载非易失性电路，如在本文不同地描述的。术语“处理器”可以指处理例如来自寄存器和/或存储器的电子数据以将该电子数据转换成可存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的部分。
通信芯片1006还可包括封装在通信芯片1006内的集成电路管芯。根据一些这样的示例性实施例，通信芯片的集成电路管芯包括实现有如本文所述的一个或多个晶体管结构(例如芯片上处理器或存储器)的一个或多个设备。如根据本公开内容将认识到的，注意，多标准无线能力可直接集成到处理器1004中(例如其中任何芯片1006的功能集成到处理器1004中，而不是具有单独的通信芯片)。进一步注意，处理器1004可以是具有这样的无线能力的芯片组。简而言之，可使用任何数量的处理器1004和/或通信芯片1006。同样，任一个芯片或芯片组可具有集成在其中的多种功能。
在各种实现方式中，计算系统1000可以是膝上型计算机、上网本、笔记本计算机、智能电话、平板计算机、个人数字助理(PDA)、超移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录器。在另外的实现方式中，系统1000可以是处理数据或采用如本文所述的低接触电阻晶体管设备的任何其它电子设备(例如具有分别且如在本文中不同地描述的配置有p型锗和n型III-V材料层的中间层的p和n型设备)。
很多实施例将是明显的，且本文描述的特征可在任何数量的配置中组合。本发明的一个示例性实施例提供了一种半导体集成电路。所述集成电路包括具有多个沟道区的衬底和在每个沟道区之上的栅极电极，其中栅极电介质层设置在每个栅极电极和对应的沟道区之间。集成电路还包括在衬底中并相邻于对应的沟道区的p型源极/漏极区和在衬底中的并相邻于对应的沟道区的n型源极/漏极区。集成电路还包括在p型源极/漏极区的至少一部分上的p型锗层和在n型源极/漏极区的至少一部分上的n型III-V半导体材料层。集成电路还包括在p型锗层和n型III-V半导体材料层中的每个上的金属接触部。在一些情况下，n型III-V半导体材料层是无掺杂的。在一些情况下，n型III-V半导体材料层具有小于0.5eV的带隙。在一些情况下，n型III-V半导体材料层具有小于0.2eV的带隙。在其它情况下，n型III-V半导体材料层是掺杂的。在一些这样的情况下，n型III-V半导体材料层掺杂有一种或多种两性掺杂剂。在一个这样的情况下，n型III-V半导体材料层以大于1E18原子/cm3的代位浓度掺杂有一种或多种两性掺杂剂。在一些情况下，p型锗层掺杂有硼。在一个这样的情况下，硼浓度超过1E20/cm-3。在一些情况下，设备被实现有平面晶体管架构。在其它情况下，设备被实现有非平面晶体管架构。在一些这样的情况下，非平面晶体管架构包括FinFET晶体管和/或纳米线晶体管中的至少一个。在一些情况下，p型和n型源极/漏极区包括硅、锗或其合金。本发明的另一实施例包括电子设备，其包括具有一个或多个集成电路的印刷电路板，如在本段中不同地定义的。在一个这样的情况下，一个或多个集成电路包括通信芯片和/或处理器中的至少一个。在另一这样的情况下，设备是计算设备。
本发明的另一实施例提供设备，其包括具有多个沟道区的含硅衬底和在每个沟道区之上的栅极电极，其中栅极电介质层设置在每个栅极电极和对应的沟道区之间。设备还包括在衬底中并相邻于对应的沟道区的p型源极/漏极区和在衬底中并相邻于对应的沟道区的n型源极/漏极区，p型和n型源极/漏极区包括硅、锗或其合金。设备还包括在p型源极/漏极区的至少一部分上的p型锗层和在n型源极/漏极区的至少一部分上的n型III-V半导体材料层。设备还包括在p型锗层和n型III-V半导体材料层中的每个上的金属接触部。在一些情况下，n型III-V半导体材料层是无掺杂的。在其它情况下，n型III-V半导体材料层是掺杂的。在一个这样的情况下，n型III-V半导体材料层掺杂有一种或多种两性掺杂剂。在另一这样的情况下，n型III-V半导体材料层以大于1E18原子/cm3的代位浓度掺杂有一种或多种两性掺杂剂。在一些情况下，n型III-V半导体材料层具有小于0.5eV的带隙。在一些情况下，p型锗层掺杂有硼。在一个这样的情况下，硼浓度超过1E20/cm-3。
本发明的另一实施例提供用于形成半导体设备的方法。该方法包括提供具有多个沟道区的衬底，并提供在每个沟道区之上的栅极电极，其中栅极电介质层设置在每个栅极电极和对应的沟道区之间。该方法还包括：提供在衬底中并相邻于对应的沟道区的p型源极/漏极区，以及提供在衬底中并相邻于对应的沟道区的n型源极/漏极区。该方法还包括提供在p型源极/漏极区的至少一部分上的p型锗层，并提供在n型源极/漏极区的至少一部分上，并且在其上具有所述p型锗层的所述p型源极/漏极区之上的n型III-V半导体材料层。该方法还包括回蚀n型III-V半导体材料层以暴露p型源极/漏极区之上的下层p型锗并使在n型源极/漏极区之上的n型III-V半导体材料层变薄。该方法还包括在p型锗层和n型III-V半导体材料层中的每个上提供金属接触部。
为了说明和描述的目的提供了本发明的示例性实施例的前述描述。并非意在是无遗漏的或将本发明限制到所公开的精确形式。根据本公开内容，很多修改和变化是可能的。意图是本发明的范围并不由本具体实施方式部分限制而是由所附权利要求限制。

Claims (25)

1.一种半导体集成电路，包括：
具有多个沟道区的衬底；
在每个沟道区之上的栅极电极，其中栅极电介质层设置在每个栅极电极和对应的沟道区之间；
在所述衬底中并相邻于对应的沟道区的p型源极/漏极区；
在所述衬底中并相邻于对应的沟道区的n型源极/漏极区；
在所述p型源极/漏极区的至少一部分上的p型锗层：
在所述n型源极/漏极区的至少一部分上的n型III-V半导体材料层；以及
在所述p型锗层和所述n型III-V半导体材料层中的每个层上的金属接触部。
2.如权利要求1所述的集成电路，其中所述n型III-V半导体材料层是无掺杂的。
3.如权利要求1或2所述的集成电路，其中所述n型III-V半导体材料层具有小于0.5eV的带隙。
4.如前述权利要求中的任一项所述的集成电路，其中所述n型III-V半导体材料层具有小于0.2eV的带隙。
5.如权利要求1所述的集成电路，其中所述n型III-V半导体材料层是掺杂的。
6.如权利要求5所述的集成电路，其中所述n型III-V半导体材料层掺杂有一种或多种两性掺杂剂。
7.如权利要求6所述的集成电路，其中所述n型III-V半导体材料层以大于1E18原子/cm3的代位浓度掺杂有一种或多种两性掺杂剂。
8.如前述权利要求中的任一项所述的集成电路，其中所述p型锗层掺杂有硼。
9.如权利要求8所述的集成电路，其中所述硼浓度超过1E20/cm-3。
10.如前述权利要求中的任一项所述的集成电路，其中所述设备被实现有平面晶体管架构。
11.如前述权利要求中的任一项所述的集成电路，其中所述设备被实现有非平面晶体管架构。
12.如权利要求11所述的集成电路，其中所述非平面晶体管架构包括FinFET晶体管和/或纳米线晶体管的至少其中之一。
13.如前述权利要求中的任一项所述的集成电路，其中所述p型和n型源极/漏极区包括硅、锗或其合金。
14.一种电子设备，包括：
具有一个或多个如在前述权利要求中的任一项中限定的集成电路的印刷电路板。
15.如权利要求14所述的电子设备，其中所述一个或多个集成电路包括通信芯片和/或处理器的至少其中之一。
16.如权利要求14或15所述的电子设备，其中所述设备是计算设备。
17.一种设备，包括：
具有多个沟道区的含硅衬底；
在每个沟道区之上的栅极电极，其中栅极电介质层设置在每个栅极电极和对应的沟道区之间；
在所述衬底中并相邻于对应的沟道区的p型源极/漏极区，所述p型源极/漏极区包括硅、锗或其合金；
在所述衬底中并相邻于对应的沟道区的n型源极/漏极区，所述n型源极/漏极区包括硅、锗或其合金；
在所述p型源极/漏极区的至少一部分上的p型锗层；
在所述n型源极/漏极区的至少一部分上的n型III-V半导体材料层；以及
在所述p型锗层和所述n型III-V半导体材料层中的每个层上的金属接触部。
18.如权利要求17所述的设备，其中所述n型III-V半导体材料层是无掺杂的。
19.如权利要求17所述的设备，其中所述n型III-V半导体材料层是掺杂的。
20.如权利要求19所述的设备，其中所述n型III-V半导体材料层掺杂有一种或多种两性掺杂剂。
21.如权利要求20所述的设备，其中所述n型III-V半导体材料层以大于1E18原子/cm3的代位浓度掺杂有一种或多种两性掺杂剂。
22.如权利要求17到21中的任一项所述的设备，其中所述n型III-V半导体材料层具有小于0.5eV的带隙。
23.如权利要求17到22中的任一项所述的设备，其中所述p型锗层掺杂有硼。
24.如权利要求23所述的设备，其中所述硼浓度超过1E20/cm-3。
25.一种用于形成半导体设备的方法，包括：
提供具有多个沟道区的衬底；
在每个沟道区之上提供栅极电极，其中栅极电介质层设置在每个栅极电极和对应的沟道区之间；
在所述衬底中并相邻于对应的沟道区提供p型源极/漏极区；
在所述衬底中并相邻于对应的沟道区提供n型源极/漏极区；
在所述p型源极/漏极区的至少一部分上提供p型锗层；
在所述n型源极/漏极区的至少一部分上并且在其上具有所述p型锗层的所述p型源极/漏极区之上提供n型III-V半导体材料层；
回蚀所述n型III-V半导体材料层以暴露所述p型源极/漏极区之上的下层p型锗并使在所述n型源极/漏极区之上的所述n型III-V半导体材料层变薄；以及
在所述p型锗层和所述n型III-V半导体材料层中的每个层上提供金属接触部。
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