CN109585301A - 用于包括具有低接触电阻的衬垫硅化物的集成电路制作的工艺 - Google Patents

用于包括具有低接触电阻的衬垫硅化物的集成电路制作的工艺 Download PDF

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CN109585301A
CN109585301A CN201910006565.3A CN201910006565A CN109585301A CN 109585301 A CN109585301 A CN 109585301A CN 201910006565 A CN201910006565 A CN 201910006565A CN 109585301 A CN109585301 A CN 109585301A
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transistor
doped layer
metal
drain region
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CN109585301B (zh
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柳青
W·克里梅尔
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STMicroelectronics lnc USA
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Abstract

本公开涉及一种用于包括具有低接触电阻的衬垫硅化物的集成电路制作的工艺。一种集成电路包括支撑具有源极区域和漏极区域的晶体管的衬底。在晶体管的源极区域和漏极区域上存在高掺杂浓度德尔塔掺杂层。成组的接触延伸通过覆盖晶体管的金属前电介质层。硅化物区域被提供在成组的接触的底部处。硅化物区域通过在接触的底部处存在的金属与晶体管的源极区域和漏极区域上的高掺杂浓度德尔塔掺杂层之间的自对准硅化反应形成。

Description

用于包括具有低接触电阻的衬垫硅化物的集成电路制作的 工艺
本申请是于2015年3月31日提交的、申请号为201510149770.7、发明名称为“用于包括具有低接触电阻的衬垫硅化物的集成电路制作的工艺”的中国发明专利申请的分案申请。
技术领域
本发明涉及集成电路的制作，并且更具体地涉及用于形成源极-漏极区域的具有低接触电阻的硅化物接触的工艺技术。
背景技术
本领域技术人员认识到形成晶体管器件的源极-漏极区域的低电阻接触的重要性。低电阻连接通常由硅化物支持。然而，随着晶体管大小继续向下按比例缩小，接触面积降低并且接触电阻涉及增加。因此，在本领域中有对随工艺几何结构缩小将支持形成更低接触电阻的工艺技术的需要。
发明内容
在一个实施例中，一种集成电路包括：具有源极区域、漏极区域和栅极的nMOS晶体管；具有源极区域、漏极区域和栅极的pMOS晶体管；在pMOS晶体管的源极区域和漏极区域上的高掺杂浓度德尔塔掺杂层；覆盖nMOS晶体管和pMOS晶体管的金属前(pre-metal)电介质层；延伸通过金属前电介质层到nMOS晶体管的源极区域和漏极区域的第一组接触；延伸通过金属前电介质层到pMOS晶体管的源极区域和漏极区域的第二组接触；通过金属与形成nMOS晶体管的源极区域和漏极区域的第一半导体材料之间的自对准硅化反应形成在第一组接触的底部处的第一硅化物区域；以及通过金属与形成pMOS晶体管的源极区域和漏极区域上的高掺杂浓度德尔塔掺杂层之间的自对准硅化反应形成在第二组接触的底部处的第二硅化物区域。
在一个实施例中，一种工艺包括：从第一半导体材料形成用于nMOS晶体管的源极区域和漏极区域；从第二半导体材料形成用于pMOS晶体管的源极区域和漏极区域；在第二半导体材料上沉积高掺杂浓度德尔塔掺杂层；沉积上置金属前电介质层；形成延伸通过金属前电介质层到nMOS晶体管的源极区域和漏极区域的第一组开口；形成延伸通过金属前电介质层到pMOS晶体管的源极区域和漏极区域的第二组开口；在第一组开口和第二组开口的底部处沉积金属；以及加热以发起自对准硅化反应。该自对准硅化反应被提供在：金属与第一半导体材料之间以在nMOS晶体管的源极和漏极区域上形成第一硅化物区域；以及金属与高掺杂浓度德尔塔掺杂层之间以在pMOS晶体管的源极和漏极区域上形成第二硅化物区域。
在一个实施例中，一种集成电路，包括：衬底；具有由所述衬底支撑的源极区域和漏极区域的晶体管；在晶体管的源极区域和漏极区域上的高掺杂浓度德尔塔掺杂层；覆盖晶体管的金属前电介质层；延伸通过金属前电介质层到晶体管的源极区域和漏极区域的成组的接触；通过金属与晶体管的源极区域和漏极区域上的高掺杂浓度德尔塔掺杂层之间的自对准硅化反应形成在成组的接触的底部处的硅化物区域。
附图说明
为了更好地理解实施例，现在将仅通过示例的方式参考附图，其中：
图1至图10示出了根据一个实施例的工艺步骤；
图11至图18示出了根据一个实施例的工艺步骤；
图19至图26示出了根据一个实施例的工艺步骤；以及
图27至图28是图示了鳍配置的截面。
具体实施方式
现在参考示出用于制作集成电路的工艺步骤的图1至图10。
图1示出了集成电路衬底10。衬底10包括如本领域中已知的包括下置轻掺杂衬底层12、中间掩埋氧化物层14和上置半导体层16的绝缘体上硅(SOI)衬底。更具体地，上置半导体层可以被完全耗尽(即，本征半导体)，并且因此衬底10是完全耗尽型SOI衬底(FD-SOI)类型的。半导体层16可以例如包括硅或者硅锗。下置轻掺杂衬底层12可以由硅形成并且具有100-800μm的厚度。中间掩埋氧化物层14可以具有10-30nm的厚度。上置半导体层16可以具有4-10nm的厚度。
现在参考图2，衬底10已经由浅沟槽隔离结构18(例如，由填充有氧化硅(SiO或者SiO2)材料的沟槽形成)分隔成用于支撑至少一个nMOS晶体管器件的第一有源区域20和用于支撑至少一个pMOS晶体管器件的第二有源区域22。虽然STI结构18被示出完全穿透衬底10，但是将要理解的是结构18可以备选地部分地穿透衬底10并且终止在下置轻掺杂衬底层12内。
在一个实施例中，第一有源区域20中的上置半导体层16可以包括硅(Si)半导体材料，而第二有源区域20中的上置半导体材料层16可以包括硅锗(SiGe)半导体材料。对于本领域技术人员众所周知的技术是可用的以在SOI衬底中产生硅和硅锗上层区域。
在一个实施例中，STI结构18的上表面被定位在上置半导体层16的上表面上方。两个表面之间的偏移可以例如具有5-20nm的厚度。在备选实施例中，STI结构18和上置半导体层16的上表面是共面的。
现在参考图3。虚设栅极堆叠30被形成在每个区域中的上置半导体层16的上表面的顶上。栅极堆叠30包括虚设栅极结构32和侧壁间隔物34。用于形成栅极堆叠30的工艺对于本领域技术人员是众所周知的。
在一个实施例中，虚设栅极结构32由多晶硅材料形成。多晶硅材料可以按照针对给定应用所需而被掺杂。化学气相沉积(CVD)工艺可以用于在层中沉积多晶硅材料。如本领域中已知的合适的光刻工艺然后被用于图形化多晶硅材料层并且形成虚设栅极结构32。
在一个实施例中，侧壁间隔物34可以由包括但不限于氧化物层或者氮化物层的一层或者多层形成。侧壁间隔物34所图示的形状不一定表示间隔物的实际形状。特定形状没有确保栅极结构32的横向表面被覆盖那样重要。原子层沉积(ALD)工艺可以用于共形沉积用于侧壁间隔物34的材料，其中刻蚀被执行以从水平表面去除材料，以便留下栅极结构32的侧壁上的材料。
虽然未明确示出，但是帽层对于每个栅极堆叠30而言可以被提供在栅极结构32之上。
现在参考图4。掩模材料层40被提供在第二区域22之上。掩模材料层40覆盖第二区域22中的栅极堆叠30和上置半导体层16。掩模材料层40可以包括例如具有2-5nm厚度的氮化硅(SiN)或者硅硼碳氮(SiBCN)材料层。原子层沉积工艺可以用于沉积层40。
使用如本领域已知的外延生长工艺，从栅极堆叠30的每侧上的第一区域20中的上置半导体层16的上表面生长半导体区域42。区域42形成用于第一区域20中的nMOS晶体管器件的抬升的源极-漏极(RSD)区域。用于外延生长区域42的工艺可以包括盐酸(HCl)刻蚀以确保选择性。区域42的厚度可以例如包括10-30nm。用于区域42的材料可以例如包括硅(Si)或者碳化硅(SiC)。区域42可以根据例如应用磷(P)或者砷(As)被合适地掺杂。掺杂可以用外延生长原位完成或者通过注入完成。
现在参考图5，掩模材料层40被去除以暴露在栅极堆叠30每侧上的第二区域22中的上置半导体层16的上表面。如本领域已知的干法或者湿法刻蚀工艺可以例如用于去除层40。
另外，第一区域20中的区域42和栅极堆叠30由掩模层50覆盖。掩模材料层50可以包括例如具有2-5nm厚度的氮化硅(SiN)材料层。原子层沉积工艺可以用于沉积层50。
使用如本领域已知的外延生长工艺，从在栅极堆叠30每侧上的第二区域22中的上置半导体层16的上表面生长半导体区域52。区域52形成用于第二区域22中的pMOS晶体管器件的抬升的源极-漏极(RSD)区域。用于外延生长区域52的工艺可以包括盐酸(HCl)刻蚀以确保选择性。区域52的厚度可以例如包括10-30nm。用于区域52的材料可以例如包括硅锗(SiGe)。区域可以根据应用例如利用硼(B)合适地掺杂。掺杂可以利用外延生长原位完成或者通过注入完成。在一个实施例中，原位硼掺杂外延生长的RSD可以具有4×1020至6×1020cm-2的硼浓度。
使用对于本领域技术人员众所周知的原子层沉积(ALD)技术，高硼(B)浓度德尔塔掺杂硅锗(SiGe)的层60被沉积在区域52的表面上。该过程的结果在图6中示出。在一个实施例中，层60可以具有2×1022cm-2的硼浓度。有利地，这是区域52的浓度的三倍以上。
现在参考图7。栅极结构32(和存在的任何帽)已经从侧壁间隔物34之间去除并且由栅极氧化物70、金属栅极电极72和自对准帽74取代。
在一个实施例中，栅极氧化物70可以包括氧化硅(SiO或者SiO2)材料或者作为替代可以包括诸如氧化铪(HfO2)之类的高K电介质材料。氧化物70可以具有的厚度。原子层沉积工艺可以用于沉积氧化物70。
在一个实施例中，金属栅极电极72由结合后栅极制作技术使用的诸如钨之类的任何合适的金属材料形成，本领域技术人员已知后栅极制作技术用于形成金属栅极电极。金属材料可以使用化学气相沉积工艺进行沉积。在一个实施例中，金属栅极电极72可以包括由例如TiN或者碳化钛(TiC)形成的功函数金属(WFM)层。
在一个实施例中，栅极帽74可以由氮化硅(SiN)或者硅硼碳氮(SiBCN)材料制成。栅极帽74可以具有20-50nm的厚度。高密度等离子体(HDP)辅助的沉积工艺可以用于沉积栅极帽材料。
另外，提供电介质层76以覆盖衬底、抬升的源极-漏极结构、栅极堆叠结构等。电介质层76可以包括例如氧化硅(SiO或者SiO2)材料。电介质层76使用化学气相沉积工艺进行沉积。因为沉积是共形的，所以执行用来去除过量材料并且对层76的顶表面(与栅极堆叠和帽74的顶部共面)进行平整化的工艺。该工艺可以包括例如化学机械抛光(CMP)操作。
参考图8，附加的电介质层80被提供在电介质层76的平整化顶表面的顶上。在用氧化物70、金属栅极72和帽74取代栅极堆叠的形成完成之后沉积该层80。电介质层80可以包括例如氧化硅(SiO或者SiO2)材料。电介质层80使用物理气相沉积(PVD)或者化学气相沉积工艺进行沉积。如果必要，层80的顶表面也可以使用例如CMP被平整化。
层76和层80包括用于集成电路的金属前电介质(PMD)层。
现在参考图9。开口90被形成在抬升的源极-漏极区域之上并且延伸通过PMD层以暴露区域42的顶表面和德尔塔掺杂硅锗(SiGe)层60(在区域52之上)的顶表面。开口可以例如使用掩模和各向异性干法刻蚀工艺形成。
共形阻挡金属层92然后被沉积在每个开口90的侧壁上以及有源区域20中的区域42的顶表面和有源区域22中的德尔塔掺杂硅锗(SiGe)层60的顶表面上。阻挡层92可以包括例如氮化钛(TiN)材料。阻挡层92使用化学气相沉积工艺被沉积。
然后使用沉积工艺形成由例如钨制成的上置金属层的沉积物94。例如使用化学气相沉积(CVD)工艺形成钨沉积物94。沉积物94基本上完全填充开口90中的每个开口。沉积物94可以例如包括共形沉积物，包括覆盖PMD层的顶表面的部分。在这种情况下，执行用来去除过量钨材料并且平整化沉积物94的顶表面(与PMD层的顶表面共面)的工艺。该工艺可以包括例如化学机械抛光(CMP)操作。
然后执行自对准硅化工艺以在钨沉积物94与有源区域20中的区域42之间形成第一低电阻膜100，并且在钨沉积物94与有源区域22中的区域52之间形成第二低电阻膜102。如本领域技术人员已知的将衬底加热到合适的温度引起TiN层92与区域42的硅材料反应，以形成用于第一低电阻膜100的第一硅化物并且引起TiN层92与德尔塔掺杂硅锗(SiGe)层60反应以形成用于第二低电阻膜102的第二硅化物。结果在图10中示出。
集成电路的完成涉及本领域技术人员众所周知的后段制程(BEOL)处理技术的执行。
现在参考示出了用于制作集成电路的工艺步骤的图11至图18。
图11示出了集成电路衬底10。衬底10包括如本领域中已知的包括下置轻掺杂衬底层12、中间掩埋氧化物层14和上置半导体层16的绝缘体上硅(SOI)衬底。更具体地，上置半导体层可以被完全耗尽(即，本征半导体)，并且因此衬底10是完全耗尽型SOI衬底(FD-SOI)。半导体层16可以例如包括硅或者硅锗。下置轻掺杂衬底层12可以由硅制成并且具有100-800μm的厚度。中间掩埋氧化物层14可以具有20-200nm的厚度。上置半导体层16可以具有20-50nm的厚度。
现在参考图12，衬底10已经由浅沟槽隔离(STI)结构18(例如，由填充有氧化硅(SiO或者SiO2)材料的沟槽形成)分隔为用于支撑至少一个nMOS FINFET晶体管器件的第一有源区域20和用于支撑至少一个pMOS FINFET晶体管器件的第二有源区域22。虽然STI结构18被示出完全穿透衬底10，但是将要理解的是结构18可以备选地部分地穿透衬底10并且终止在下置轻掺杂衬底层12内。
使用如本领域中已知的外延生长工艺，从第一区域20中的上置半导体层16的上表面生长半导体区域120。半导体区域120例如由硅(Si)或者碳化硅(SiC)形成。区域120可以根据应用例如利用磷(P)或者砷(As)被合适地掺杂。掺杂可以利用外延生长原位完成或者可以通过注入完成。
此外，使用如本领域中已知的外延生长工艺，从第二区域22中的上置半导体层16的上表面生长半导体区域122。半导体区域122例如由硅锗(SiGe)形成。区域122可以根据应用例如利用硼(B)被合适地掺杂。掺杂可以利用外延生长原位完成或者可以通过注入完成。在一个实施例中，原位硼掺杂外延生长区域122可以具有4×1020cm-2至6×1020cm-2的硼浓度。
区域120和区域122例如使用如本领域中已知的光刻工艺以在第一区域20之上的第一鳍构件124和在第二区域22之上的第二鳍构件126的形状(见，图27)被图形化。在该配置中，每个鳍构件包括源极区域S、沟道区域C和漏极区域D。
现在参考图13。虚设栅极堆叠130被形成在每个区域中的上置半导体层16的上表面的顶上。栅极堆叠130包括虚设栅极结构132(见，图27)和侧壁间隔物134。每个虚设栅极堆叠130跨立在沟道区域C的区域中的其对应的鳍构件124、126之上。用于形成栅极堆叠130的工艺对于本领域技术人员是众所周知的。
在一个实施例中，虚设栅极结构132由多晶硅材料形成。多晶硅材料可以按照针对给定应用所需而被掺杂。化学气相沉积工艺可以用于在层中沉积多晶硅材料。如本领域中已知的合适的光刻工艺然后用于图形化多晶硅材料层并且形成虚设栅极结构132。
在一个实施例中，侧壁间隔物134可以由包括但不限于氧化物层或者氮化物层的一层或者多层形成。侧壁间隔物134的所图示的形状不一定表示间隔物的实际形状。特定形状没有确保栅极结构132的横向表面被覆盖那样重要。原子层沉积工艺可以用于沉积用于侧壁间隔物134的材料，其中刻蚀被执行以从水平表面去除材料，以便留下栅极结构132的侧壁上的材料。
虽然未明确示出，但是绝缘帽对于每个栅极堆叠130而言可以被提供在栅极结构132之上。
现在参考图14。掩模材料层140被提供在第一区域20之上。掩模材料层140覆盖第一区域20中的栅极堆叠130、第一鳍构件124(由层120构成)以及上置半导体层16。掩模材料层140可以包括例如具有2-5nm厚度的氮化硅(SiN)或者硅硼碳氮(SiBCN)材料层。原子层沉积工艺可以用于沉积层140。
使用对于本领域技术人员众所周知的原子层沉积(ALD)技术，高硼(B)浓度德尔塔掺杂硅锗(SiGe)的层142被沉积在用于第二鳍构件126的区域122的表面上。在一个实施例中，层142可以具有2×1022cm-2的硼浓度。有利地，这是区域122的浓度的三倍以上。
现在参考图15。栅极结构132(和任何帽，如果存在)已经从侧壁间隔物134之间去除并且由栅极氧化物170、金属栅极电极172和自对准帽174取代。
在一个实施例中，栅极氧化物170可以包括氧化硅(SiO或者SiO2)材料或者作为替代可以包括诸如氧化铪(HfO2)之类的高K电介质材料。氧化物170可以具有的厚度。原子层沉积工艺可以用于沉积氧化物170。
在一个实施例中，金属栅极电极172由结合后栅极制作技术使用的诸如钨之类的任何合适的金属材料形成，本领域技术人员已知后栅极制作技术用于形成金属栅极电极。金属材料可以使用化学气相沉积工艺进行沉积。在一个实施例中，金属栅极电极172可以包括由例如TiN或者碳化钛(TiC)形成的功函数金属(WFM)层。
在一个实施例中，栅极帽174可以由氮化硅(SiN)或者硅硼碳氮(SiBCN)材料制成。栅极帽174可以具有20-50nm的厚度。高密度等离子体辅助的沉积工艺可以用于沉积栅极帽材料。
另外，提供电介质层176以覆盖衬底、抬升的源极-漏极结构、栅极堆叠结构等。电介质层176可以包括例如氧化硅(SiO或者SiO2)材料。电介质层176使用化学气相沉积工艺进行沉积。因为沉积是共形的，所以执行用来去除过量材料并且对层176的顶表面(与栅极堆叠和帽174的顶部共面)进行平整化的工艺。该工艺可以包括例如化学机械抛光(CMP)操作。
参考图16，附加的电介质层180被提供在电介质层176的平整化顶表面的顶上。在用氧化物170、金属栅极172和帽174取代栅极堆叠的形成完成之后沉积该层180。电介质层180可以包括例如氧化硅(SiO或者SiO2)材料。电介质层180使用物理气相沉积或者化学气相沉积工艺进行沉积。如果必要，层180的顶表面也可以使用例如CMP被平整化。
层176和层180包括用于集成电路的金属前电介质(PMD)层。
现在参考图17。开口90被形成在抬升的源极-漏极区域之上并且延伸通过PMD层以暴露鳍124的顶表面和德尔塔掺杂硅锗(SiGe)层142(在鳍126之上)的顶表面。开口可以例如使用掩模和各向异性干法刻蚀工艺形成。
共形阻挡金属层92然后被沉积在每个开口90的侧壁上以及在有源区域20中的区域42的顶表面和有源区域22中的德尔塔掺杂硅锗(SiGe)层142的顶表面上。阻挡层92可以包括例如氮化钛(TiN)材料。阻挡层92使用化学气相沉积工艺被沉积。
然后使用沉积工艺形成由例如钨制成的上置金属层的沉积物94。例如使用化学气相沉积(CVD)工艺形成钨沉积物94。沉积物94基本上完全填充开口90中的每个开口。沉积物94可以例如包括共形沉积物，包括覆盖PMD层的顶表面的部分。在这种情况下，执行用来去除过量钨材料并且平整化沉积物94的顶表面(与PMD层的顶表面共面)的工艺。该工艺可以包括例如化学机械抛光(CMP)操作。
然后执行自对准硅化工艺以在钨沉积物94与有源区域20中的鳍124之间形成第一低电阻膜100，并且在钨沉积物94与有源区域22中的鳍126之间形成第二低电阻膜102。如本领域技术人员已知的将衬底加热到合适的温度引起TiN层92与鳍124的硅材料反应，以形成用于第一低电阻膜100的第一硅化物并且引起TiN层92与德尔塔掺杂硅锗(SiGe)层142(在鳍126上)反应以形成用于第二低电阻膜102的第二硅化物。结果在图18中示出。
集成电路的完成涉及本领域技术人员众所周知的后段制程(BEOL)处理技术的执行。
现在参考示出了用于制作集成电路的工艺步骤的图19至图26。
作为使用SOI衬底(图11)的备选，可以作为替代使用体衬底10’，如图19所示。体衬底10’包括半导体材料(诸如硅或者硅锗)层16’。衬底10’可以按照针对应用所需合适地掺杂。
现在参考图20，衬底10’已经由浅沟槽隔离(STI)结构18(例如，由填充有氧化硅(SiO或者SiO2)材料的沟槽形成)分隔为用于支撑至少一个nMOS FINFET晶体管器件的第一有源区域20和用于支撑至少一个pMOS FINFET晶体管器件的第二有源区域22。虽然STI结构18被示出完全穿透衬底10’，但是将要理解的是结构18可以备选地部分地穿透衬底10’并且终止在层16’内。
使用如本领域中已知的外延生长工艺，从第一区域20中的上置半导体层16的上表面生长半导体区域120。半导体区域120例如由硅(Si)或者碳化硅(SiC)形成。区域120可以根据应用例如利用磷(P)或者砷(As)被合适地掺杂。掺杂可以利用外延生长原位完成或者可以通过注入完成。
此外，使用如本领域中已知的外延生长工艺，从第二区域22中的上置半导体层16的上表面生长半导体区域122。半导体区域122例如由硅锗(SiGe)形成。区域122可以根据应用例如利用硼(B)被合适地掺杂。掺杂可以利用外延生长原位完成或者可以通过注入完成。在一个实施例中，原位硼掺杂外延生长区域122可以具有4×1020cm-2至6×1020cm-2的硼浓度。
区域120和区域122例如随后使用如本领域中已知的光刻工艺以在第一区域20之上的第一鳍构件124和在第二区域22之上的第二鳍构件126的形状(见，图28)被图形化。在该配置中，每个鳍构件包括源极区域S、沟道区域C和漏极区域D。
现在参考图21。虚设栅极堆叠130被形成在每个区域中的上置半导体层16的上表面的顶上。栅极堆叠130包括虚设栅极结构132(见，图28)和侧壁间隔物134。每个虚设栅极堆叠130跨立在沟道区域C的区域中的其对应的鳍构件124、126之上。用于形成栅极堆叠130的工艺对于本领域技术人员是众所周知的。
在一个实施例中，虚设栅极结构132由多晶硅材料形成。多晶硅材料可以按照针对给定应用所需而被掺杂。化学气相沉积工艺可以用于在层中沉积多晶硅材料。如本领域中已知的合适的光刻工艺然后用于图形化多晶硅材料层并且形成虚设栅极结构132。
在一个实施例中，侧壁间隔物134可以由包括但不限于氧化物层或者氮化物层的一层或者多层形成。侧壁间隔物134的所图示的形状不一定表示间隔物的实际形状。特定形状没有确保栅极结构132的横向表面被覆盖那样重要。原子层沉积工艺可以用于沉积用于侧壁间隔物134的材料，其中刻蚀被执行以从水平表面去除材料，以便留下栅极结构132的侧壁上的材料。
现在参考图22。掩模材料层140被提供在第一区域20之上。掩模材料层140覆盖第一区域20中的栅极堆叠130、第一鳍构件124以及上置半导体层16。掩模材料层140可以包括例如具有2-5nm厚度的氮化硅(SiN)或者硅硼碳氮(SiBCN)材料层。原子层沉积工艺可以用于沉积层140。
使用对于本领域技术人员众所周知的原子层沉积(ALD)技术，高硼(B)浓度德尔塔掺杂硅锗(SiGe)的层142被沉积在用于第二鳍构件126的区域122的表面上。在一个实施例中，层142可以具有2×1022cm-2的硼浓度。有利地，这是区域122的浓度的三倍以上。
现在参考图23。栅极结构132已经从侧壁间隔物134之间去除并且由栅极氧化物170、金属栅极电极172和自对准帽174取代。
在一个实施例中，栅极氧化物170可以包括氧化硅(SiO或者SiO2)材料或者作为替代可以包括诸如氧化铪(HfO2)之类的高K电介质材料。氧化物170可以具有的厚度。原子层沉积工艺可以用于沉积氧化物170。
在一个实施例中，金属栅极电极172由结合后栅极制作技术使用的诸如钨之类的任何合适的金属材料形成，本领域技术人员已知后栅极制作技术用于形成金属栅极电极。金属材料可以使用化学气相沉积工艺进行沉积。在一个实施例中，金属栅极电极172可以包括由例如TiN或者碳化钛(TiC)形成的功函数金属(WFM)层。
在一个实施例中，栅极帽174可以由氮化硅(SiN)或者硅硼碳氮(SiBCN)材料制成。栅极帽174可以具有20-50nm的厚度。高密度等离子体辅助的沉积工艺可以用于沉积栅极帽材料。
另外，提供电介质层176以覆盖衬底、抬升的源极-漏极结构、栅极堆叠结构等。电介质层176可以包括例如氧化硅(SiO或者SiO2)材料。电介质层176使用化学气相沉积工艺进行沉积。因为沉积是共形的，所以执行用来去除过量材料并且对层176的顶表面(与栅极堆叠和帽174的顶部共面)进行平整化的工艺。该工艺可以包括例如化学机械抛光(CMP)操作。
参考图24，附加的电介质层180被提供在电介质层176的平整化顶表面的顶上。在用氧化物170、金属栅极172和帽174取代栅极堆叠的形成完成之后沉积该层180。电介质层180可以包括例如氧化硅(SiO或者SiO2)材料。电介质层180使用物理气相沉积或者化学气相沉积工艺进行沉积。如果必要，层180的顶表面也可以使用例如CMP被平整化。
层176和层180包括用于集成电路的金属前电介质(PMD)层。
现在参考图25。开口90被形成在抬升的源极-漏极区域之上并且延伸通过PMD层以暴露鳍124的顶表面和德尔塔掺杂硅锗(SiGe)层142在鳍126之上)的顶表面(。开口可以例如使用掩模和各向异性干法刻蚀工艺形成。
共形阻挡金属层92然后被沉积在每个开口90的侧壁上以及在有源区域20中的区域42的顶表面和有源区域22中的德尔塔掺杂硅锗(SiGe)层142的顶表面上。阻挡层92可以包括例如氮化钛(TiN)材料。阻挡层92使用化学气相沉积工艺被沉积。
然后使用沉积工艺形成由例如钨制成的上置金属层的沉积物94。例如使用化学气相沉积(CVD)工艺形成钨沉积物94。沉积物94基本上完全填充开口90中的每个开口。沉积物94可以例如包括共形沉积物，包括覆盖PMD层的顶表面的部分。在这种情况下，执行用来去除过量钨材料并且平整化沉积物94的顶表面(与PMD层的顶表面共面)的工艺。该工艺可以包括例如化学机械抛光(CMP)操作。
然后执行自对准硅化工艺以在钨沉积物94与有源区域20中的鳍124之间形成第一低电阻膜100，并且在钨沉积物94与有源区域22中的鳍126之间形成第二低电阻膜102。如本领域技术人员已知的将衬底加热到合适的温度引起TiN层92与鳍124的硅材料反应以形成用于第一低电阻膜100的第一硅化物并且引起TiN层92与德尔塔掺杂硅锗(SiGe)层142(在鳍126上)反应以形成用于第二低电阻膜102的第二硅化物。结果在图26中示出。
集成电路的完成涉及本领域技术人员众所周知的后段制程(BEOL)处理技术的执行。
虽然本文详细地讨论了做出和使用各个实施例，应当领会的是，如本文所描述的是提供可以在各种背景中实施的很多发明构思。本文所讨论的实施例仅仅是代表性的而不限制本发明的范围。
虽然已经在附图和前述描述中详细地图示和描述了本发明，但是这样的图示和描述被认为是说明性或者示例性的而不是限制性的；本发明并不限于所公开的实施例。本领域技术人员在实践所要求权利的发明中，通过研究附图、公开和所附权利要求书中可以理解和影响对所公开的实施例的其他变化。

Claims (50)

1.一种方法，包括：
从半导体材料形成用于晶体管的源极区域和漏极区域；
在所述源极区域和所述漏极区域的顶表面上沉积高掺杂浓度德尔塔掺杂层；
沉积上置金属前电介质层；
形成延伸通过所述金属前电介质层的成组的开口，以暴露所述源极区域和所述漏极区域的所述顶表面上的所述高掺杂浓度德尔塔掺杂层；
在所述成组的开口的底部处沉积与所述高掺杂浓度德尔塔掺杂层接触的金属；以及
加热以发起所述金属与所述高掺杂浓度德尔塔掺杂层的至少第一部分的自对准硅化反应，以在所述源极区域和所述漏极区域上形成硅化物区域。
2.根据权利要求1所述的方法，其中所述高掺杂浓度德尔塔掺杂层的在所述第一部分每侧上的第二部分未被转换为硅化物。
3.根据权利要求1所述的方法，进一步包括用附加的金属填充所述成组的开口。
4.根据权利要求1所述的方法，其中所述半导体材料从由硅和硅锗构成的组中选择。
5.根据权利要求1所述的方法，其中形成所述源极区域和所述漏极区域包括形成抬升的源极-漏极结构。
6.根据权利要求1所述的方法，其中形成所述源极区域和所述漏极区域包括形成鳍结构。
7.根据权利要求1所述的方法，其中所述晶体管由衬底支撑，所述衬底从由绝缘体上硅(SOI)衬底和体衬底构成的组中选择。
8.根据权利要求7所述的方法，其中所述SOI衬底的上半导体层被完全耗尽。
9.根据权利要求1所述的方法，其中所述半导体材料包括硅锗，并且其中所述高掺杂浓度德尔塔掺杂层包括硅锗。
10.根据权利要求9所述的方法，其中用于所述高掺杂浓度德尔塔掺杂层的掺杂物包括硼。
11.根据权利要求10所述的方法，其中所述自对准硅化反应的所述金属包括钛，并且所述硅化物区域包括硅化钛。
12.一种方法，包括：
从第一半导体材料形成用于nMOS晶体管的源极区域和漏极区域；
从第二半导体材料形成用于pMOS晶体管的源极区域和漏极区域；
在所述pMOS晶体管的所述源极区域和所述漏极区域的顶表面上沉积高掺杂浓度德尔塔掺杂层；
沉积上置金属前电介质层；
形成延伸通过所述金属前电介质层的第一组开口，以暴露所述nMOS晶体管的所述源极区域和所述漏极区域的顶表面；
形成延伸通过所述金属前电介质层的第二组开口，以暴露所述pMOS晶体管的所述源极区域和所述漏极区域上的所述高掺杂浓度德尔塔掺杂层；
在所述第一组开口和所述第二组开口的底部处沉积金属，所述第二组开口中的所述金属与所述高掺杂浓度德尔塔掺杂层接触；
加热以：
发起所述金属与所述第一半导体材料的自对准硅化反应，以在所述nMOS晶体管的所述源极区域和所述漏极区域上形成第一硅化物区域；以及
发起所述金属与所述高掺杂浓度德尔塔掺杂层的自对准硅化反应，以在所述pMOS晶体管的所述源极和所述漏极区域上形成第二硅化物区域。
13.根据权利要求12所述的方法，其中所述第一半导体材料从由硅和碳化硅构成的组中选择，并且所述第二半导体材料从由硅和硅锗构成的组中选择。
14.根据权利要求12所述的方法，其中形成所述nMOS晶体管和所述pMOS晶体管的所述源极区域和所述漏极区域包括形成抬升的源极-漏极结构。
15.根据权利要求12所述的方法，其中形成所述nMOS晶体管和所述pMOS晶体管的所述源极区域和所述漏极区域包括形成鳍结构。
16.根据权利要求12所述的方法，其中所述nMOS晶体管和所述pMOS晶体管由衬底支撑，所述衬底从由绝缘体上硅(SOI)衬底和体衬底构成的组中选择。
17.根据权利要求16所述的方法，其中所述SOI衬底的上半导体层被完全耗尽。
18.根据权利要求12所述的方法，其中所述第二半导体材料包括硅锗并且其中所述高掺杂浓度德尔塔掺杂层包括硅锗。
19.根据权利要求18所述的方法，其中用于所述高掺杂浓度德尔塔掺杂层的掺杂物包括硼。
20.根据权利要求12所述的方法，其中所述自对准硅化反应的所述金属包括钛，并且所述第一硅化物区域和所述第二硅化物区域包括硅化钛。
21.一种方法，包括：
从半导体材料形成晶体管的区域；
在所述区域的顶表面上沉积高掺杂浓度德尔塔掺杂层；
沉积上置电介质层；
形成延伸通过所述电介质层的开口，以暴露所述晶体管的所述区域上的所述高掺杂浓度德尔塔掺杂层；
在所述开口的底部处沉积与所述高掺杂浓度德尔塔掺杂层接触的金属；以及
加热以发起所述金属与所述高掺杂浓度德尔塔掺杂层的至少第一部分的自对准硅化反应，以在所述晶体管的所述区域上形成硅化物区域。
22.根据权利要求21所述的方法，其中所述晶体管的所述区域是源极区域或漏极区域之一。
23.根据权利要求21所述的方法，其中用于所述高掺杂浓度德尔塔掺杂层的掺杂物包括硼。
24.根据权利要求21所述的方法，其中所述半导体材料包括硅锗，并且其中所述高掺杂浓度德尔塔掺杂层包括硅锗。
25.根据权利要求21所述的方法，其中所述自对准硅化反应的所述金属包括钛，并且所述硅化物区域包括硅化钛。
26.根据权利要求21所述的方法，其中所述高掺杂浓度德尔塔掺杂层的在所述第一部分每侧上的第二部分未被转换为硅化物。
27.一种方法，包括：
形成半导体材料鳍结构，所述半导体材料鳍结构包括用于晶体管的源极区域和漏极区域；
在所述半导体材料鳍结构上沉积高掺杂浓度德尔塔掺杂层；
沉积上置金属前电介质层；
形成延伸通过所述金属前电介质层的成组的开口到所述晶体管的所述源极区域和所述漏极区域上的所述高掺杂浓度德尔塔掺杂层；
在所述成组的开口的底部处沉积金属；以及
加热以发起所述金属与所述高掺杂浓度德尔塔掺杂层的至少第一部分之间的自对准硅化反应，以在所述源极区域和所述漏极区域上形成硅化物区域。
28.根据权利要求27所述的方法，其中所述高掺杂浓度德尔塔掺杂层的在所述第一部分每侧上的第二部分未被转换为硅化物。
29.根据权利要求27所述的方法，进一步包括用附加的金属填充所述成组的开口。
30.根据权利要求27所述的方法，所述半导体材料鳍结构由从由硅和硅锗构成的组中选择的材料制成。
31.根据权利要求27所述的方法，其中所述晶体管由衬底支撑，所述衬底从由绝缘体上硅(SOI)衬底和体衬底构成的组中选择。
32.根据权利要求27所述的方法，其中所述半导体材料鳍结构包括硅锗，并且其中所述高掺杂浓度德尔塔掺杂层包括硅锗。
33.根据权利要求32所述的方法，其中用于所述高掺杂浓度德尔塔掺杂层的掺杂物包括硼。
34.根据权利要求33所述的方法，其中所述自对准硅化反应的所述金属包括钛，并且所述硅化物区域包括硅化钛。
35.一种方法，包括：
从第一半导体材料形成用于nMOS晶体管的源极区域和漏极区域，所述第一半导体材料从由硅和碳化硅构成的组中选择；
从第二半导体材料形成用于pMOS晶体管的源极区域和漏极区域，所述第二半导体材料从由硅和硅锗构成的组中选择；
在所述第二半导体材料上沉积高掺杂浓度德尔塔掺杂层；
沉积上置金属前电介质层；
形成延伸通过所述金属前电介质层到所述nMOS晶体管的所述源极区域和所述漏极区域的第一组开口；
形成延伸通过所述金属前电介质层到所述pMOS晶体管的所述源极区域和所述漏极区域的第二组开口；
在所述第一组开口和所述第二组开口的底部处沉积金属；
加热以：
在所述金属与所述第一半导体材料之间发起自对准硅化反应，以在所述nMOS晶体管的所述源极区域和所述漏极区域上形成第一硅化物区域；以及
在所述金属与所述高掺杂浓度德尔塔掺杂层之间发起自对准硅化反应以在所述pMOS晶体管的所述源极和所述漏极区域上形成第二硅化物区域。
36.根据权利要求35所述的方法，其中形成所述nMOS晶体管和所述pMOS晶体管的所述源极区域和所述漏极区域包括形成抬升的源极-漏极结构。
37.根据权利要求35所述的方法，其中形成所述nMOS晶体管和所述pMOS晶体管的所述源极区域和所述漏极区域包括形成鳍结构。
38.根据权利要求35所述的方法，其中所述nMOS晶体管和所述pMOS晶体管由衬底支撑，所述衬底从由绝缘体上硅(SOI)衬底和体衬底构成的组中选择。
39.根据权利要求38所述的方法，其中所述SOI衬底的上半导体层被完全耗尽。
40.根据权利要求35所述的方法，其中所述高掺杂浓度德尔塔掺杂层包括硅锗。
41.根据权利要求40所述的方法，其中用于所述高掺杂浓度德尔塔掺杂层的掺杂物包括硼。
42.根据权利要求35所述的方法，其中所述自对准硅化反应的所述金属包括钛，并且所述第一硅化物区域和所述第二硅化物区域包括硅化钛。
43.一种集成电路，包括：
衬底；
晶体管，具有由所述衬底支撑的源极区域和漏极区域；
高掺杂浓度德尔塔掺杂层，在所述晶体管的所述源极区域和所述漏极区域上；
金属前电介质层，覆盖所述晶体管；
接触，延伸通过所述金属前电介质层到所述晶体管的所述源极区域和所述漏极区域；
在每个接触的底部处的导电区域，包括所述高掺杂浓度德尔塔掺杂层的第一部分的金属硅化物，其中所述高掺杂浓度德尔塔掺杂层的在所述第一部分每侧上的第二部分未被硅化。
44.根据权利要求43所述的集成电路，其中所述衬底是绝缘体上硅衬底。
45.根据权利要求43所述的集成电路，其中形成所述晶体管的所述源极区域和所述漏极区域的半导体材料从由硅和硅锗构成的组中选择。
46.根据权利要求43所述的集成电路，其中所述晶体管的所述源极区域和所述漏极区域包括抬升的源极-漏极结构。
47.根据权利要求43所述的集成电路，其中所述晶体管的所述源极区域和所述漏极区域包括鳍结构。
48.根据权利要求43所述的集成电路，其中所述晶体管是pMOS。
49.根据权利要求43所述的集成电路，其中所述金属硅化物的所述金属包括钛。
50.根据权利要求43所述的集成电路，其中所述晶体管是nMOS。
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