CN105304556B - 接触结构及其形成方法 - Google Patents

接触结构及其形成方法 Download PDF

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Publication number
CN105304556B
CN105304556B CN201410566325.6A CN201410566325A CN105304556B CN 105304556 B CN105304556 B CN 105304556B CN 201410566325 A CN201410566325 A CN 201410566325A CN 105304556 B CN105304556 B CN 105304556B
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layer
opening
dielectric layer
contact
contact area
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CN105304556A (zh
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林瑀宏
林圣轩
张志维
周友华
许嘉麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例包括接触结构及其形成方法。一个实施例是形成半导体器件的方法，该方法包括：在衬底上方形成接触区域；在接触区域和衬底上方形成介电层；以及形成穿过介电层的开口以暴露接触区域的一部分。该方法还包括：在接触区域的暴露部分上以及沿着开口的侧壁形成金属硅化物层；以及用导电材料填充开口以在介电层中形成导电插塞，导电插塞电连接至接触区域。

Description

接触结构及其形成方法
技术领域
本发明总体涉及半导体领域，更具体地，涉及半导体器件的接触结构以及形成方法。
背景技术
半导体器件用于各种电子应用中，例如，诸如个人电脑、手机、数码相机和其他电子设备。通常通过在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导电材料层，然后使用光刻来图案化各个材料层以在其上形成电路部件和元件来制造半导体器件。
半导体产业通过不断减小最小特征尺寸来不断提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成度，这使得更多的部件集成到给定的区域内。
在半导体器件中使用诸如金属或半导体的导电材料以制造集成电路的电连接件。随着器件的尺寸的减小，对导体和绝缘体的需求已经改变。
发明内容
根据本发明的一个方面，提供了一种形成半导体器件的方法，该方法包括：在衬底上方形成接触区域；在接触区域和衬底上方形成介电层；形成穿过介电层的开口以暴露接触区域的一部分；在接触区域的暴露部分上以及沿着开口的侧壁形成金属硅化物层；以及用导电材料填充开口以在介电层中形成接触插塞，接触插塞电连接至接触区域。
优选地，形成金属硅化物层包括：沿着接触区域的暴露部分、开口的侧壁以及在介电层上方形成含硅覆盖层；在开口中和介电层上方的含硅覆盖层上形成金属层；在开口中和介电层上方的金属层上形成粘合层；以及实施硅化工艺以使含硅覆盖层的至少一部分与金属层反应从而形成金属硅化物层。
优选地，含硅覆盖层包括硅、锗、硅锗、碳化硅、磷化硅或它们的组合。
优选地，金属层包括镍、钴、钛、钨或它们的组合。
优选地，粘合层包括氮化钛、氮化钽或它们的组合。
优选地，实施硅化工艺包括：在约100℃至约900℃的温度下、包括Ar、N2或它们的组合的工艺气体并且在约770托至约1000托的压力下对衬底实施退火工艺。
优选地，在接触区域的暴露部分上以及沿着开口的侧壁形成金属硅化物层消耗掉接触区域的至少一部分。
优选地，该方法还包括：平坦化导电材料以形成导电插塞，其中，在平坦化步骤之后，导电插塞的顶面与介电层的顶面基本上共面。
优选地，衬底是鳍式场效应晶体管(FinFET)的半导体鳍，而接触区域是FinFET的源/漏极区，并且形成接触区域包括：在半导体鳍中蚀刻凹槽；在凹槽中外延生长半导体材料；以及以至少一种掺杂剂掺杂半导体材料从而形成源/漏极区。
优选地，接触区域包括硅、硅锗、磷化硅、碳化硅或它们的组合。
优选地，金属硅化物层基本沿着开口的侧壁从接触区域的顶面延伸至介电层的顶面。
优选地，金属硅化物层具有沿着接触区域的第一厚度和沿着开口的侧壁的第二厚度，第一厚度在约30埃至约之间，而第二厚度在约至约之间。
根据本发明的另一方面，提供了一种形成接触结构的方法，该方法包括：在衬底上方形成接触层；在接触层和衬底上方沉积介电层；图案化介电层以形成穿过介电层的开口，接触层的至少一部分暴露在开口中；沿着暴露的接触层和介电层的侧壁在开口中以及在介电层上方沉积覆盖层；在开口中和介电层上方的覆盖层上沉积金属层；在开口中和介电层上方的金属层上沉积粘合层；以及在沉积粘合层之后，对覆盖层和金属层进行退火以沿着接触层和介电层的侧壁在开口中以及在介电层上方形成金属硅化物层。
优选地，该方法还包括：在开口中和介电层上方的粘合层上填充导电材料；以及实施平坦化工艺以在介电层中形成导电插塞，平坦化工艺去除位于介电层上方的导电材料、粘合层和金属硅化物层。
优选地，在对覆盖层和金属层实施退火以形成金属硅化物层之后，金属层的一部分保持未反应并且介于在金属硅化物层和粘合层之间。
优选地，金属层中保持未反应的部分的厚度在约3埃至约之间。
优选地，覆盖层具有与接触层基本上相同的材料组成。
根据本发明的又一方面，提供了一种形成接触结构的方法，该方法包括：在衬底中形成接触区域；在接触区域上方形成介电层；在介电层中形成开口以至少暴露接触区域的表面；沿着接触区域的暴露表面和开口的侧壁共形地沉积含硅覆盖层；在开口中的含硅覆盖层上共形地沉积金属层；在开口中的金属层上共形地沉积粘合层；以及对含硅覆盖层和金属层进行退火以沿着接触区域和介电层的侧壁在开口中形成金属硅化物层。
优选地，在开口中的金属层上共形地沉积粘合层的步骤之后，实施对含硅覆盖层和金属层进行退火的步骤。
优选地，金属硅化物层具有延伸在接触区域的顶面下方的表面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的半导体器件的截面图。
图2A至图2G是根据一些实施例的在半导体器件的制造中的中间阶段的截面图。
图3示出了根据一些实施例的另一半导体器件的截面图。
图4示出了根据一些实施例的在图2A至图2G中示出的工艺的工艺流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在本文中可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对位置术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文中使用的空间相对位置描述符可以同样地作出相应的解释。
通常而言，使用本发明的实施例，半导体器件可以利用具有改进的工艺稳定性的低电阻硅化物接触件。具体地，本发明在形成接触开口之后在接触开口中形成硅化物，而不是在形成接触件之前形成硅化物。在该工艺中，在接触开口内形成覆盖层并且在覆盖层上方形成金属层。然后对这些层进行退火以形成硅化物层。通过在形成接触开口之后形成覆盖层，覆盖层性能不受接触开口蚀刻工艺、介电层形成或在形成覆盖层之前实施的任何其他工艺的影响。这改进了用于形成覆盖层的处理窗口并且也改进了用于形成接触件的工艺稳定性。此外，覆盖层可以修复由蚀刻接触开口导致的损坏。
图1示出了根据一些实施例的半导体器件100的截面图。半导体器件100包括衬底20、有源或无源器件22、接触层24、介电层26和接触结构50。接触结构包括金属硅化物层40、未反应的金属层32’、粘合层34和导电插塞42’。
衬底20可以是晶圆的一部分，并且可以包括诸如硅、锗、金刚石等的半导体材料。可选地，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化铟镓和这些的组合等的化合物材料也可以使用。此外，衬底20可以包括绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料(诸如，外延硅、锗、锗硅、SOI、绝缘体上硅锗(SGOI)或它们的组合)层。如本领域所知，衬底20可以掺杂有诸如硼、铝或镓等的p型掺杂剂，但是该衬底可以可选地掺杂有n型掺杂剂。
衬底20可以包括有源和无源器件22。作为本领域普通技术人员会认识到，诸如晶体管、电容器、电阻器和它们的组合等的各种器件可用于生成半导体器件100的设计的结构和功能需求。有源和无源器件22可以使用任何合适的方法形成。在图中仅示出了衬底20的一部分，因为这足以充分描述说明性实施例。
在衬底20上方形成接触层24。接触层24可以包括位于衬底20上方的掺杂区。在一些实施例中，在衬底20的顶面上或中直接形成接触层24。在接触层24上方形成介电层26。介电层26可以由诸如氧化硅的氧化物、低k介电质、聚合物等或它们的组合形成。
接触结构50形成为延伸穿过介电层26到达接触层24。可以在介电层26中的开口中形成接触结构50(见下文论述的图2A至图2F)。接触结构50包括直接邻接接触层24和介电层26的金属硅化物层40。金属硅化物层40提供与接触层24的低电阻接触以及与接触层24的良好的粘合性。在一些实施例中，金属硅化物层40基本上沿着接触结构50的整个侧壁从接触层24延伸至介电层26的顶面26A。由于在硅化工艺期间可能会消耗一些接触层24以形成金属硅化物层40，所以金属硅化物层40的部分40A的表面可以延伸为低于接触层24的顶面24A。
未反应的金属层32’位于金属硅化物层40上。未反应的金属层32’是在形成金属硅化物层40期间未被消耗的金属层。在一些实施例中，因为基本上整个金属层都在形成金属硅化物层40期间被消耗，所以不存在未反应的金属层32’。在未反应的金属层32’上形成粘合层34，粘合层34改进了随后形成的导电插塞42’之间的粘合性，并且还防止了未反应的金属层32’(以及例如在硅化工艺之前的图2D中的金属层32)的氧化。
导电插塞42’形成在粘合层34上并且可以基本上填充介电层26中的开口的剩余部分。在一些实施例中，该导电插塞42’具有与介电层26的顶面26A基本共平面的顶面42A。
图2A至图2G是根据一些实施例的制造半导体器件100的中间阶段的截面图，而图4是图2A至图2G中示出的工艺的工艺流程图。参考图2A，示出了处于处理的中间阶段的包括接触层24、介电层26和开口28的半导体器件100。虽然在图2A中未示出，但是接触层24可以形成在衬底20上方或上(步骤302)。
接触层24可以包括位于衬底20上方的掺杂区。接触层可以由硅、硅锗、磷化硅、碳化硅等或它们的组合形成。接触层24可以从衬底20处或从一些其他中间结构处外延生长。在一些实施例中，在形成在衬底20中的凹槽中外延生长接触层24。在其他实施例中，通过利用注入工艺掺杂衬底20的一部分来形成接触层24。例如，接触层24可以是晶体管的源极区或漏极区。
在接触层24上方形成介电层26(步骤304)。介电层26可以由氧化物(诸如，氧化硅、硼磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)、氟硅酸盐玻璃(FSG))、低k介电质(诸如，碳掺杂的氧化物)、极低k介电质(诸如，多孔碳掺杂的二氧化硅)、聚合物(诸如，聚酰亚胺)等或它们的组合形成。低k介电材料可以具有低于3.9的k值。介电层26可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、旋涂介电质(SOD)工艺等或它们的组合来沉积。在一些实施例中，介电层26是层间介电质(ILD)。
在形成介电层26之后，可以形成穿过介电层26到达接触层24的顶面24A的开口28(步骤306)。例如，可以使用可接受的光刻和蚀刻技术(诸如，各向异性干蚀刻)来形成开口28。
在一些实施例中，开口的形成包括诸如光刻胶的掩蔽材料。在这些实施例中，可以在介电层上方沉积并且图案化光刻胶(未示出)。光刻胶可以包括诸如深紫外线(DUV)光刻胶的传统的光刻胶材料，并且可以例如通过采用布置光刻胶的旋涂工艺而沉积在介电层26的顶面上。然而，可以可选地利用形成或布置光刻胶的其他任何合适的材料或者方法。一旦已经形成光刻胶，光刻胶可以通过图案化的掩模板(reticle)暴露于能量(例如，光)从而导致光刻胶中暴露于能量的那些部分发生反应。然后可以使光刻胶显影，并且可以去除光刻胶的部分，从而在光刻胶中形成开口，并且通过开口暴露介电层26的部分顶面。在图案化光刻胶之后，可以图案化介电层26以形成开口28。
在形成开口28之后，可以实施可选的清洗工艺以去除由蚀刻工艺引起的位于接触层24上的原生氧化物或任何残留物(步骤308)。可以使用HCl溶液实施清洗工艺，并且清洗时间可以例如为约一分钟。在一些实施例中，通过将暴露的接触层24保持在真空或者不含氧或氧化剂的环境中，可以避免原生氧化物。
图2B示出了在介电层26和接触层24上方以及在开口28中形成覆盖层30(步骤310)。在一些实施例中，覆盖层30将基本上被随后形成金属硅化物层40的工艺消耗。覆盖层30可以修复由开口28的蚀刻所造成的对接触层24和介电层26的任何破坏。此外，覆盖层30可以增大接触结构50(见图2G)和介电层26之间的粘合性。
覆盖层30可以由硅、锗、硅锗、碳化硅、磷化硅等或它们的组合形成。在一些实施例中，覆盖层30具有与接触层基本相同的材料组成。例如，在接触层24由硅锗形成的实施例中，覆盖层30也由硅锗形成。
在接触层24是n型金属氧化物半导体场效应晶体管(NMOS)的一部分的实施例中，覆盖层30由硅、硅化磷、碳化硅等或它们的组合制成。在接触层24是p型金属氧化物半导体场效应晶体管(PMOS)的一部分的实施例中，覆盖层30由硅、锗、硅锗等或它们的组合制成。如图2B所示，覆盖层30包括邻接接触层24的部分30A、沿着开口28的侧壁延伸并且邻接介电层26的部分30B，以及在介电层26上方延伸并且邻接介电层26的部分30C。在一些实施例中，通过CVD、ALD、PVD等或它们的组合形成厚度为从约至约的覆盖层30。覆盖层30可以共形地沉积为沿着开口28的底部和侧壁以及在介电层26上方具有基本上均匀的厚度。
如图2C所示，在形成覆盖层30之后，在覆盖层30上方以及在开口中形成金属层32(步骤312)。在一些实施例中，金属层32将基本上被随后形成金属硅化物层40的工艺消耗。金属层32可以由镍、钴、钛、钨等或它们的组合形成。如图2C所示，金属层32包括位于开口底部的部分32A、沿着开口的侧壁延伸的的部分32B，以及在介电层26上方延伸的部分32C。在一些实施例中，通过PVD、ALD、溅射沉积等或它们的组合形成厚度为从约至约的金属层32。金属层32可以共形地沉积为沿着开口的底部和侧壁以及在介电层26上方具有基本上均匀的厚度。
如图2D所示，在形成金属层32之后，在金属层32上方以及在开口中形成粘合层34(步骤314)。粘合层34改进了随后形成的导电插塞42’(见图2G)之间的粘合性并且还防止金属层32的氧化。粘合层34可以由氮化钛、氮化钽等或它们的组合形成。如图2D中所示，粘合层34包括位于开口底部的部分34A、沿着开口的侧壁延伸的部分34B以及在介电层26上方延伸的部分34C。在一些实施例中，通过CVD、PVD、ALD等或它们的组合形成厚度为从约至约的粘合层34。粘合层34可以共形地沉积为沿着开口的底部和侧壁以及在介电层26上方具有基本上均匀的厚度。
图2E示出了由覆盖层30和金属层32形成金属硅化物层40的硅化工艺(步骤316)。金属硅化物层40的形成包括对半导体器件100实施退火工艺。退火工艺导致覆盖层30与金属层32反应以形成金属硅化物层40。在一些实施例中，使用热浸工艺、尖峰退火、快速退火、激光退火等或它们的组合来实施退火工艺。在一些实施例中，在约100℃至约900℃的温度下、在包括诸如Ar、N2等或它们的组合的工艺气体的大气环境中并且在约770托至约1000托的压力下实施退火工艺。
在一些实施例中，在形成金属硅化物层40之后，仍然存在未转化成金属硅化物层40的未反应的金属层32’。如图2E所示，金属硅化物层40包括位于开口底部并且邻接接触层24的部分40A、沿着开口的侧壁延伸并且邻接介电层26的部分40B以及在介电层26上方延伸并且邻接介电层26的部分40C。在一些实施例中，金属硅化物层40的底部40A的厚度为约至约而金属硅化物层40的侧壁部分40B的厚度为约至约
图2F示出了用导电材料42填充介电层26中的开口(步骤318)。在一些实施例中，导电材料42填充开口并且还延伸在介电层26上方。导电材料42将形成随后形成的导电插塞42’(见图2G)。在一些实施例中，导电材料42由钨形成。在可选实施例中，导电材料42包括其他金属或金属合金，诸如，铝、铜、氮化钛、氮化钽等或它们的组合。可以使用CVD、ALD、PVD、溅射等或它们的组合实施导电材料的形成。
在导电材料42延伸在介电层26上方的实施例中，可以对导电材料42实施平坦化工艺以形成如图2G所示的导电插塞42’(步骤320)。在一些实施例中，平坦化工艺是化学机械抛光(CMP)工艺、蚀刻工艺等或它们的组合。在平坦化工艺之后，导电插塞42’的顶面42A与介电层26的顶面26A基本共面。如图2G所示，金属硅化物层40、未反应的金属层32’(如果存在)、粘合层34以及导电插塞42’形成接触结构50。
图3示出了根据一些实施例的半导体器件200的截面图。半导体器件200包括在衬底202上形成的有源器件150。在示出的实施例中，有源器件是晶体管，但是其他实施例可以包括其他各种有源和无源器件，诸如，电阻器、电容器、电感器、二极管、变容二极管等或它们的组合。在实施例中，有源器件150是鳍式场效应晶体管(FinFET)。
衬底202可以是晶圆的一部分，并且可以包括诸如硅、锗或金刚石等的半导体材料。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化铟镓和这些的组合等的化合物材料。此外，衬底202可以包括SOI衬底。通常，SOI衬底包括半导体材料(诸如，外延的硅、锗、硅锗、SOI、SGOI或它们的组合)层。衬底202可以掺杂有p型掺杂剂，诸如，硼、铝或镓等，但是衬底可以可选地掺杂有本领域已知的n型掺杂剂。在图中仅示出了衬底202的一部分，因为这足以充分描述该说明性实施例。在一些实施例中，衬底202是从衬底延伸的半导体鳍。
有源器件150包括源/漏极区210、栅介质204、栅电极206、栅极间隔件208、介电层212以及接触结构50。有源器件150的形成可以开始于栅极介电层(未示出)和栅电极层(未示出)的形成。可以通过热氧化、CVD、溅射或用于形成栅介质的其他任何合适的方法来形成栅极介电层。在其他实施例中，栅极介电层包括具有高介电常数(k值，例如，大于3.9)的介电材料。该材料可以包括氮化硅、氮氧化物、诸如HfO2、HfZrOx、HfSiOx、HfTiOx和HfAlOx等的金属氧化物，以及它们的组合和多层。在另一实施例中，栅极介电层可以具有选自诸如氮化钛、氮化钽或氮化钼的金属氮化物材料的覆盖层。
可以在栅极介电层上方形成栅电极层(未示出)。栅电极层可以包括导电材料并且可以选自由多晶硅(多晶Si)、多晶硅锗(多晶SiGe)、金属氮化物、金属硅化物、金属氧化物和金属组成的组。金属氮化物的实例包括氮化钨、氮化钼、氮化钛和氮化钽等或它们的组合。金属硅化物的实例包括硅化钨、硅化钛、硅化钴、硅化镍、硅化铂、硅化铒等或它们的组合。金属氧化物的实例包括氧化钌、氧化铟锡等或它们的组合。金属的实例包括钨、钛、铝、铜、钼、镍、铂等或它们的组合。
可以通过CVD、溅射沉积或用于沉积导电材料的其他合适的技术来沉积栅电极层。栅电极层的厚度可以在约至约的范围内。在栅电极层的图案化或栅极蚀刻之前，该栅电极层的顶面通常具有非平坦的顶面，并且可以例如通过CMP工艺来平坦化。此时，例如，通过离子注入技术，可以将离子引入栅电极层内或可以不将离子引入栅电极层内。
在形成栅电极层之后，可以图案化栅电极层和栅极介电层以形成栅电极206和栅介质204。栅极图案化工艺可以包括使用可接受的沉积和光刻技术在栅电极层上沉积和图案化栅极掩模(未示出)。栅极掩模可包含常用的掩蔽材料，诸如(但不限于)光刻胶材料、氧化硅、氮氧化硅和/或氮化硅。如图3所示，可以使用等离子蚀刻来蚀刻栅电极层和栅极介电层以形成栅电极206和栅介质204。
在形成栅电极206和栅极介电质204之后，可以形成源/漏极区210。可以通过利用注入工艺将合适的掺杂剂注入以补充衬底202中的掺杂剂来掺杂衬底202的一部分，从而形成源/漏极区210。在衬底202注入有诸如硼、镓或铟等的p型掺杂剂的实施例中，源/漏极区210注入有诸如磷、砷或锑等的n型掺杂剂。源/漏极区210的注入可以使用栅电极206作为掩模。在一些实施例中，可以对掺杂的源/漏极区210实施退火以促进掺杂杂质扩散到衬底202内。
在另一实施例中，可以通过在衬底202中形成凹槽(未示出)并且在凹槽中外延生长材料来形成源/漏极区210。在实施例中，该凹槽可以通过各向异性蚀刻形成。可选地，凹槽可以通过各向同性取向依赖蚀刻工艺形成，其中，四甲基氢氧化铵(TMAH)等可用作蚀刻剂。在形成凹槽之后，可以通过在凹槽中外延生长材料来形成源/漏极区210。在外延工艺期间，可以将诸如HCl气体(作为蚀刻气体)的蚀刻气体加入到工艺气体中，从而在凹槽中而不是在栅电极206上选择性地生长源/漏极区210。在可选实施例中，不添加蚀刻气体，或蚀刻气体的量很小，从而在衬底202和栅电极206上形成有源/漏极区210的薄层。在又一个实施例中，栅电极206和衬底202可以覆盖有牺牲层(未示出)以防止在其上的外延生长。既可以通过如上论述的注入方法来掺杂源/漏极区210，也可以在生长材料的同时通过原位掺杂方法来掺杂源/漏极区210。
源/漏极区210的形成方法可以包括ALD、CVD(诸如，减压CVD(RPCVD)、金属有机化学汽相沉积(MOCVD))或其他合适的方法。根据源/漏极区210的期望的组成，用于外延生长的前体可以包括SiH4、GeH4、CH3和以及PH3等,并且调节含Si气体、含Ge气体、含C气体和含P气体的分压以调节锗/碳/磷与硅的原子比率。
在一些实施例中，形成源/漏极区210以对栅电极206下面的沟道区施加应变。在衬底202由硅形成的实施例中，可以利用诸如与硅具有不同的晶格常数的硅锗或硅碳等的材料，通过选择性外延生长(SEG)工艺来形成源/漏极区210。源/漏极区210中的应力源材料和形成在栅电极206下面的沟道区之间的晶格失配会使应力施加在沟道区内，这将增大载流子迁移率和器件的整体性能。既可以通过如上论述的注入方法来掺杂源/漏极区210，也可以在生长生长材料的同时通过原位掺杂来掺杂源/漏极区210。
可以通过在栅电极206和衬底202上方毯式沉积间隔件层(未示出)来形成栅极间隔件208。间隔件层可以包括SiN、氮氧化物、SiC、SiON、氧化物等并且可以通过用于形成这样的层的方法(诸如，CVD、等离子体增强CVD、溅射沉积等或它们的组合)来形成。然后优选地通过各向异性蚀刻来图案化栅极间隔件208以从栅电极206和衬底202的水平表面处去除间隔件层。
在一些实施例中，源/漏极区210包括轻掺杂区(未示出)和重掺杂区。在这个实施例中，在形成栅极间隔件208之前，可以轻掺杂源极/漏极区210。在形成栅极间隔件208之后，然后可以重掺杂源/漏极区210。这形成了轻掺杂区和重掺杂区。轻掺杂区主要位于栅极间隔件208下面，而重掺杂区沿衬底202位于栅极间隔件208外部。
在形成栅电极206、源/漏极区210和栅极间隔件208之后，形成介电层212。介电层212可以由氧化物(诸如，氧化硅、BPSG、USG、FSG)、低k介电质(诸如，碳掺杂的氧化物)、极低k介电质(诸如，多孔碳掺杂的二氧化硅)、聚合物(诸如，聚酰亚胺)等或它们的组合形成。低k介电材料可以具有低于3.9的k值。可通过CVD、PVD、ALD、SOD工艺等或它们的组合来沉积介电层212。介电层212也可称为ILD 212。
在形成介电层212之后，形成穿过介电层212的开口(未示出)以暴露源/漏极区210的一部分。例如，可使用可接受的光刻和蚀刻技术(诸如，各向异性干蚀刻)来形成开口。
在介电层212中形成开口之后，在开口中形成接触结构50。以与以上在图2A至图2G中描述的类似的方式形成接触结构50，因此本文中不再重复描述。接触结构50将源极/漏极区210电连接至上面的结构(未示出)，诸如，导线/通孔和/或其他有源和无源器件。例如，可以在接触结构50和介电层212上方形成包括介电材料和导电材料的交替层的互连结构。接触结构50可以将源极/漏极区210电连接至该互连结构。
根据本发明的实施例，优势包括具有改进的工艺稳定性的低电阻硅化物接触件。具体地，本发明在形成接触开口之后在接触开口中形成硅化物而不是在形成接触件之前形成硅化物。在该工艺中，在接触开口内部形成覆盖层并且在覆盖层上方形成金属层。然后对这些层进行退火以形成硅化物层。通过在形成接触开口之后形成覆盖层，覆盖层性能不受接触开口蚀刻工艺、介电层形成或在形成覆盖层之前实施的其他任何工艺的影响。这改进了形成覆盖层的工艺窗，并且也改进了形成接触件的工艺的稳定性。此外，覆盖层可以修复由蚀刻接触开口而导致的破坏。
一个实施例是一种形成半导体器件的方法，该方法包括：在衬底上方形成接触区域；在接触区域和衬底上方形成介电层；以及形成穿过介电层的开口以暴露接触区域的一部分。该方法还包括：在接触区域的暴露部分上并且沿着开口的侧壁形成金属硅化物层；以及用导电材料填充开口以在介电层中形成导电插塞，该导电插塞电连接至接触区域。
另一个实施例是一种形成接触结构的方法，该方法包括：在衬底上方形成接触层；在接触层和衬底上方沉积介电层；图案化介电层以形成穿过介电层的开口，从而接触层的至少一部分暴露在开口中；以及沿着暴露的接触层和介电层的侧壁在开口中以及在介电层上方沉积覆盖层。该方法还包括：在开口中的覆盖层上以及在介电层上方沉积金属层；在开口中的金属层上以及在介电层上方沉积粘合层；以及在沉积粘合层之后，对覆盖层和金属层进行退火以沿着接触层和介电层的侧壁在开口中以及在介电层上方形成金属硅化物层。
又一个实施例是一种形成接触结构的方法，该方法包括：在衬底中形成接触区域；在接触区域上方形成介电层；在介电层中形成开口以至少暴露接触区域的表面；以及沿着接触区域的暴露表面和开口的侧壁共形地沉积含硅覆盖层。该方法还包括：在开口中的含硅覆盖层上共形地沉积金属层；在开口中的金属层上共形地沉积粘合层；以及对含硅覆盖层和金属层进行退火以沿着接触区域和介电层的侧壁在开口中形成金属硅化物层。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在本文介绍的实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，他们可以对本发明做出多种变化、替换以及改变。

Claims (19)

1.一种形成半导体器件的方法，所述方法包括：
在衬底上方形成接触区域；
在所述接触区域和所述衬底上方形成介电层；
形成穿过所述介电层的开口以暴露所述接触区域的一部分；
在所述接触区域的暴露部分上以及沿着所述开口的侧壁形成金属硅化物层，其中，形成所述金属硅化物层包括：
沿着所述接触区域的暴露部分、所述开口的侧壁以及在所述介电层上方形成含硅覆盖层；
在所述开口中和所述介电层上方的所述含硅覆盖层上形成金属层；
在所述开口中和所述介电层上方的金属层上形成粘合层；以及
实施硅化工艺以使所述含硅覆盖层的至少一部分与所述金属层反应从而形成所述金属硅化物层；以及
用导电材料填充所述开口的位于所述金属硅化物层和所述粘合层上方的剩余部分以在所述介电层中形成接触插塞，所述接触插塞电连接至所述接触区域。
2.根据权利要求1所述的方法，其中，所述含硅覆盖层包括硅、锗、硅锗、碳化硅、磷化硅或它们的组合。
3.根据权利要求1所述的方法，其中，所述金属层包括镍、钴、钛、钨或它们的组合。
4.根据权利要求1所述的方法，其中，所述粘合层包括氮化钛、氮化钽或它们的组合。
5.根据权利要求1所述的方法，其中，实施所述硅化工艺包括：
在100℃至900℃的温度下、包括Ar、N2或它们的组合的工艺气体并且在770托至1000托的压力下对所述衬底实施退火工艺。
6.根据权利要求1所述的方法，其中，在所述接触区域的暴露部分上以及沿着所述开口的侧壁形成所述金属硅化物层消耗掉所述接触区域的至少一部分。
7.根据权利要求1所述的方法，还包括：
平坦化所述导电材料以形成所述接触插塞，其中，在所述平坦化步骤之后，所述接触插塞的顶面与所述介电层的顶面共面。
8.根据权利要求1所述的方法，其中，所述衬底是鳍式场效应晶体管(FinFET)的半导体鳍，而所述接触区域是所述鳍式场效应晶体管的源/漏极区，并且形成所述接触区域包括：
在所述半导体鳍中蚀刻凹槽；
在所述凹槽中外延生长半导体材料；以及
以至少一种掺杂剂掺杂所述半导体材料从而形成所述源/漏极区。
9.根据权利要求1所述的方法，其中，所述接触区域包括硅、硅锗、磷化硅、碳化硅或它们的组合。
10.根据权利要求1所述的方法，其中，所述金属硅化物层沿着所述开口的侧壁从所述接触区域的顶面延伸至所述介电层的顶面。
11.根据权利要求1所述的方法，其中，所述金属硅化物层具有沿着所述接触区域的第一厚度和沿着所述开口的侧壁的第二厚度，所述第一厚度在至之间，而所述第二厚度在至之间。
12.一种形成接触结构的方法，所述方法包括：
在衬底上方形成接触层；
在所述接触层和所述衬底上方沉积介电层；
图案化所述介电层以形成穿过所述介电层的开口，所述接触层的至少一部分暴露在所述开口中；
沿着暴露的接触层和所述介电层的侧壁在所述开口中以及在所述介电层上方沉积覆盖层；
在所述开口中和所述介电层上方的所述覆盖层上沉积金属层；
在所述开口中和所述介电层上方的所述金属层上沉积粘合层；
在沉积所述粘合层之后，对所述覆盖层和所述金属层进行退火以沿着所述接触层和所述介电层的侧壁在所述开口中以及在所述介电层上方形成金属硅化物层；以及
在形成所述金属硅化物层之后，在所述开口中和所述介电层上方的所述粘合层上填充导电材料。
13.根据权利要求12所述的方法，还包括：
实施平坦化工艺以在所述介电层中形成导电插塞，所述平坦化工艺去除位于所述介电层上方的所述导电材料、所述粘合层和所述金属硅化物层。
14.根据权利要求12所述的方法，其中，在对所述覆盖层和所述金属层实施退火以形成所述金属硅化物层之后，所述金属层的一部分保持未反应并且介于在所述金属硅化物层和所述粘合层之间。
15.根据权利要求14所述的方法，其中，所述金属层中保持未反应的部分的厚度在至之间。
16.根据权利要求12所述的方法，其中，所述覆盖层具有与所述接触层相同的材料组成。
17.一种形成接触结构的方法，所述方法包括：
在衬底中形成接触区域；
在所述接触区域上方形成介电层；
在所述介电层中形成开口以至少暴露所述接触区域的表面；
沿着所述接触区域的暴露表面和所述开口的侧壁共形地沉积含硅覆盖层；
在所述开口中的所述含硅覆盖层上共形地沉积金属层；
在所述开口中的所述金属层上共形地沉积粘合层
对所述含硅覆盖层和所述金属层进行退火以沿着所述接触区域和所述介电层的侧壁在所述开口中形成金属硅化物层；以及
在形成所述金属硅化物层之后，在所述开口中和所述介电层上方的所述粘合层上填充导电材料。
18.根据权利要求17所述的方法，其中，在所述开口中的所述金属层上共形地沉积所述粘合层的步骤之后，实施对所述含硅覆盖层和所述金属层进行退火的步骤。
19.根据权利要求17所述的方法，其中，所述金属硅化物层具有延伸在所述接触区域的顶面下方的表面。
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