TW201603187A - 半導體裝置及接觸結構的形成方法 - Google Patents

半導體裝置及接觸結構的形成方法 Download PDF

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TW201603187A
TW201603187A TW103136579A TW103136579A TW201603187A TW 201603187 A TW201603187 A TW 201603187A TW 103136579 A TW103136579 A TW 103136579A TW 103136579 A TW103136579 A TW 103136579A TW 201603187 A TW201603187 A TW 201603187A
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Taiwan
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layer
forming
opening
dielectric layer
contact
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TW103136579A
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TWI564995B (zh
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林瑀宏
林聖軒
張志維
周友華
許嘉麟
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台灣積體電路製造股份有限公司
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Abstract

本揭露之實施例包括接觸結構及其形成方法。一實施例為形成半導體裝置之形成方法，此方法包括：形成接觸區於基底之上；形成介電層於接觸區及基底之上；及形成穿透介電層之開口以暴露出接觸區之一部份。此方法更包括：於接觸區露出之部份上及沿該開口之側壁形成金屬矽化物層；以及於開口中填入導電材料以於介電層中形成導電插塞，其中導電插塞電性耦合至接觸區。

Description

半導體裝置及接觸結構的形成方法
本揭露係有關於一種半導體裝置，特別有關於半導體裝置之接觸結構。
半導體裝置已被使用於各種電子應用中，例如：個人電腦、手機、數位相機及其他電子設備。典型的半導體裝置製造係依序沉積絕緣或介電層、導電層及半導體層材料於半導體基板之上，再經由微影技術圖案化各層以於其上形成電路元件及構件。
半導體產業經由不斷地降低最小特徵之尺寸，以在一給定的面積中整合更多元件，進而持續地提昇各種電子元件(例如：電晶體、二極體、電阻器、電容器…等等)之積集度(integration density)。
半導體裝置中多使用導電材料例如：金屬或半導體於積體電路間形成電性連接。隨著元件尺寸之縮小，對於導體及絕緣體之要求亦隨之改變。
本揭露之一實施例為形成半導體裝置的方法，此方法包括：形成一接觸區於一基底之上；形成一介電層於該接觸區及該基底之上；以及，形成一開口穿透該介電層以暴露出 該接觸區之一部份。此方法更包括：於該接觸區露出之該部份上及沿著該開口之側壁形成一金屬矽化物層；以及於該開口填入一導電材料以於該介電層中形成一導電插塞，其中該導電插塞電性耦合至該接觸區。
本揭露另一實施例為形成接觸結構的方法，此方法包括：形成一接觸層於一基底之上；沉積一介電層於該接觸層及該基底之上；圖案化該介電層以形成一開口穿透該介電層，且至少一部分該接觸層係暴露於該開口中；以及，沿著露出之該接觸層和該介電層之側壁及於該介電層之上沉積一蓋層於該開口中。此方法更包括：沉積一金屬層於該開口中及該介電層上之該蓋層之上；沉積一黏著層於該開口中及該介電層上之該金屬層之上；並在沉積黏著層後，退火該蓋層及該金屬層以於該開口中沿著該接觸層和該介電層之側壁及於該介電層上形成一金屬矽化物層。
本揭露又一實施例為形成接觸結構的方法，此方法包括：形成一接觸區於一基底之上；形成一介電層於該接觸區之上；形成一開口於該介電層中以暴露至少該接觸區之一表面；以及，沿著該接觸區露出之該表面及該開口之側壁順應性沉積一含矽蓋層。此方法更包括：順應性沉積一金屬層於該開口中之該含矽蓋層上；順應性沉積一黏著層於該開口中之該金屬層上；以及，退火該含矽蓋層及該金屬層以於該開口中沿著該接觸區及該介電層之側壁形成一金屬矽化物。
100‧‧‧半導體裝置
20‧‧‧基底
22‧‧‧主動或被動裝置
24‧‧‧接觸層
26‧‧‧介電層
28‧‧‧開口
30‧‧‧蓋層
30A、30B、30C‧‧‧部份
32‧‧‧金屬層
32A、32B、32C‧‧‧部份
32’‧‧‧未反應金屬層
34‧‧‧黏著層
34A、34B、34C‧‧‧部份
40‧‧‧金屬矽化物層
40A、40B、40C‧‧‧部份
42‧‧‧導電材料
42’‧‧‧導電插塞
50‧‧‧接觸結構
150‧‧‧主動裝置
200‧‧‧半導體裝置
202‧‧‧基底
204‧‧‧閘極介電質
206‧‧‧閘極電極
208‧‧‧閘極間隔物
210‧‧‧源極/汲極區域
212‧‧‧介電層
以下搭配附圖對本揭露作詳細說明。須強調的 是，根據常規的作法，圖式中各種特徵並未依比例繪示。相反地，為清楚起見，各種特徵之尺寸可能任意擴張或縮小。
第1圖為根據一些實施例繪示之半導體裝置剖面圖。
第2A-2G為根據一些實施例繪示之半導體裝置於製造中間階段之剖面圖。
第3圖為根據一些實施例繪示之另一半導體裝置剖面圖。
第4圖根據一些實施例繪示如第2A-2G圖所示製程之製程流程圖。
以下提供許多不同實施例或示例，以施行所請標的之各種特徵。以下描述元件及設置之特定示例以簡化本揭露。當然，此等僅為示例，並非意圖作為限定。舉例而言，在以下”形成第一特徵於第二特徵上或上方”的描述中，可能包含第一特徵及第二特徵形成直接接觸的實施方式，亦可能包含形成額外的特徵於第一特徵及第二特徵之間，而第一特徵與第二特徵並未直接接觸的實施方式。此外，本揭露在不同例子可能使用重複的元件標號(數字及/或字母)。此重複係為了簡化及清楚之目的，而非代表各實施例及/或結構間具有特定關係。
再者，此處所使用之空間性相對詞語，例如：”下面”、”之下”、”較低”、”之上”、”較高”及其相似者，係為了簡單描述如圖中繪示之元件或特徵相對另一元件或特徵之關係。這些空間性相對詞語意圖涵蓋除了圖中所繪示方位以外，裝置於使用或操作中之不同方位。這些設備或組件亦可轉向(旋轉90度或於其他方向)，而其所使用之空間性描述亦可依此 理解。
整體而言，運用本揭露之實施例，半導體裝置可以利用低電阻的矽化物接觸(silicide contact)增進製程穩定性。尤其，本揭露係在形成接觸開口後，於接觸開口中形成矽化物接觸，而不是在形成接觸前形成矽化物。在此製程中，蓋層係形成於接觸開口內，且金屬層係形成於蓋層之上。接著，這些膜層經退火(annealed)以形成矽化物層。藉由在形成接觸開口之後形成蓋層，則接觸開口的蝕刻過程、形成介電層、或在形成蓋層之前進行的任何其他處理都不會影響蓋層性質。如此一來，可提昇形成蓋層的製程寬裕度(processing window)及增進形成接觸的製程穩定性。此外，蓋層可修復蝕刻接觸開口所造成的損傷。
第1圖為根據一些實施例繪示之半導體裝置100的剖面圖。半導體裝置100包括基底20、主動或被動裝置22、接觸層24、介電層26及接觸結構50。接觸結構包括金屬矽化物層40、未反應金屬層32’、黏著層34及導電插塞42’。
基底20可為部份晶圓，且可能包括半導體材料例如：矽、鍺、鑽石(diamond)或其相似者。或者，亦可使用化合物材料，例如：矽鍺(silicon germanium)、碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、砷化銦(indium arsenide)、磷化銦(indium phosphide)、矽鍺碳化物(silicon germanium carbide)、鎵砷磷化物(gallium arsenic phosphide)、鎵銦磷化物(gallium indium phosphide)、上述之組合、及其相似者。此外，基底20可包括絕緣層覆矽(SOI)基底。一般而言，絕緣層覆矽 基底包括半導體材料膜層，例如：磊晶矽(epitaxial silicon)、鍺、矽鍺、絕緣層覆矽、絕緣層覆矽鍺(SGOI)、或上述之組合。基底20可摻雜p型摻質，例如：硼、鋁、鎵、或其相似者；或者，基底亦可摻雜如本領域所知的n型摻質。
基底20可包括主動及被動裝置22。如本領域技藝人士所認知的，各式各樣的裝置，如：電晶體、電容器、電阻器、上述之組合及其相似者均可用於製造半導體裝置100設計的結構或功能要求。可使用任何適宜之方式形成主動及被動裝置22。因其以足以完整描述所繪示之實施例，故圖示中僅顯示部份基底20。
接觸層24係形成於基底20之上。接觸層24可包括摻雜區域於基底20之上。在一些實施例中，接觸層24係直接形成於基底20上或基底20之頂表面中。介電層26係形成於接觸層24之上。介電層26可由氧化物所形成，例如：氧化矽、低介電常數介電質(low-k dielectrics)、高分子、其相似者、或上述之組合。
形成接觸結構50延伸穿過介電層26至接觸層24。接觸結構50可形成於介電層26中之開口中(如下第2A-2F圖所討論的)。接觸結構50包括金屬矽化物層40直接毗鄰(directly adjoining)接觸層24及介電層26。金屬矽化物層40對接觸層24提供低電阻接觸及良好黏著性。在一些實施例中，金屬矽化物層40大抵自接觸層24沿著接觸結構50之整個側壁延伸至介電層26之頂表面26A。由於部份接觸層24可能在形成金屬矽化物層40之矽化製程(silicidation process)中消耗掉，金屬矽化物層 40可具有部份40A之表面延伸於接觸層24之頂表面24A下方。
未反應金屬層32’係位於金屬矽化物層40上。未反應金屬層32’係在形成金屬矽化物層40時未被消耗的金屬層。在一些實施例中，由於整個金屬層在形成金屬矽化物層40時大抵都被消耗掉，而未反應金屬層32’並不存在。黏著層34係形成於未反應金屬層32’上。黏著層34可增進未反應金屬層32’與後續形成之導電插塞42’之間的黏著性，也可避免未反應金屬層32’(亦為矽化製程前之金屬層32，如第2D圖所示)之氧化。
導電插塞42’係形成於黏著層34上，並大抵填滿介電層26中開口之剩餘部份。在一些實施例中，導電插塞42’具有頂表面42A，其與介電層26之頂表面26A大抵為共平面(coplanar)。
第2A-2G為根據一些實施例繪示之半導體裝置100於製造中間階段之剖面圖，而第4圖繪示如第2A-2G圖所示製程之製程流程圖。請參照第2A圖，其顯示於製造中間階段之半導體裝置100，包括：接觸層24、介電層26及開口28。雖未顯示於第2A圖中，接觸層24可形成於基底20上或上方(步驟302)。
接觸層24可包括摻雜區域於基底20之上。接觸層可由矽、矽鍺、磷化矽(silicon phosphide)、碳化矽、其相似者、或上述之組合所形成。可自基底20或自一些其他中間結構磊晶成長(epitaxially growing)接觸層24。在一些實施例中，自形成於基底20中的凹陷中磊晶成長接觸層24。在其他實施例中，經由植入製程摻雜部份基底20形成接觸層24。例如：接觸層24可為電晶體之源極區域或汲極區域。
介電層26係形成於接觸層24之上(步驟304)。介電層26可由氧化物所形成，例如：氧化矽、硼磷矽玻璃(borophosphosilicate glass,BPSG)、未摻雜的矽酸鹽玻璃(undoped silicate glass,USG)、氟矽玻璃(fluorinated silicate glass,FSG)、低介電常數介電質，例如：摻碳氧化物、超低介電常數介電質(extremely low-k dielectrics)，例如：摻雜多孔性碳之二氧化矽、高分子，例如：聚酰亞胺(polyimide)、其相似者、或上述之組合。低介電常數介電材料可具有小於3.9之介電常數。可經由化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、旋塗介電材料(spin-on-dielectric,SOD)製程、其相似者、或上述之組合沉積介電層26。在一些實施例中，介電層26係層間介電質(inter-layer dielectric,ILD)。
在形成介電層26之後，可形成開口28穿過介電層26至接觸層24之頂表面24A(步驟306)。可經由適宜之光微影(photolithography)及蝕刻技術，例如：非等向性乾蝕刻(anisotropic dry etch)形成開口28。
在一些實施例中，開口之形成包括罩幕材料，例如：光阻。在這些實施例中，可於介電層之上沉積及圖案化光阻(未顯示)。光阻可包括習知之光阻材料，例如：深紫外光(deep ultra-violet,DUV)光阻，並可經由例如：旋轉塗佈法(spin-on)製程將光阻沉積於介電層26之頂表面上。或者，亦可利用其他適宜之材料或方法形成或放置光阻。一旦形成光阻後，光阻將透過圖案化光罩(patterned reticle)暴露於能量(例如：光)中，以於暴露於能量中的這些光阻部份中引發反應。接著，光阻成 形後，將移除部份光阻以於光阻中形成開口，並經由此些開口暴露出介電層26之部份頂表面。在圖案化光阻後，可圖案化介電層26以形成開口。
在形成開口28後，可選擇性地(optional)執行清潔製程以移除接觸層24上來自蝕刻製程之原生氧化物(native oxide)或任何殘留物質(步驟308)。此清潔製程可使用氯化氫溶液來執行，且其清潔時間例如約為一分鐘。在一些實施例中，可將露出之接觸層24保持於真空中或無氧或無氧化劑之環境中以避免原生氧化物。
第2B圖繪示形成蓋層30於介電層26及接觸層24之上及開口28中(步驟310)。在一些實施例中，蓋層30大抵於後續形成金屬矽化物層40之製程中消耗完畢。蓋層30可修復接觸層24及介電層26因蝕刻開口28所造成之任何損傷。此外，蓋層30可提高接觸結構50(見第2G圖)及介電層26間之黏著性。
蓋層30可由矽、鍺、矽鍺、碳化矽、磷化矽、其相似者、或上述之組合所形成。在一些實施例中，蓋層30大抵具有與接觸層相同之組成。舉例而言，在使用矽鍺形成接觸層24之實施例中，蓋層30亦由矽鍺所形成。
在接觸層24係部份N型金氧半場效電晶體(NMOS)之實施例中，蓋層30係由矽、磷化矽、碳化矽、其相似者、或上述之組合所形成。在接觸層24係部份P型金氧半場效電晶體(NMOS)之實施例中，蓋層30係由矽、鍺、矽鍺、其相似者、或上述之組合所形成。如第2B圖所繪示，蓋層30包括：部份30A毗鄰(adjoining)接觸層24、部份30B沿開口28之側壁延伸並毗 鄰介電層26及部份30C毗鄰並延伸於介電層26上。在一些實施例中，蓋層30係經由化學氣相沉積、原子層沉積、物理氣相沉積、其相似者、或上述之組合所形成，且蓋層30之厚度介於約10Å至約200Å。可順應性(conformally)沉積蓋層30，以沿開口28之底部及側壁和介電層26之上形成大抵相同之厚度。
在形成蓋層30後，如第2C圖所示，形成金屬層32於蓋層30之上及開口中(步驟312)。在一些實施例中，金屬層32在後續形成金屬矽化物層40之製程中大抵消耗完畢。金屬層32可由鎳、鈷、鈦、鎢、其相似者、或上述之組合所形成。如第2C圖所繪示，金屬層32包括：部份32A位於開口底部、部份32B沿開口28之側壁延伸及部份32C延伸於介電層26上。在一些實施例中，金屬層32係經由物理氣相沉積、原子層沉積、濺鍍沉積、其相似者、或上述之組合所形成，且金屬層32之厚度介於約30Å至約300Å。可順應性沉積金屬層32，以沿開口之底部及側壁和介電層26之上形成大抵相同之厚度。
在形成金屬層32後，如第2D圖所示，形成黏著層34於金屬層32之上及開口中(步驟314)。黏著層34增進金屬層32與後續形成之導電插塞42’(見第2G圖)間的黏著性，並避免金屬層32之氧化。黏著層34可由氮化鈦(titanium nitride)、氮化鉭(tantalum nitride)、其相似者、或上述之組合所形成。如第2D圖所繪示，黏著層34包括：部份34A位於開口底部、部份34B沿開口之側壁延伸及部份34C延伸於介電層26之上。在一些實施例中，黏著層34係經由化學氣相沉積、物理氣相沉積、原子層沉積、其相似者或上述之組合所形成，且黏著層34之厚度介 於約5Å至約50Å。可順應性沉積黏著層34，以沿開口之底部及側壁和介電層26之上形成大抵相同之厚度。
第2E圖繪示自蓋層30及金屬層32形成金屬矽化物層40之矽化製程(步驟316)。金屬矽化物層40之形成包括於半導體裝置100上執行退火製程(annealing process)。退火製程使蓋層30與金屬層32發生反應形成金屬矽化物層40。在一些實施例中，退火製程之執行係使用熱浸入式退火(thermal soaking)、尖峰式退火(spike annealing)、閃光退火(flash annealing)、雷射退火(laser annealing)、其相似者、或上述之組合。在一些實施例中，退火製程係在溫度介於約100℃至約900℃；於包括製程氣體，例如：氬氣、氮氣、其相似者、或上述之組合之氣氛；及壓力介於約770Torr至約1000Torr之下執行。
在形成金屬矽化物層40後，在一些實施例中，仍保留未轉換為金屬矽化物層40之未反應金屬層32’。如第2E圖所繪示，金屬矽化物層40包括：部份40A位於開口底部及毗鄰接觸層24、部份40B沿開口之側壁延伸並毗鄰介電層26及部份40C毗鄰並延伸於介電層26上。在一些實施例中，金屬矽化物層40之底部部份40A之厚度介於約30Å至約300Å，而金屬矽化物層40之側壁部份40B之厚度介於約3Å至約30Å。
第2F圖繪示以導電材料42填入位於介電層26之開口中(步驟318)。在一些實施例中，導電材料42填入開口並延伸至介電層26之上。導電材料42大抵形成後續形成之導電插塞42’(見第2G圖)。在一些實施例中，導電材料42係由鎢所形成。在其他實施例中，導電材料42包括其他金屬或金屬合金，例 如：鋁、銅、氮化鈦、氮化鉭、其相似者、或上述之組合。導電材料可經由執行化學氣相沉積、原子層沉積、物理氣相沉積、濺鍍、其相似者或上述之組合所形成。
如第2G圖所繪示，在導電材料42延伸於介電層26之上的實施例中，可於導電材料42上執行平坦化製程(planarization process)以形成導電插塞42’(步驟320)。在一些實施例中，平坦化製程為化學機械研磨(CMP)製程、蝕刻製程、其相似者、或上述之組合。在平坦化製程之後，導電插塞42’之頂表面42A係大抵與介電層26之頂表面26A為共平面。如第2G圖所繪示，金屬矽化物層40、未反應金屬層32’(如果存在)、黏著層34、及導電插塞42’形成了接觸結構50。
第3圖為根據一些實施例繪示之半導體裝置200的剖面圖。半導體裝置200包括主動裝置150形成於基底202上。在所繪示之實施例中，主動裝置150為電晶體，然於其他實施例中亦可包括各種其他主動及被動裝置，例如：電阻器、電容器、電感器、二極體、變容二極管(varactors)、其相似者、或上述之組合。於一實施例中，主動裝置150為鰭式場效電晶體(FinFET)。
基底202可為部份晶圓，且可能包括半導體材料例如：矽、鍺、鑽石或其相似者。或者，亦可使用化合物材料，例如：矽鍺(silicon germanium)、碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、砷化銦(indium arsenide)、磷化銦(indium phosphide)、矽鍺碳化物(silicon germanium carbide)、鎵砷磷化物(gallium arsenic phosphide)、鎵銦磷化物(gallium indium phosphide)、上述之組合、或其相似者。此外，基底202可包括絕緣層覆矽(SOI)基底。一般而言，絕緣層覆矽基底包括半導體材料膜層，例如：磊晶矽(epitaxial silicon)、鍺、矽鍺、絕緣層覆矽、絕緣層覆矽鍺(SGOI)、或上述之組合。基底202可摻雜p型摻質，例如：硼、鋁、鎵、或其相似者；或者，基底亦可摻雜如本領域所知的n型摻質。因其以足以完整描述所繪示之實施例，故圖示中僅顯示部份基底202。在一些實施例中，基底202為自基底延伸之半導體鰭板。
主動裝置150包括：源極/汲極區域210、閘極介電質204、閘極電極206、閘極間隔物(gate spacers)208、介電層212及接觸結構50。主動裝置150之形成始於形成閘極介電質層(未顯示)及閘極電極層(未顯示)。可經由熱氧化(thermal oxidation)、化學氣相沉積、濺鍍或任何其他適宜之方式形成閘極介電質。在其他實施例中，閘極介電質層包括具有高介電常數之介電材料，例如：介電常數大於3.9。其材料可包括：氮化矽(silicon nitrides)、氧氮化合物(oxynitrides)、金屬氧化物，例如：氧化鉿(HfO2)、鉿鋯氧化物(HfZrOx)、矽鉿氧化物(HfSiOx)、鈦鉿氧化物(HfTiOx)、鋁鉿氧化物(HfAlOx)、其相似者、及其組合或多層結構。於另一實施例中，閘極介電質層可包括蓋層，其可擇自金屬氮化物材料，例如：氮化鈦、氮化鉭、或氮化鉬(molybdenum nitride)。
閘極電極層(未顯示)可形成於閘極介電質層之上。閘極電極層可包括導電材料，且可擇自以下所組成之群組：多晶矽(poly-Si)、多晶矽鍺(poly-SiGe)、金屬氮化物 (metal-nitrides)、金屬矽化物(metal-silicides)、金屬氧化物和金屬。金屬氮化物之例子包括：氮化鎢(tungsten nitride)、氮化鉬、氮化鈦、氮化鉭、其相似者、或上述之組合。金屬矽化物之例子包括：矽化鎢(tungsten silicide)、矽化鈦(titanium silicide)、矽化鈷(cobalt silicide)、矽化鎳(nickel silicide)、矽化鉑(platinum silicide)、矽化鉺(erbium silicide)、其相似者、或上述之組合。金屬氧化物之例子包括：氧化釕(ruthenium oxide)、氧化銦錫(indium tin oxide)、其相似者、或上述之組合。金屬之例子包括：鎢、鈦、鋁、銅、鉬、鎳、鉑、其相似者、或上述之組合。
閘極電極層可經由化學氣相沉積、濺鍍沉積、或其他適宜之技術沉積導電材料。閘極電極層之厚度範圍可介於約200Å至約4,000Å。閘極電極層之頂表面通常為非平面(non-planar)頂表面，其可在閘極電極層圖案化或閘極蝕刻之前平坦化，例如：經由化學機械研磨製程平坦化。在此階段可於閘極電極層中引入或不引入離子，例如：經由離子植入技術引入離子。
在形成閘極電極層後，閘極電極層及閘極介電質層可經圖案化以形成閘極電極206及閘極介電質204。閘極圖案化製程可包括使用適宜之沉積及光微影技術，於閘極電極層上沉積及圖案化閘極罩幕(未顯示)。閘極罩幕可納入常用之罩幕材料，例如(但不限於)：光阻材料、氧化矽、氮氧化矽、及/或氮化矽。可使用電漿蝕刻製程蝕刻閘極電極層及閘極介電質層以形成如第3圖所示之閘極電極206及閘極介電質204。
在形成閘極電極206及閘極介電質204之後，可形成源極/汲極區域210。可經由植入製程植入適當之摻質以補充(complement)基底202中之摻質，藉此摻雜部份基底202以形成源極/汲極區域210。在基底202植入p型摻質(例如：例如：硼、鎵、銦、或其相似者)之實施例中，源極/汲極區域210係植入n型摻質(例如：磷、砷、銻、或其相似者)。可使用閘極電極206作為罩幕對源極/汲極區域210進行植入製程。在一些實施例中，可對經摻雜之源極/汲極區域210進行回火以促進摻質雜質擴散至基底202中。
在另一實施例中，可經由於基底202中形成凹陷(未顯示)並於凹陷中磊晶成長材料來形成源極/汲極區域210。於一實施例中，可經由非等向性蝕刻(anisotropic etch)形成凹陷。或者，可經由等向定向蝕刻製程(isotropic orientation dependent etching process)形成凹陷，並可使用氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)作為蝕刻劑。在形成凹陷之後，可於凹陷中磊晶成長材料來形成源極/汲極區域210。在此磊晶成長製程中，可於製程氣體中加入蝕刻氣體，例如：氯化氫氣體(用以作為蝕刻氣體)，以選擇性地(selectively)於凹陷中成長源極/汲極區域210，而不形成於閘極電極206上。在其他的實施例中，不添加蝕刻氣體或僅添加少量的蝕刻氣體，以使源極/汲極區域210之薄層形成於基底202及閘極電極206上。於另一實施例中，可使用犧牲層(未顯示)覆蓋閘極電極206及基底202以避免磊晶成長於其上。源極/汲極區域210可經由上述之植入方法進行摻雜或在材料成長時進行原位摻雜 (in-situ doping)。
源極/汲極區域210之形成方法包括：原子層沉積、化學氣相沉積，例如：減壓化學氣相沉積(RPCVD)、金屬有機化學氣相沉積(MOCVD)、或其他適用之方法。根據源極/汲極區域210所需之組成，磊晶成長之前驅物可包括：甲矽烷(SiH4)、甲鍺烷(GeH4)、甲基矽烷(SiCH3H3)、磷化氫(PH3)、及/或其相似者，且可調整含矽氣體、含鍺氣體、含碳氣體及含磷氣體之分壓以修改鍺/碳/磷與矽的原子比。
在一些實施例中，源極/汲極區域210的形成可以施加應力於閘極電極206下方之通道區域。在使用矽形成基底202之實施例中，可接著透過選擇性磊晶成長(selective epitaxial growth,SEG)製程形成源極/汲極區域210，且源極/汲極區域210具有晶格常數(lattice constant)不同於矽之材料，例如：矽鍺、碳化矽、或其相似者。源極/汲極區域210中的應力源材料(stressor material)及形成於閘極電極206下方之通道區域的晶格不匹配(lattice mismatch)會施加應力於通道區域，藉此提高載子移動率(carrier mobility)及裝置之整體性能。源極/汲極區域210可經由上述之植入方法進行摻雜或在材料成長時進行原位摻雜。
可經由於閘極電極206及基底202之上毯覆式沉積間隔層(未顯示)來形成閘極間隔物208。間隔層可包括：氮化矽、氮氧化物、碳化矽、氮氧化矽、氧化物、及其相似者，並可使用可用以形成此類膜層之方法來形成，例如：化學氣相沉積、電漿輔助化學氣相沉積、濺鍍沉積、其相似者、或上述之 組合。接著，較佳可經由非等向性蝕刻自閘極電極206及基底202之水平表面移除間隔層，以圖案化閘極間隔物208。
在一些實施例中，源極/汲極區域210包括輕度摻雜區域(未顯示)及重度摻雜區域。在此實施例中，在形成閘極間隔物208之前，可輕度摻雜源極/汲極區域210。形成閘極間隔物208之後，可重度摻雜源極/汲極區域210。這樣就形成了輕度摻雜區域及重度摻雜區域。輕度摻雜區域主要位於閘極間隔物208下方，而重度摻雜區域沿基底202位於閘極間隔物208之外。
在形成閘極電極206後，形成源極/汲極210、閘極間隔物208及介電層212。介電層212可由氧化物所形成，例如：氧化矽、硼磷矽玻璃(BPSG)、未摻雜的矽酸鹽玻璃(USG)、氟矽玻璃(FSG)、低介電常數介電質，例如：摻碳氧化物、超低介電常數介電質，例如：摻雜多孔性碳之二氧化矽、高分子，例如：聚酰亞胺、其相似者、或上述之組合。低介電常數介電材料可具有小於3.9之介電常數。可經由化學氣相沉積、物理氣相沉積、原子層沉積、旋塗介電材料(spin-on-dielectric,SOD)製程、其相似者、或上述之組合沉積介電層212。介電層212亦可稱為層間介電質212。
形成介電層212後，形成穿透介電層212之開口(未顯示)以露出部份源極/汲極210。可使用適宜之光微影及蝕刻技術形成開口，例如：非等向性乾蝕刻。
於介電層212中形成開口後，於開口中形成接觸結構50。可經由相似於上述第2A-2G圖之方式形成接觸結構50， 於此不再贅述。接觸結構50電性耦合源極/汲極區域210至上覆之結構(未顯示)，例如：導電線/導孔及/或其他主動及被動裝置。舉例而言，可於接觸結構50及介電層212之上形成包括由介電材料及導電材料形成交替層(alternating layers)的內連接結構。接觸結構50可電性耦合源極/汲極區域210至此內連接結構。
根據本揭露之實施例，其優點包括提升製程穩定度之低電阻矽化物接觸。尤其，本揭露係在形成接觸開口後，於接觸開口中形成矽化物接觸，而不是在形成接觸前形成矽化物。在此製程中，蓋層係形成於接觸開口內，且金屬層係形成於蓋層之上。接著，這些膜層經退火以形成矽化物層。藉由在形成接觸開口之後形成蓋層，則接觸開口的蝕刻過程、形成介電層、或在形成蓋層之前進行的任何其他處理都不會影響蓋層性質。如此一來，可提昇形成蓋層的操作範圍(processing window)及增進形成接觸的製程穩定性。此外，蓋層可修復蝕刻接觸開口所造成的損傷。
上述列舉概述了一些實施例的特徵，以使此技藝人士對本揭露之各個面向更為明瞭。應了解的是，此技藝人士可以本揭露為基礎設計或改良其他製程及結構，以執行及/或達成與本文不同實施例中所述之相同目的及/或相同之優點。此技藝人士亦應可理解，此類等同結構並未偏離本揭露之精神與範圍，且其可在不偏離本揭露之精神與範圍中做各種改變、取代及變化。
32’‧‧‧未反應金屬層
34‧‧‧黏著層
40‧‧‧金屬矽化物層
42’‧‧‧導電插塞
50‧‧‧接觸結構
150‧‧‧主動裝置
200‧‧‧半導體裝置
202‧‧‧基底
204‧‧‧閘極介電質
206‧‧‧閘極電極
208‧‧‧閘極間隔物
210‧‧‧源極/汲極區域
212‧‧‧介電層

Claims (10)

  1. 一種形成半導體裝置的方法，包括：形成一接觸區於一基底之上；形成一介電層於該接觸區及該基底之上；形成一開口穿透該介電層以暴露出該接觸區之一部份；於該接觸區露出之該部份上及沿著該開口之側壁形成一金屬矽化物層；以及於該開口中填入一導電材料以於該介電層中形成一導電插塞，其中該導電插塞電性耦合至該接觸區。
  2. 如申請專利範圍第1項所述之形成半導體裝置的方法，其中形成該金屬矽化物層包括：沿著該接觸區露出之該部份和該開口之側壁及於該介電層之上形成一含矽蓋層；形成一金屬層於該開口中及該介電層上之該含矽蓋層上；形成一黏著層於該開口中及該介電層上之該金屬層上；以及執行一矽化製程使至少部份該含矽蓋層及該金屬層反應形成該金屬矽化物層。
  3. 如申請專利範圍第2項所述之形成半導體裝置的方法，其中形成該含矽蓋層包括：矽、鍺、矽鍺、碳化矽、磷化矽、或上述之組合。
  4. 如申請專利範圍第2項所述之形成半導體裝置的方法，其中進行該矽化製程的步驟包括：於該基底上執行一退火製程，其中溫度自約100℃至約 900℃；製程氣體包括：氬氣，氮氣、或上述之組合；壓力自約770托(torr)至約1000托。
  5. 如申請專利範圍第1項所述之形成半導體裝置的方法，其中於該接觸區露出之該部份上及沿著該開口之側壁形成該金屬矽化物層至少消耗部份該接觸區。
  6. 如申請專利範圍第1項所述之形成半導體裝置的方法，其中該基底為用以形成一鰭式場效電晶體(FinFET)之一半導體鰭板，而該接觸區為該鰭式場效電晶體之一源/汲極區域，且其中形成該接觸區的步驟包括：蝕刻一凹陷於該半導體鰭板中；於該凹陷中磊晶成長一半導體材料；以及以至少一摻質摻雜該半導體材料以形成該源/汲極區域。
  7. 如申請專利範圍第1項所述之形成半導體裝置的方法，其中該金屬矽化物層大抵沿著該開口之側壁自該接觸區之一頂表面延伸至該介電層之一頂表面。
  8. 如申請專利範圍第1項所述之形成半導體裝置的方法，其中該金屬矽化物層沿著該接觸區具有一第一厚度及沿著該開口之側壁具有一第二厚度，其中該第一厚度自約30Å至約300Å，而該第二厚度自約3Å至約30Å。
  9. 一種形成接觸結構的方法，包括：形成一接觸層於一基底之上；沉積一介電層於該接觸層及該基底之上；圖案化該介電層以形成一開口穿透該介電層，且至少一部分該接觸層係暴露於該開口中； 沿著露出之該接觸層和該介電層之側壁及於該介電層之上沉積一蓋層於該開口中；沉積一金屬層於該開口中及該介電層上之該蓋層之上；沉積一黏著層於該開口中及該介電層上之該金屬層上；以及在沉積該黏著層後，退火該蓋層及該金屬層以於該開口中沿著該接觸層和該介電層之側壁及於該介電層上形成一金屬矽化物層。
  10. 如申請專利範圍第9項所述之形成接觸結構的方法，其中退火該蓋層及該金屬層以形成該金屬矽化物層之步驟，該金屬層之一部份維持未反應並夾設於該金屬矽化物層及該黏著層之間。
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