CN113206045A - 半导体装置的形成方法 - Google Patents

半导体装置的形成方法 Download PDF

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Publication number
CN113206045A
CN113206045A CN202110148791.2A CN202110148791A CN113206045A CN 113206045 A CN113206045 A CN 113206045A CN 202110148791 A CN202110148791 A CN 202110148791A CN 113206045 A CN113206045 A CN 113206045A
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layer
dielectric layer
gate
ferroelectric
region
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赖德洋
彭峻彦
张志宇
杨柏峰
杨世海
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开涉及半导体装置的形成方法。提供负电容场效晶体管与铁电场效晶体管装置与其形成方法。栅极介电堆叠包括铁电栅极介电层。依序沉积非晶的高介电常数的介电层与掺质源层，接着进行沉积后退火。沉积后退火可将非晶的高介电常数的介电层转换成多晶的高介电常数膜，其具有掺质所稳定的结晶晶粒于结晶相中，其中高介电常数的介电层为高介电常数的铁电介电层。在沉积后退火之后，可移除残留的掺质源层。形成栅极于残留的掺质源层(若存在)与多晶的高介电常数膜上。

Description

半导体装置的形成方法
技术领域
本公开实施例涉及高介电常数的铁电介电层的形成方法。
背景技术
半导体装置已用于多种电子应用，比如个人电脑、手机、数码相机、或其他电子设备。半导体装置的制作方法通常为依序沉积绝缘或介电层、导电层、与半导体层的材料于半导体基板上，并采用微影图案化多种材料层以形成电路构件与单元于基板上。
半导体产业持续减少最小结构尺寸以改善多种电子构件(如晶体管、二极管、电阻、电容器、或类似物)的集成密度，可将更多构件整合至给定区域。然而随着最小结构缩小，产生必须解决的额外问题。
发明内容
在一实施例中，半导体装置的形成方法包括形成界面层于基板上；形成高介电常数的介电层于界面层上，其中高介电常数的介电层的至少一部分为非晶；形成掺质源层于高介电常数的介电层上；以及进行第一退火，使高介电常数的介电层转变成高介电常数的铁电介电层，且高介电常数的铁电介电层为多晶。
在一实施例中，半导体装置的形成方法包括：形成界面层于基板上；形成氧化铪层于界面层上，其中氧化铪层的至少一部分为非晶；形成掺质源层于氧化铪层上；在形成掺质源层之后进行第一退火，使掺质源层的掺质扩散至氧化铪层中，以形成高介电常数的铁电介电层，其中高介电常数的铁电介电层为斜晶相的多晶；在进行第一退火之后，移除掺质源层的残留部分；以及形成导电层于高介电常数的铁电介电层上。
在一实施例中，半导体装置包括：半导体区；栅极介电堆叠，位于半导体区上，且栅极介电堆叠包括：界面层，位于半导体区上，且界面层为非铁电；以及铁电介电层，位于界面层上，其中铁电介电层包括多晶材料；掺质源层，位于铁电介电层上；以及栅极，位于掺质源层上，且栅极包括导电层。
附图说明
图1是一些实施例中，鳍状场效晶体管的三维图。
图2至图7、图8A、图8B、图9A、图9B、图10A至图10D、图11A、图11B、图12A、图12B、图13A、图13B、图14A至图14H、图15A、图15B、图16A、及图16B是一些实施例中，制造负电容场效晶体管与铁电场效晶体管的鳍状场效晶体管的中间阶段的剖视图。
图14I是一些实施例中，负电容场效晶体管与铁电场效晶体管的鳍状场效晶体管的铁电栅极介电层的残留极化图。
其中，附图标记说明如下：
A-A，B-B，C-C：剖面
50：基板
51：分隔线
50N，50P，75，89：区域
52：鳍状物
54：绝缘材料
56：隔离区
58：通道区
60：虚置介电层
62：虚置栅极层
64：遮罩层
72：虚置栅极
73：界面层
74：遮罩
76：第一高介电常数的介电层
77：高介电常数的铁电介电层
78：掺质源层
79：残留的掺质源层
80：栅极密封间隔物
82：源极/漏极区
86：栅极间隔物
87：接点蚀刻停止层
88：第一层间介电层
90：凹陷
91，91A，91B：铁电栅极介电层
92：栅极介电层
94：栅极
94A：盖层
94B：功函数调整层
94C：填充材料
96：栅极遮罩
108：第二层间介电层
110：栅极接点
112：源极/漏极接点
具体实施方式
下述详细描述可搭配附图说明，以利理解本公开的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本公开实施例的不同结构。特定构件与排列的实施例是用以简化而非局限本公开。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本公开的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
本公开的多个实施例说明负电容的场效晶体管与铁电场效晶体管装置，以及制作负电容场效晶体管与铁电场效晶体管装置于集成电路中的方法。此处说明的负电容场效晶体管与铁电场效晶体管装置采用的栅极介电堆叠包括铁电介电层与其他非铁电介电层(界面层)的组合。如下详述，实施例包括形成介电层与掺杂介电层的方法，以形成稳定铁电特性的铁电介电层，其可调整制作制程条件以客制化铁电介电层。铁电层可提供具有负电容的层状物，而负电容可与其他介电层的电容结合以提供结合介电堆叠的高电容。此介电堆叠用于装置时(比如作为晶体管的栅极介电层)可提供这些优点。
此处所述的结构与方法的优点，是可调整制作制程以修整铁电介电层的负电容，以符合负电容场效晶体管与铁电场效晶体管所用的漏极电流对栅极电压的规格。本公开实施例所述的负电容场效晶体管为鳍状场效晶体管，其可为形成于鳍状半导体带上的三维金属氧化物半导体场效晶体管。然而应理解的是，本公开实施例可用于其他三维结构如全绕式栅极金属氧化物半导体晶体管或平面结构。
图1显示一些实施例中，鳍状场效晶体管的三维图。鳍状场效晶体管包括鳍状物52于基板50(如半导体基板)上。隔离区56位于基板50中，且鳍状物52自相邻的隔离区56之间向上凸起。虽然说明与图式中的隔离区56与基板50分开，但此处所述的用语基板可为单指半导体基板，或含有隔离区的半导体基板。此外，虽然图式中的鳍状物52为单一的连续材料如基板50，鳍状物52及/或基板50可包括单一材料或多种材料。在此说明内容中，鳍状物52指的是延伸于相邻的隔离区56之间的部分。
栅极介电层92沿着鳍状物52的侧壁与上表面，且栅极94位于栅极介电层92上。源极/漏极区82相对于栅极介电层92与栅极94，位于鳍状物52的两侧中。图1亦显示后续附图所用的参考剖面。剖面A-A沿着栅极94的纵轴，并垂直于鳍状场效晶体管的源极/漏极区82之间的电流方向。剖面B-B垂直于剖面A-A，沿着鳍状物52的纵轴并在鳍状场效晶体管的源极/漏极区82之间的电流方向中。剖面C-C平行于剖面A-A，且延伸穿过鳍状场效晶体管的源极/漏极区。后续附图将依据这些参考剖面以求图示清楚。
此处所述的一些实施例中，采用栅极后制制程形成鳍状场效晶体管。在其他实施例中，可采用栅极优先制程。此外，一些实施例可实施于平面装置如平面场效晶体管。
图2至图14H、图15A至图16B是一些实施例中，制造负电容场效晶体管与铁电场效晶体管的鳍状场效晶体管的中间阶段的剖视图。图2至图7沿着图1所示的参考剖面A-A，差别在于多个鳍状物或鳍状场效晶体管。图8A、图9A、图10A、图11A、图12A、图13A、图14A、图14F、图15A、及图16A沿着图1所示的参考剖面A-A，而图8B、图9B、图10B、图11B、图12B、图13B、图14B至图14E、图14G、图14H、图15B、及图16B沿着图1所示的类似剖面B-B，差别在于多个鳍状物或鳍状场效晶体管。图10C及图10D沿着图1所示的剖面C-C，差别在于多个鳍状物与鳍状场效晶体管。
在图2中，提供基板50。基板50可为半导体基板如基体半导体、绝缘层上半导体基板、或类似物，且其可掺杂(比如掺杂p型或n型掺质)或未掺杂。基板50可为晶圆如硅晶圆。一般而言，绝缘层上硅基板为半导体材料层形成于绝缘层上。举例来说，绝缘层可为埋置氧化物层、氧化硅层、或类似物。可提供绝缘层于基板上，而基板通常为硅基板或玻璃基板。亦可采用其他基板如多层基板或组成渐变基板。在一些实施例中，基板50的半导体材料可包含硅、锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、砷化铟、及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟)、或上述的组合。
基板50具有区域50N与区域50P。区域50N可用于形成n型装置如n型金属氧化物半导体晶体管(比如n型鳍状场效晶体管)。区域50P可用于形成p型装置如p型金属氧化物半导体晶体管(比如p型鳍状场效晶体管)。区域50N可与区域50P物理分隔(比如隔有分隔线51)，且任何数目的装置结构(如其他主动装置、掺杂区、隔离结构、或类似物)可位于区域50N与区域50P之间。
在图3中，鳍状物52形成于基板50中。鳍状物52为半导体带。在一些实施例中，鳍状物52形成于基板50中的方法可为蚀刻沟槽于基板50中。蚀刻制程可为任何可接受的蚀刻制程，比如反应性离子蚀刻、中性束蚀刻、类似制程、或上述的组合。蚀刻可为非等向。
鳍状物的图案化方法可为任何合适方法。举例来说，可采用一或多道光微影制程图案化鳍状物，包括双重图案化或多重图案化制程。一般而言，双重或多重图案化制程可结合光微影与自对准制程所产生的图案间距，可小于采用单一直接的光微影制程所得的图案间距。举例来说，一实施例形成牺牲层于基板上，并采用光微影制程图案化牺牲层。采用自对准制程沿着图案化的牺牲层的侧部形成间隔物。接着移除牺牲层，而保留的间隔物之后可作为遮罩以图案化鳍状物52。在一些实施例中，遮罩可保留于鳍状物52上。
在图4中，形成绝缘材料54于基板50之上与相邻的鳍状物52之间。绝缘材料54可为氧化物如氧化硅、氮化物、或上述的组合，且其形成方法可为高密度等离子体化学气相沉积、可流动的化学气相沉积(比如在远端等离子体系统中沉积化学气相沉积为主的材料，之后硬化材料使其转变成另一材料如氧化物)、类似方法、或上述的组合。亦可采用任何可接受的制程所形成的其他绝缘材料。在所述实施例中，绝缘材料54为可流动的化学气相沉积制程所形成的氧化硅。一旦形成绝缘材料，即可进行退火制程。在一实施例中，多余的绝缘材料54覆盖鳍状物52。虽然图式中的绝缘材料54为单层，一些实施例中的绝缘材料54可为多层。举例来说，一些实施例可先沿着基板50与鳍状物52的表面形成衬垫层(未图示)。之后可形成上述的填充材料于衬垫层上。
在图5中，对绝缘材料54进行移除制程，以移除鳍状物52上的多余绝缘材料54。在一些实施例中，可采用平坦化制程如化学机械研磨、回蚀刻制程、上述的组合、或类似制程。平坦化制程可露出鳍状物52，使平坦化制程完成后的鳍状物52与绝缘材料54的上表面齐平。
在图6中，使绝缘材料54凹陷以形成浅沟槽隔离区56。绝缘材料54凹陷后，区域50N与区域50P中的鳍状物52的上侧部分自相邻的浅沟槽隔离区56之间凸起。此外，浅沟槽隔离区56的上表面可具有图示的平坦表面、凸起表面、凹陷表面(如碟化)、或上述的组合。可由合适蚀刻使浅沟槽隔离区56的上表面平坦、凸起、及/或凹陷。可采用可接受的蚀刻制程使浅沟槽隔离区56凹陷，比如对绝缘材料54具有选择性的蚀刻制程(比如蚀刻绝缘材料54的速率大于蚀刻鳍状物52的速率)。举例来说，氧化物移除步骤可采用稀氢氟酸。
图2至图6所示的制程仅为如何形成鳍状物52的一例。在一些实施例中，鳍状物的形成方法可为外延成长制程。举例来说，可形成介电层于基板50的上表面上，并可蚀刻沟槽穿过介电层以露出下方的基板50。可外延成长同质外延结构于沟槽中并使介电层凹陷，使同质外延结构自介电层凸起以形成鳍状物。此外，一些实施例的异质外延结构可作为鳍状物52。举例来说，可使图5中的鳍状物52凹陷，并外延成长不同于鳍状物52的材料于凹陷的鳍状物52上。在这些实施例中，鳍状物52包括凹陷材料以及位于凹陷材料上的外延成长材料。在其他实施例中，可形成介电层于基板50的上表面上，并可蚀刻沟槽穿过介电层。接着可外延成长不同于基板50的材料的异质外延结构于沟槽中，且可使介电层凹陷，进而使异质外延结构自介电层凸起以形成鳍状物52。一些实施例外延成长同质外延结构或异质外延结构，且可在成长时原位掺杂外延成长的材料，其可省略之前与之后的布植。不过原位掺杂与布植掺质可搭配使用。
此外，外延不同的材料于区域50N(如n型金属氧化物半导体区)与区域50P(如p型金属氧化物半导体区)中具有优点。在多种实施例中，鳍状物52的上侧部分的组成可为硅锗(SixGe1-x，其中x可为0至1)、碳化硅、纯锗或实质上纯锗、III-V族半导体化合物、II-VI族半导体化合物、或类似物。举例来说，形成III-V族半导体化合物的可行材料包括但不限于砷化铟、砷化铝、砷化镓、磷化铟、氮化镓、砷化镓铟、砷化铝铟、锑化镓、锑化铝、磷化铝、磷化镓、或类似物。
如图6所示，可形成合适井区(未图示)于鳍状物52及/或基板50中。在一些实施例中，p型井可形成于区域50N中，而n型井可形成于区域50P中。在一些实施例中，p型井与n型井均形成于区域50N与区域50P中。
在不同井型态的实施例中，可采用光组或其他遮罩(未图示)以达区域50N与区域50P所用的不同布植步骤。举例来说，可形成光阻于区域50N中的鳍状物52与浅沟槽隔离区56上。图案化光阻以露出基板50的区域50P如p型金属氧化物半导体区。可采用旋转涂布技术形成光阻，并采用可接受的光微影技术图案化光阻。一旦图案化光阻，即可在区域50P中进行n型杂质布植，而光阻可作为遮罩以实质上避免p型杂质布植至区域50N如n型金属氧化物半导体区中。n型杂质可为磷、砷、锑、或类似物，且其布植至区域中的浓度可小于或等于1018cm-3，比如介于约1016cm-3至约1018cm-3之间。在布植之后可移除光阻，且移除方法可为可接受的灰化制程。
在布植区域50P之后，可形成光阻于区域50P中的浅沟槽隔离区56与鳍状物52上。图案化光阻以露出基板50的区域50N如n型金属氧化物半导体区。可采用旋转涂布技术形成光阻，并采用可接受的光微影技术图案化光阻。一旦图案化光阻，可进行p型杂质的布植于区域50N中，而光阻可作为遮罩以实质上避免p型杂质布植至区域50P如p型金属氧化物半导体区中。布植至区域中的p型杂质可为硼、二氟化硼、或类似物，其浓度可小于或等于1018cm-3，比如介于约1017cm-3至约1018cm-3之间。在布植之后可移除光阻，且移除方法可为可接受的灰化制程。
在布植区域50N与区域50P之后，可进行退火以活化布植的p型杂质及/或n型杂质。在一些实施例中，外延的鳍状物的成长材料可在成长时原位掺杂，因此可省略布植。然而原位掺杂与布植掺杂可搭配使用。
在图7中，形成虚置介电层60于鳍状物52上。举例来说，虚置介电层60可为氧化硅、氮化硅、上述的组合、或类似物，且其形成方法可为依据可接受的技术进行的沉积或热成长。虚置栅极层62形成于虚置介电层60上，而遮罩层64形成于虚置栅极层62上。可沉积虚置栅极层62于虚置介电层60上，接着平坦化虚置栅极层62。可沉积遮罩层64于虚置栅极层62上。虚置栅极层62可为导电或非导电的材料，比如非晶硅、多晶硅、多晶硅锗、金属氮化物、金属硅化物、金属氧化物、或金属。虚置栅极层62的沉积方法可为物理气相沉积、化学气相沉积、溅镀沉积、或本技术领域已知用于沉积导电材料的其他技术。虚置栅极层62的组成可为其他材料，其对蚀刻隔离区的步骤具有高蚀刻选择性。举例来说，遮罩层64可包含氮化硅、氮氧化硅、或类似物。在此例中，形成单一的虚置栅极层62与单一的遮罩层64于整个区域50N与区域50P上。值得注意的是，图式中的虚置介电层60只覆盖鳍状物52，但此仅用于说明目的。在一些实施例中，虚置介电层60可覆盖浅沟槽隔离区56，并延伸于虚置栅极层62与浅沟槽隔离区56之间。
图8A至图16B显示制造实施例的装置的多种额外步骤。图8A至图16B显示的结构可在区域50N与区域50P中。举例来说，图8A至图16B所示的结构可用于区域50N与区域50P。区域50N与区域50P的结构差异(若存在)将搭配每一图式说明。
在图8A及图8B中，可采用可接受的光微影与蚀刻技术图案化遮罩层64(见图7)以形成遮罩74。接着可将遮罩74的图案转移至虚置栅极层62，以形成虚置栅极72。在一些实施例中(未图示)，亦可将遮罩74的图案转移至虚置介电层60。虚置栅极72覆盖鳍状物52的个别通道区58。遮罩74的图案可用于物理分隔每一虚置栅极72以及与其相邻的虚置栅极。虚置栅极72的纵向亦可实质上垂直于个别的外延的鳍状物52的纵向。
如图8A及图8B所示，可形成栅极密封间隔物80于虚置栅极72、遮罩74、及/或鳍状物52的露出表面上。热氧化或沉积之后，可进行非等向沉积以形成栅极密封间隔物80。栅极密封间隔物80的组成可为氧化硅、氮化硅、氮氧化硅、或类似物。
在形成栅极密封间隔物80之后，可进行轻掺杂源极/漏极区(未图示)所用的布植。在不同装置型态的实施例中，与图6所示的上述布植类似，可形成遮罩如光阻于区域50N上并露出区域50P，并可布植合适型态(如p型)的杂质至区域50P中露出的鳍状物52中。接着可移除遮罩。之后可形成遮罩如光阻于区域50P上并露出区域50N，并可布植合适型态(如n型)的杂质至区域50N中露出的鳍状物52中。接着可移除遮罩。n型杂质可为任何前述的n型杂质，且p型杂质可为任何前述的p型杂质。轻掺杂源极/漏极区的杂质浓度可为约1015cm-3至约1018cm-3。可进行退火以活化布植的杂质。
在图9A及图9B中，形成栅极间隔物86于沿着虚置栅极72与遮罩74的侧壁的栅极密封间隔物80上。栅极间隔物86的形成方法可为顺应性地沉积绝缘材料，接着非等向蚀刻绝缘材料。栅极间隔物86的绝缘材料可为氧化硅、氮化硅、氮氧化硅、碳氮化硅、上述的组合、或类似物。
在图10A及图10B中，形成外延的源极/漏极区82于鳍状物52中，以施加应力至个别的通道区58中，进而改善效能。外延的源极/漏极区82形成于鳍状物52中，使每一虚置栅极72位于个别的相邻多对外延的源极/漏极区82之间。在一些实施例中，外延的源极/漏极区82可延伸至鳍状物52中，亦可穿过鳍状物52。在一些实施例中，栅极间隔物86用于使外延的源极/漏极区82与虚置栅极72分开合适的横向距离，使外延的源极/漏极区82不会向外短接至最终的鳍状场效晶体管其之后形成的栅极。
区域50N如n型金属氧化物半导体区中的外延的源极/漏极区82，其形成方法可为遮罩区域50P如p型金属氧化物半导体区，并蚀刻区域50N中的鳍状物52的源极/漏极区，以形成凹陷于鳍状物52中。接着可外延成长区域50N中的外延的源极/漏极区82于凹陷中。外延的源极/漏极区82可包含任何可接受的材料，比如适用于n型鳍状场效晶体管的材料。举例来说，若鳍状物52为硅，则区域50N中的外延的源极/漏极区82包括的材料可施加拉伸应力于通道区58中，比如硅、碳化硅、碳磷化硅、磷化硅、或类似物。区域50N中的外延的源极/漏极区82可具有自鳍状物52的个别表面隆起的表面，且可具有晶面。
区域50P如p型金属氧化物半导体区中的外延的源极/漏极区82的形成方法，可为遮罩区域50N如n型金属氧化物半导体区，并蚀刻区域50P中的鳍状物52的源极/漏极区，以形成凹陷于鳍状物52中。接着外延成长区域50P中的外延的源极/漏极区82于凹陷中。外延的源极/漏极区82可包含任何可接受的材料，比如适用于p型鳍状场效晶体管的材料。举例来说，若鳍状物52为硅，区域50P中的外延的源极/漏极区82可包含施加压缩应力至通道区58中的材料，比如硅锗、硼化硅锗、锗、锗锡、或类似物。区域50P中的外延的源极/漏极区82亦可具有自鳍状物52的个别表面隆起的表面，且可具有晶面。
可布植掺质至外延的源极/漏极区82及/或鳍状物52以形成源极/漏极区，其与前述形成轻掺杂源极/漏极区的制程类似。之后可进行退火。源极/漏极区的杂质浓度介于约1019cm-3至约1021cm-3之间。源极/漏极区所用的n型及/或p型杂质可为任何前述杂质。在一些实施例中，可在成长时原位掺杂外延的源极/漏极区。
用于形成外延的源极/漏极区82于区域50N与区域50P中的外延制程，可使外延的源极/漏极区的晶面横向地向外扩出鳍状物52的侧壁。在一些实施例中，这些晶面造成相同的鳍状场效晶体管的相邻的源极/漏极区82合并，如图10C所示。在其他实施例中，在完成图10D所示的外延制程之后，相邻的源极/漏极区82维持分开。在图10C及图10D所示的实施例中，栅极间隔物86覆盖鳍状物52的侧壁的一部分，并延伸于浅沟槽隔离区56上以阻挡外延成长。在一些其他实施例中，可调整形成栅极间隔物86的间隔物蚀刻步骤以移除间隔物材料，并使外延成长区可延伸至浅沟槽隔离区56的表面。
在图11A及图11B中，沉积第一层间介电层88于图10A及图10B所示的结构上。第一层间介电层88的组成可为介电材料，且其沉积方法可为任何合适方法如化学气相沉积、等离子体辅助化学气相沉积、或可流动的化学气相沉积。介电材料可包含磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、或类似物。亦可采用任何可接受的制程所形成的其他绝缘材料。在一些实施例中，接点蚀刻停止层87位于第一层间介电层88以及外延的源极/漏极区82与栅极间隔物86之间。接点蚀刻停止层87可包含介电材料如氮化硅、氧化硅、氮氧化硅、或类似物，且其蚀刻速率与上方的第一层间介电层88的材料的蚀刻速率不同。
在图12A及图12B中，可进行平坦化制程如化学机械研磨使第一层间介电层88的上表面与虚置栅极72或遮罩74的上表面齐平。平坦化制程亦移除虚置栅极72上的遮罩74，以及沿着遮罩74的侧壁的栅极密封间隔物80与栅极间隔物86的部分。在平坦化制程之后，虚置栅极72、栅极密封间隔物80、栅极间隔物86、与第一层间介电层88的上表面齐平。综上所述，虚置栅极72的上表面自第一层间介电层88露出。在一些实施例中，可保留遮罩74，而平坦化制程使第一层间介电层88的上表面与遮罩74的上表面齐平。
在图13A及图13B中，以蚀刻步骤移除虚置栅极72(与遮罩74，若存在)，可形成凹陷90。可采用湿式化学蚀刻或干蚀刻制程(如非等向的反应性离子蚀刻)。在移除虚置栅极72时，虚置介电层60可作为蚀刻停止层。在一些实施例中，蚀刻制程包含的蚀刻剂可选择性蚀刻虚置栅极72(与遮罩74，若存在)，而不明显蚀刻第一层间介电层88、接点蚀刻停止层87、或栅极间隔物86与栅极密封间隔物80。在图13A及图13B所示的一些实施例中，亦移除凹陷90中的虚置介电层60的一部分，其采用的蚀刻剂移除虚置介电层60的蚀刻速率大于移除通道区58、浅沟槽隔离区56、第一层间介电层88、栅极间隔物86、与栅极密封间隔物80的蚀刻速率。移除凹陷90中的虚置介电层60的一部分，可露出个别鳍状物52的通道区58。每一通道区58位于相邻的多对外延的源极/漏极区82之间。
应理解不同于图13A及图13B所示的多种结构亦属可能。举例来说，一些其他实施例可只移除虚置栅极72并保留虚置介电层60，而凹陷90露出虚置介电层60。在一些实施例中，可移除栅极密封间隔物80与虚置介电层60的部分。
图14A至图14H显示形成置换栅极层(如介电层与导电层)所用的制程步骤。包含置换栅极介电层与导电层的结构可视作最终栅极结构。此处所述的负电容场效晶体管的鳍状场效晶体管其最终栅极结构，采用的栅极介电堆叠包括非铁电栅极介电层与铁电栅极介电层，并形成于通道区58上。如上述说明，栅极介电堆叠中包含铁电栅极介电层以产生负电容分量，其可与非铁电栅极介电层的电容结合以助增加结合的介电堆叠的电容，进而实施高临界斜率的晶体管(比如增加晶体管的开启电流/关闭电流比例)。由关系式：1/(结合介电堆叠的电容)＝1/(非铁电栅极介电层的电容)-1/(铁电栅极介电层的负电容)可知，铁电栅极介电层的负电容分量可增加结合介电堆叠的电容。
图14A及图14B显示栅极介电层的置换步骤。两个介电层分别为非铁电栅极介电层如界面层73与铁电栅极介电层91。铁电栅极介电层91可为高介电常数的介电层，其介电常数大于氧化硅的介电常数。在一些实施例中，铁电栅极介电层91的介电常数大于约7.0。如下详述，可调整形成这些层状物的制程以得界面层73与铁电栅极介电层91的厚度与介电特性，进而提供栅极介电堆叠所需的电容与低待机电源应用(低关闭电流)所用的特定漏极电流对栅极电压曲线。
图14A及图14B所示的实施例中的界面层73可与凹陷90中的通道区的露出表面(比如侧壁与上表面)相邻，且界面层73的形成方法可为化学氧化露出的半导体。氧化凹陷90中露出的通道区58的半导体，可形成一致的氧化物膜于露出表面上。在一些实施例中，通道区58的半导体可为硅或锗，而界面层73可为氧化硅或氧化锗。在一些实施例中，可进行热氧化技术如快速热退火，其温度为约500℃至约1000℃，且可采用一氧化二氮或浓度为0.1％至100％的稀释氧气。
在一些实施例中，可由湿式化学法氧化露出的半导体如硅，比如将晶圆浸入稀释的臭氧化水浴，其温度可为约20℃至约60℃。臭氧浓度可介于1ppm至30ppm之间。举例来说，可调整氧化条件如快速热氧化制程所用的温度及/或氧浓度，或稀释臭氧化水浴制程所用的臭氧浓度，以将界面层73的厚度调整至约
Figure BDA0002931303870000121
至约2nm。在一些其他实施例中(未图示)，界面层73的形成技术可采用化学气相沉积技术。
如图14A及图14B所示，顺应性地沉积铁电栅极介电层91，以覆盖凹陷90之外的栅极密封间隔物80、栅极间隔物86、第一层间介电层88、与接点蚀刻停止层87。铁电栅极介电层91更延伸至栅极密封间隔物80的侧壁上的凹陷90中、界面层73上、与鳍状物52的通道区58的两侧侧壁之外的浅沟槽隔离区56的露出表面上。在此处所述的实施例中，最终栅极结构中采用的铁电介电材料为斜方晶相的掺杂多晶氧化铪。采用掺质(如硅、镧、锆、类似物、或上述的组合)稳定化斜方晶相的氧化铪，且将掺质导入氧化铪中的方法可采用固体源扩散技术。可调整固体源扩散制程的制程参数，以调整铁电栅极介电层91的铁电特性。在一些实施例中，可采用其他介电材料如氧化锆与氧化铪-氧化锆固体溶液，与掺质如镁、铝、或钇。形成铁电栅极介电层91的方法，将搭配图14B的区域的放大图详述于下。
最终的负电容场效晶体管与铁电场效晶体管装置，可包含界面层73与铁电栅极介电层91。在采用铁电栅极介电层91的实施例中，界面层73的厚度将决定最终的负电容场效晶体管与铁电场效晶体管装置的电流-电压与电容-电压特性是否稳定(比如无磁滞)。若界面层73小于
Figure BDA0002931303870000131
则电性可能不稳定。若界面层73大于2nm，则栅极总电容对晶体管设计目标而言可能过低。
图14C至图14E显示图14B的区域75，在形成铁电栅极介电层91的中间制程步骤时的放大剖视图。形成铁电栅极介电层91的两个实施例如下所述，且图14D及图14E中的个别铁电栅极介电层可分别视作铁电栅极介电层91A及91B。铁电栅极介电层91A及91B可一起视作铁电栅极介电层91。如图14C所示，依序沉积第一高介电常数的介电层76(如非晶氧化铪层)与掺质源层78于界面层73上，且沉积方法可采用化学气相沉积、原子层沉积、等离子体辅助原子层沉积、类似方法、或上述的组合。掺质源层78的材料可包含氧化硅、氧化镧、或氧化锆，以分别用于掺质硅、镧、或锆。掺质源层78的厚度可为约
Figure BDA0002931303870000132
至约
Figure BDA0002931303870000133
且第一高介电常数的介电层76的厚度可为约1nm至约10nm。
一些实施例采用原子层沉积技术形成第一高介电常数的介电层76(如非晶氧化铪层)，可准备羟基化的起始表面(以氢原子封端)。举例来说，每一原子层沉积反应循环包括两个反应脉冲以及每一反应脉冲之后进行的净化步骤。在第一反应脉冲时，可将前驱物气体如烷酰胺铪(如四(乙基甲基酰胺)铪、四(二甲基酰胺)铪、或四(二乙基酰胺)铪)作为形成氧化铪所需的铪原子源。铪源气体导入反应腔室的流速可为约100sccm至约10000sccm，其可搭配载气如氮气、氩气、或氦气导入反应腔室(载气流速可为约100sccm至约10000sccm)，且导入时间可为约0.1秒至约6秒。腔室压力可为约1Torr至约10Torr，且腔室温度可为约200℃至约400℃。来自前驱物气体的铪可取代表面分子以产生表面-气体反应，而新的表面以来自前驱物分子的一对配体封端(若前驱物为四(乙基甲基酰胺)铪，则封端的一对配体为(NMeEt))，且每一对配体结合至一铪原子。
可采用净化气体如氮气、氩气、或氦气进行约0.1秒至约60秒的第一净化脉冲，以自腔室移除副产物与多余的铪源前驱物气体，且净化气体的流速可为约100sccm至约10000sccm。
第一净化脉冲之后，可进行原子层沉积反应循环的第二反应脉冲，其可将第二前驱物气体如臭氧、氧气、水、或重水导入反应腔室，以提供形成氧化铪所需的氧原子。在一些实施例中，氧源气体可搭配载气(如氮气、氩气、或氦气)导入反应腔室，氧源气体的流速可为约100sccm至约10000sccm，载气流速可为约100sccm至约10000sccm，且历时约0.1秒至约60秒。腔室压力可为约1Torr至约10Torr，且腔室温度可为约200℃至约400℃。第二前驱物气体的表面与气体的反应，可在表面分离配体与铪原子。一些实施例采用水或重水，而自由配体与氢结合乙形成气态副产物(如H(NMeEt)或D(NMeEt))，且来自水的OH或重水的OD结合铪以产生新的羟基化表面(以氢原子或氘原子封端)。在采用臭氧与氧气的实施例中，分离的配体可进行后续氧化反应以形成最终副产物如水、甲醛、二氧化碳、一氧化氮、二氧化氮、或类似物。来自副产物水的OH可再羟基化表面。举例来说，一些实施例的第二反应脉冲包括导入臭氧与载气(如氮气或氩气)约1秒至约20秒，且臭氧流速为约500sccm至约10000sccm。腔室压力可为约1Torr至约10Torr，且温度可为约200℃至约400℃。在此实施例中，可采用氮气或氩气作为净化气体。
可进行第二净化脉冲如上述，以自反应腔室移除副产物与多余的氧源气体。
举例来说，上述原子层沉积反应循环包括第一反应脉冲(采用第一前驱物气体)、第一净化脉冲、第二反应脉冲(采用第二前驱物气体如氧源气体)、与第二净化脉冲。上述原子层沉积反应循环可重复任意次数，以形成所需厚度的层状物(如氧化铪层)。
在一些实施例中，可采用等离子体辅助原子层沉积制程形成第一高介电常数的介电层76(如非晶氧化铪层)。举例来说，等离子体辅助原子层沉积的第一反应脉冲与第一净化脉冲可与前述的热原子层沉积制程所用的步骤类似，而等离子体辅助原子层沉积反应循环的第二反应脉冲时，可搭配直接等离子体或远端等离子体导入氧源前驱物气体。射频功率可为约10瓦至约2千瓦，频率可为约10kHz至约20MHz，且直流电偏压可为约0V至约100V。等离子体可采用臭氧、氧气、水、或重水作为制程气体，并采用氩气或氦气作为载气，导入制程气体与载气的时间可为约0.1秒至约60秒，制程气体流速可为约100sccm至约10000sccm，且载气流速可为约100sccm至约10000sccm。腔室压力可为约1000mTorr至约10000mTorr。等离子体可增加氧化物种的反应性，因此等离子体原子层沉积制程的腔室温度可低于上述热原子层沉积制程的腔室温度。举例来说，等离子体辅助原子层沉积制程所用的温度可为约100℃至约400℃。一些实施例采用等离子体辅助原子层沉积，由于低温而可在第一反应脉冲时采用有机金属铪前驱物，比如HyALD的CpHf(NMe2)3，其中Cp指的是茂基环。
掺质源层78的形成方法亦可采用原子层沉积制程。举例来说，掺质源层78的形成方法可采用原子层沉积反应循环，其中第一前驱物气体(如硅源气体、镧源气体、或锆源气体)可提供掺质源层78的掺质原子。硅掺质所用的前驱物可为四氯化硅、硅烷、C6H17NSi(LTO520)、乙硅烷、或类似物。镧掺质所用的前驱物可为La(C5H5)3、La(C11H19O2)3(La(thd)3)、C21H45LaN6(La(FMD)3)、或类似物。锆掺质所用的前驱物可为四氯化锆、Zr(C5H5)(N(CH3)2)3Zr(NCH3C2H5)4(TEMAZ)、[(CH3)2N]4Zr(TDMAZ)、或类似物。第一反应脉冲可历时0.1秒至约60秒，其可将掺质前驱物气体与载气导入反应腔室，掺质气体的流速可为约100sccm至约10000sccm，且载气流速可为约100sccm至约10000sccm。腔室压力可为约1Torr至约10Torr，且温度可为约200℃至约400℃。
原子层沉积的第一反应脉冲之后可为净化脉冲，而净化脉冲之后可为第二反应脉冲。在第二反应脉冲时，可将第二前驱物气体如臭氧、氧气、水、或重水导入反应腔室，以提供表面与气体反应形成掺质氧化物单层所需的氧源。第二反应脉冲可历时0.1秒至60秒，而氧源气体导入反应腔室的流速可为约100sccm至约10000sccm。氧源气体可搭配载气如氮气、氩气、或氦气导入反应腔室，且载气流速可为约100sccm至约10000sccm。在第二反应脉冲之后，可进行另一净化制程以完成反应循环，如上所述。
在一些实施例中，可采用等离子体辅助原子层沉积制程以形成掺质源层78。举例来说，可采用与上述热原子层沉积制程类似的气体及制程参数，进行等离子体辅助原子层沉积制程的第一反应脉冲与第一净化脉冲。
一些实施例在等离子体辅助原子层沉积反应循环的第二反应脉冲时，可搭配直接等离子体或远端等离子体导入氧源前驱物。射频功率可为约10瓦至约2千瓦，频率可为约10kHz至约20MHz，且直流电偏压可为约0V至约100V。等离子体可采用臭氧、氧气、水、或重水作为制程气体搭配载气(如氩气或氦气)，导入制程气体的流速可为约100sccm至约10000sccm，而载气的流速可为约100sccm至约10000sccm，且导入制程气体与载气的时间可为约0.1秒至约60秒。腔室压力可为约1Torr至约10Torr。等离子体可增加氧化物种的反应性，因此等离子体辅助原子层沉积的腔室温度可低于上述热原子层沉积的腔室温度。举例来说，等离子体辅助原子层沉积制程的温度可为约100℃至约400℃。
一些实施例采用等离子体辅助原子层沉积，其可采用掺质所用的额外前驱物(比如硅掺质所用的H2Si[N(C2H5)2]2、镧掺质所用的La(C3H7C5H4)3、或锆掺质所用的ZyALD。
在一些实施例中，可采用多种掺质物种。在形成个别层状物时，可控制原子层沉积或等离子体辅助的原子层沉积的反应循环的数目，以准确控制掺质源层78与第一高介电常数的介电层76的厚度。
在图14D中，进行沉积后退火。在一些实施例中，在氮气环境或稀释的氧气环境中进行沉积后退火。在一些实施例中，沉积后退火可为快速热退火，其温度为约500℃至约1000℃，而浸入时间为约5秒至约10分钟。沉积后退火亦可为峰值退火，其温度为约750℃至约1000℃。沉积后退火可用于使沉积的非铁电的第一高介电常数的介电层76转换成高介电常数的铁电介电层77。举例来说，一些实施例的沉积后退火可使非晶氧化铪层如第一高介电常数的介电层76转换成斜方晶相的掺杂多晶氧化铪层，进而形成高介电常数的铁电介电层77。非晶氧化铪层如第一高介电常数的介电层76为高介电常数的非铁电介电层，而斜方晶相的掺杂多晶氧化铪为高介电常数的铁电介电层。纯氧化铪原本不稳定的斜方晶相，可通过结合掺质原子(如硅、镧、锆、或类似物)至介电层中以稳定化。在沉积后退火使非晶氧化铪结晶时，掺质的一部分可自掺质源层78扩散并取代性地结合至氧化铪中，以形成高介电常数的铁电介电层77。改变沉积后退火制程参数如热预算，可改变最终掺质浓度轮廓与铁电特性。在一些实施例中，高介电常数的铁电介电层77的掺质原子与总原子之间的数目比例，可为约0.5％至约30％的硅掺质、约0.5％至约50％的镧掺质、与约5％至约80％的锆掺质，以提供稳定的高介电常数的铁电介电层77。若掺质原子比例低于上述范围，则不足以稳定斜方晶相的多晶氧化铪，进而减少氧化铪材料的铁电特性。若掺质原子比例高于上述范围，则会减少稳定于斜方晶相中的多晶氧化铪比例，进而减少铁电栅极介电层91的残留极化。残留极化减少，会造成负电容不足。
图14所示的掺质源层78的保留部分，为残留的掺质源层79。残留的掺质源层79与沉积的掺质源层78之间的厚度比例，可为约0.2至约0.8。沉积后退火所减少的厚度(比如沉积的掺质源层78与残留的掺质源层79之间的厚度差异)可为约
Figure BDA0002931303870000171
至约
Figure BDA0002931303870000172
在一些实施例中，残留的掺质源层79保留于负电容场效晶体管中，以作为铁电栅极介电层91A的一部分。铁电栅极介电层91A(包括高介电常数的铁电介电层77与残留的掺质源层79)的总厚度可为约1nm至约12nm。在图14E所示的其他实施例中，可采用RCA湿式清洁制程移除残留的掺质源层79。铁电栅极介电层91B的厚度(与高介电常数的铁电介电层77的厚度相同)可为约1nm至约10nm。若铁电栅极介电层91B(或高介电常数的铁电介电层77)的厚度小于1nm，则最终负电容场效晶体管与铁电场效晶体管装至的栅极介电层可能具有高漏电流及/或低时间相关的介电崩溃寿命。若铁电栅极介电层91B的厚度(或高介电常数的铁电介电层77的厚度)大于10nm，则总栅极电容对目标的晶体管设计而言会过低。移除残留的掺质源层79可改变最终制作的负电容场效晶体管装置中的铁电栅极介电层91的铁电特性，此将搭配图14I详述于下。
图14F及图14G还显示栅极94。栅极94沉积于铁电栅极介电层91上，并填入凹陷90的其余部分。在栅极填入凹陷90之后，可进行平坦化制程如化学机械研磨，以自第一层间介电层88的上表面移除铁电栅极介电层91与栅极94的多余部分。图14F及图14G显示完成平坦化步骤之后的栅极结构。图14G显示鳍状场效晶体管中位于两个栅极密封间隔物80之间的栅极94，沿着鳍状物52的纵轴(如图1所示的剖面B-B)的剖视图。图14F显示鳍状场效晶体管的两个鳍状物52与浅沟槽隔离区56上的栅极结构，沿着栅极94的纵轴的剖面图(比如沿着图1所示的剖面A-A)。在图14F中，栅极结构包括界面层73、铁电栅极介电层91、与栅极94，其沿着鳍状物52的通道区的上表面与侧壁延伸。在一些实施例中，铁电栅极介电层91与栅极94可进一步延伸至超出鳍状物52的两侧侧壁之外的浅沟槽隔离区56上。
图14H为图14G的区域89的放大图。如图14H所示，栅极94可包括含金属材料如氮化钛、氧化钛、氮化钽、碳化钽、钴、钌、铝、钨、上述的组合、或上述的多层。举例来说，虽然图14G显示单层的栅极94，但栅极94可包含任何数目的盖层94A(如衬垫层)、任何数目的功函数调整层94B、与填充材料94C，如图14H所示。在沉积盖层94A之后，可视情况进行盖层后退火。
在一些实施例中，可同时形成区域50N与区域50P中的铁电栅极介电层91，但由分开制程形成栅极94，使每一区中的铁电栅极介电层91具有相同材料，而栅极94可包含不同材料，以达n型金属氧化物半导体与p型金属氧化物半导体晶体管的个别栅极所需的不同功函数。在一些实施例中，可采用相同/分开制程的多种其他组合，以形成每一区中的铁电栅极介电层91及/或栅极94。在采用分开制程时，可采用多种遮罩步骤以遮罩并露出适当的区域。
图14I显示保留残留的掺质源层79(如图14D中的实施例)与移除残留的掺质源层79(如图14E中的实施例)的铁电性质差异。图14I中的图表比较的铁电性质，是铁电栅极介电层91的残留极化。一般而言，介电材料中的电性极化为电场的函数。通常电场＝0时的电性极化＝0。但在铁电介电层中，电性极化与电场的曲线非线性且可有磁滞回路(在电场＝0时的电性极化≠0)。零电场的电性极化可视作残留极化。可施加反向电场使电性极化＝0。磁滞增加分支与下降分支上的残留极化的极性(与反向电场)相反。残留极化可提供负电容，因此提供较陡峭的次临界斜率与较高的开启电流/关闭电流比例。
图14I显示对应图14D及图14E中的实施例(分别标示为14D及14E)的不同残留极化值。此外，第三残留极化值(如图14I所示的点A)对应无掺质源层78所掺杂的氧化铪层。在图14I所示的样品中，来自氧化镧掺质源层78的掺质镧可用于稳定多晶氧化铪的斜方晶相，以形成高介电常数的铁电介电层77，且形成方法可采用900℃的峰值沉积后退火制程。如图14I所示，氧化铪层中包含掺质可增加铁电栅极介电层91的残留极化，进而提供更陡峭的次临界斜率与开启电流/关闭电流比例，如上所述。图14I所示的结果还指出在沉积后退火制程的制程参数之外，移除或不移除最终负电容场效晶体管装置中残留的掺质源层79，可用于调整铁电栅极介电层91的铁电特性(如残留极化与副向电场)。举例来说，对应图14D的实施例的残留极化值的中间值(标示为14D)，其铁电栅极介电层91包括残留的掺质源层79。如图所示，标示为14E的样本可增加残留极化，而对应图14E的实施例中移除残留的掺质源层79。在一些实施例中，移除残留的掺质源层79的最终负电场效晶体管装置中的铁电栅极介电层91的残留极化可高出100％至300％。
如图14I所示的实施例，图14E的实施例的残留极化高于图14D的残留极化，进而提供较高的负电容、较陡峭的次临界斜率、与较高的开启电流/关闭电流比例。额外控制铁电特性(如铁电栅极介电层91的残留极化)有利于设计稳定与关闭状态特性改善的负电容场效晶体管，如上所述。在一些实施例中，可调整沉积后退火制程条件或跳过沉积后退火之后移除掺质源层的步骤，以改变最终负电容场效晶体管装置的铁电栅极介电层91的残留极化(约0.5μC/cm2至约30μC/cm2)。
在图15A及图15B中，沉积第二层间介电层108于第一层间介电层88上。在一些实施例中，第二层间介电层108为可流动的化学气相沉积法所形成的可流动膜。在一些实施例中，第二层间介电层108的组成为介电材料如磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、或类似物，且其沉积方法可为任何合适方法如化学气相沉积或等离子体辅助化学气相沉积。一些实施例在形成第二层间介电层108之前，先使栅极堆叠(包含铁电栅极介电层91与对应的上方栅极94)凹陷，使凹陷直接形成于栅极堆叠之上与栅极间隔物86的相对部分之间，如图15A及图15B所示。栅极遮罩96包括一或多层的介电材料如氮化硅、氮氧化硅、或类似物，其可填入凹陷中。之后可进行平坦化制程以移除延伸于第一层间介电层88上的栅极遮罩96所用的介电材料的多余部分。后续形成的栅极接点110(图16A及16B)可穿过栅极遮罩96，以接触凹陷的栅极94的上表面。
在图16A及图16B的一些实施例中，栅极接点110与源极/漏极接点112穿过第二层间介电层108与第一层间介电层88。源极/漏极接点112所用的开口穿过第一层间介电层88与第二层间介电层108，而栅极接点110所用的开口穿过第二层间介电层108与栅极遮罩96。可采用可接受的光微影与蚀刻技术形成开口。衬垫层(如扩散阻障层、粘着层、或类似物)与导电填充材料形成于开口中。衬垫层可包含钛、氮化钛、钽、氮化钽、或类似物。导电材料可为铜、铜合金、银、金、钨、钴、铝、镍、或类似物。可进行平坦化制程如化学机械研磨，以自第二层间介电层108的表面移除多余材料。保留的衬垫层与导电填充材料可形成源极/漏极接点112与栅极接点110于开口中。可进行退火制程以形成硅化物于外延的源极/漏极区82与源极/漏极接点112之间的界面。源极/漏极接点112物理与电性耦接至外延的源极/漏极区82，而栅极接点110物理与电性耦接至栅极94。可由不同制程或相同制程形成源极/漏极接点112与栅极接点110。虽然图示中的源极/漏极接点112与栅极接点110位于相同剖面中，但应理解每一源极/漏极接点112与栅极接点110可形成于不同剖面中，以避免接点短接。
此处所述的实施例控制沉积后退火制程的制程参数，或移除残留的掺质源层79，可调整铁电介电膜的可调铁电特性(如残留极化与负向电场)，以制作负电容场效晶体管装置的方法具有优点。控制铁电性质如前述，可提供稳定与无磁滞的负电容场效晶体管的鳍状场效晶体管装置，其具有陡峭的次临界斜率。因此本公开的实施例形成的鳍状场效晶体管的互补式金属氧化物半导体集成电路，可具有较高效能与较低的待机能耗。
在一实施例中，半导体装置的形成方法包括形成界面层于基板上；形成高介电常数的介电层于界面层上，其中高介电常数的介电层的至少一部分为非晶；形成掺质源层于高介电常数的介电层上；以及进行第一退火，使高介电常数的介电层转变成高介电常数的铁电介电层，且高介电常数的铁电介电层为多晶。实施例更包括在进行第一退火之后，移除掺质源层的残留部分；以及在移除掺质源层的残留部分之后，形成导电层于高介电常数的铁电介电层上。在一实施例中，移除掺质源层的残留部分的步骤，至少部分为湿式化学制程。在一实施例中，进行第一退火之后，形成导电层于高介电常数的铁电介电层上。在一实施例中，形成导电层之后，掺质源层的残留部分夹设于导电层与高介电常数的铁电介电层之间。在一实施例中，形成掺质源层的步骤包括进行原子层沉积制程。在一实施例中，形成掺质源层的步骤包括进行一或多个等离子体辅助原子层沉积循环。在一实施例中，高介电常数的介电层包括氧化铪。在一实施例中，掺质源层包括硅原子、镧原子、或锆原子。
在一实施例中，半导体装置的形成方法包括：形成界面层于基板上；形成氧化铪层于界面层上，其中氧化铪层的至少一部分为非晶；形成掺质源层于氧化铪层上；在形成掺质源层之后进行第一退火，使掺质源层的掺质扩散至氧化铪层中，以形成高介电常数的铁电介电层，其中高介电常数的铁电介电层为斜晶相的多晶；在进行第一退火之后，移除掺质源层的残留部分；以及形成导电层于高介电常数的铁电介电层上。在一实施例中，掺质源层包括硅原子、镧原子、或锆原子。在一实施例中，第一退火包括峰值退火，其温度介于750℃至1100℃之间。在一实施例中，掺质源层的厚度介于
Figure BDA0002931303870000211
至
Figure BDA0002931303870000212
Figure BDA0002931303870000213
之间。在一实施例中，掺质源层包括氧化硅、氧化镧、或氧化锆。在一实施例中，高介电常数的铁电介电层的厚度介于1nm至10nm之间。
在一实施例中，半导体装置包括：半导体区；栅极介电堆叠，位于半导体区上，且栅极介电堆叠包括：界面层，位于半导体区上，且界面层为非铁电；以及铁电介电层，位于界面层上，其中铁电介电层包括多晶材料；掺质源层，位于铁电介电层上；以及栅极，位于掺质源层上，且栅极包括导电层。在一实施例中，界面层至少部分地包括半导体区的半导体材料的氧化物。在一实施例中，铁电介电层包括稳定的斜方晶相的掺杂氧化铪。在一实施例中，掺杂氧化铪系掺杂硅、镧、或锆。在一实施例中，掺质源层包括氧化镧、氧化硅、或氧化锆。
上述实施例的特征有利于本技术领域中具有通常知识者理解本公开。本技术领域中具有通常知识者应理解可采用本公开作基础，设计并变化其他制程与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中具有通常知识者亦应理解，这些等效置换并未脱离本公开精神与范畴，并可在未脱离本公开的精神与范畴的前提下进行改变、替换、或更动。

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1.一种半导体装置的形成方法，包括：
形成一界面层于一基板上；
形成一高介电常数的介电层于该界面层上，其中该高介电常数的介电层的至少一部分为非晶；
形成一掺质源层于该高介电常数的介电层上；以及
进行一第一退火，使该高介电常数的介电层转变成一高介电常数的铁电介电层，且该高介电常数的铁电介电层为多晶。
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