CN113261075A - 用于形成触点的处理系统和方法 - Google Patents

用于形成触点的处理系统和方法 Download PDF

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CN113261075A
CN113261075A CN201980086259.3A CN201980086259A CN113261075A CN 113261075 A CN113261075 A CN 113261075A CN 201980086259 A CN201980086259 A CN 201980086259A CN 113261075 A CN113261075 A CN 113261075A
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chamber
layer
source
processing
trench
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高拉夫·塔雷贾
仓富敬
阿夫耶里诺斯·V·杰拉托斯
唐先明
桑杰·纳塔拉扬
凯万·卡什菲扎德
陈哲擘
雷建新
沙善·夏尔马
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Applied Materials Inc
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Abstract

本文公开的实施方式包括用于形成触点的处理系统及方法。此处理系统包括多个处理腔室，经配置以沉积、蚀刻和/或退火基板的源极/漏极区。此方法包括在源极/漏极区上方沉积经掺杂半导体层、在沟槽中形成锚定层、以及在沟槽中沉积导体。用于形成触点的方法通过使用集成处理造成降低的触点电阻，此集成处理容许源极/漏极触点形成的各种操作在相同处理系统内执行。

Description

用于形成触点的处理系统和方法
技术领域
本公开内容的实施方式一般涉及一种设备和一种方法，且更特定言之涉及形成触点的一种处理系统和一种方法。
背景技术
晶体管是现代数字处理器和存储器装置的基本装置元件，且已在高功率电子中应用。目前，各种晶体管设计或类型可用于不同应用。各种晶体管类型包括，例如双极结晶体管(BJT)、结场效应晶体管(JFET)、金属氧化物半导体场效应晶体管(MOSFET)、垂直沟道或沟槽场效晶体管、及超结晶体管或多漏极晶体管。在晶体管的MOSFET家族内新兴的一种晶体管为鳍式场效应晶体管(FinFET)。
FinFET可制造在块体半导体基板上，例如硅基板，且包含鳍状结构，其在沿着基板的表面的长度方向上蔓延并在与基板表面正交的高度方向上延伸。此鳍具有狭窄宽度，例如小于250纳米。此鳍可通过绝缘层。包含导电栅极材料与栅极绝缘体的栅极结构可形成在此鳍的一区上方。此鳍的上部分在栅极结构的任一侧上被掺杂以形成邻近于栅极的源极/漏极区。
FinFET具有对于缩减至较小尺寸的互补式MOSFET较佳的静电性质。因为此鳍是三维结构，晶体管的沟道可形成在此鳍的三个表面上，所以FinFET可展现对于占据在基板上的给定表面区域的高电流开关能力。由于沟道和装置可从基板表面提升，与常规的平面MOSFET相比较，在相邻装置之间会有着降低的电场耦合。
半导体设计、制造和操作中的一种关键挑战是触点电阻。例如，FinFET装置的源极和漏极区通过形成源极/漏极触点沟槽的蚀刻处理会被侵蚀，造成增加的触点电阻。增加的触点电阻的一种结果是电路装置的缩减效能，电路装置包括形成在半导体基板上的晶体管与其他装置结构。
因此，需要具有缩减触点电阻的触点。
发明内容
本公开内容的实施方式一般涉及形成触点的处理系统与方法。此处理系统包括多个处理腔室，设置以沉积、蚀刻和/或退火基板的源极/漏极区。此方法包括在源极/漏极区上方沉积经掺杂半导体层、在沟槽中形成锚定(anchor)层、以及在沟槽中沉积导体。形成触点的方法通过使用集成处理造成降低的触点电阻，集成处理容许源极/漏极触点形成的各种操作在相同的处理系统内执行。
在一个实施方式中，提供一种处理系统，包括系统控制器、第一处理腔室、第二处理腔室、与第四处理腔室。控制器经配置以致使第一处理腔室在基板的源极/漏极区的暴露表面上沉积经掺杂半导体层与金属硅化物层。源极/漏极区经由形成在介电材料中的沟槽而暴露，介电材料形成在源极/漏极区上方。控制器经配置以致使第二处理腔室在金属硅化物层与沟槽的侧壁上方形成锚定层。控制器经配置以致使第三处理腔室以导体填充沟槽。控制器经配置以致使第四处理腔室加热基板使得导体在沟槽内回流(reflow)。源极/漏极区具有第一掺杂浓度。经掺杂半导体层具有高于第一掺杂浓度的第二掺杂浓度。
在另一实施方式中，提供一种处理系统，包括多个处理腔室。多个处理腔室包括第一处理腔室，经配置以从基板的源极/漏极区的暴露表面移除污染物，其中源极/漏极区经由形成在介电材料中的沟槽而暴露，介电材料形成在源极/漏极区上方；第二处理腔室，经配置以在源极/漏极区上方相继沉积经掺杂半导体层与金属硅化物层；第三处理腔室，经配置以在金属硅化物层与沟槽的侧壁上沉积阻挡层；第四处理腔室，经配置以在阻挡层上方沉积锚定层；第五处理腔室，经配置以导体填充沟槽；第六处理腔室，经配置以在导体上方沉积覆盖层(overburden layer)；及第七处理腔室，经配置以加热基板使导体在沟槽内回流。源极/漏极区具有第一掺杂浓度。经掺杂半导体层具有高于第一掺杂浓度的第二掺杂浓度。
在又另一实施方式中，提供形成触点的方法，包括在基板的源极/漏极区的暴露表面上沉积经掺杂半导体层，其中源极/漏极区经由形成在介电材料中的沟槽而暴露，介电材料形成在源极/漏极区上方；在经掺杂半导体层上沉积金属硅化物层；在金属硅化物层与沟槽的侧壁上方形成锚定层；以导体填充沟槽；及加热基板以使导体在沟槽内回流。源极/漏极区具有第一掺杂浓度。经掺杂半导体层具有高于第一掺杂浓度的第二掺杂浓度。
附图说明
为了可详细理解本发明的上述特征，通过参照实施方式，其中某些实施方式绘示在随附附图中，可获得简短总结于上的本发明的更特定的说明。然而，将注意到随附附图仅绘示范例实施方式且因而不当作限制本发明的范围，且本发明的范围可容许其他等效实施方式。
图1是根据一个实施方式的形成触点的方法操作的流程图。
图2A至图2D绘示根据一个实施方式的在图1的方法的不同阶段期间的基板的各种视图。
图3绘示根据一个实施方式的基板的截面视图。
图4绘示根据一个实施方式的多腔室处理系统的图解顶视图表。
为了易于理解，已尽可能使用相同附图标记指代附图中共享的相同元件。料想一个实施方式的元件与特征可有利地并入其他实施方式中而不需进一步阐明。
具体实施方式
本文公开的实施方式包括形成触点的处理系统和方法。在各种实施方式中，此方法包括在处理系统中执行接下来的操作而不破坏真空：在基板的晶体管的源极/漏极区的暴露表面上执行预清洁处理，源极/漏极区经由形成在介电材料中的沟槽而暴露，介电材料形成在源极/漏极区上方；通过外延沉积处理在暴露的源极/漏极区上形成硅化物层；通过原子层沉积处理在硅化物层上方形成阻挡层/衬垫层；通过物理气相沉积处理在阻挡层/衬垫层上形成锚定层；通过化学气相沉积处理以导体填充沟槽；和退火基板。此集成处理可形成具有减少的电阻与孔洞的钴触点，从而提供高性能逻辑晶体管。本文公开的实施方式可用于，但不限于，创造具有缩减触点电阻的触点。
前述内容广泛地概述本发明中所述的技术。料想本公开内容的概念可实行用于平面晶体管装置或用于三维晶体管装置，诸如鳍式场效应晶体管(FinFET)、水平环绕式栅极(HGAA)FET、垂直环绕式栅极(VGAA)FET、纳米线沟道FET、应变半导体装置等等。
在此使用时，用语“约”意指标示值的+/-10％变动。应理解到此种变动可包括在本文所提供的任何数值中。
图1是根据一个实施方式的形成触点的方法100的操作的流程图。图2A至图2D绘示根据一个实施方式的在方法100的不同阶段期间的基板200的各种视图。尽管将图1与图2A至图2D结合来说明方法100操作，本领域技术人员将理解到设置以任何次序执行此方法操作的任何系统系落入本文所述的实施方式的范围内。注意到可利用方法100以形成未在本文呈现的任何其他半导体结构。本领域技术人员应认知到形成半导体装置与相关结构的完整处理并未绘示在附图中或在本文中说明。触点可为晶体管或其他半导体装置的一部分。
方法100通过提供基板200进入处理腔室而开始于操作102。处理腔室可为蚀刻腔室。基板200为在本领域中使用的任何基板，且包括任何半导体、绝缘体、或金属材料。如图2A所绘示，基板200包括半导体层202、多个半导体结构204、第一介电材料206、源极/漏极区208、触点蚀刻终止层(CESL)210、及第二介电材料212。多个半导体结构204(只图标出两个)从半导体层202延伸。半导体结构204可为半导体鳍片。半导体层202可由以下材料制造：硅(Si)、锗(Ge)、硅锗(SiGe)、或III/V族化合物半导体，诸如砷化镓(GaAs)或砷化铟镓(InGaAs)。半导体层202可以p型或n型掺杂物来掺杂。在一个实施方式中，半导体层202以p型掺杂物来掺杂，诸如硼(B)。在另一实施方式中，半导体层202以n型掺杂物来掺杂，诸如磷(P)或砷(As)。半导体结构204由与半导体层202相同的材料制造。在一个实施方式中，半导体结构204与半导体层202集成。
第一介电材料206安置在半导体层202上的半导体结构204之间。第一介电材料206可为浅沟槽隔离(STI)区，且可由二氧化硅(SiO2)、氮化硅(Si3N4)、碳氮化硅(SiCN)或其他合适介电材料所制造。
在一个实例中，源极/漏极区208是源极区或漏极区。在另一实例中，源极/漏极区208包括合并的源极/漏极区，如图2A所绘示。在任一实例中，源极/漏极区208由外延地生长在半导体结构204上的半导体材料所制造。源极/漏极区208由Si、Ge、SiGe、或III/V族化合物半导体，诸如GaAs或InGaAs所制造。源极/漏极区208可以p型或n型掺杂物来掺杂。在一个实例中，源极/漏极区208以p型掺杂物来掺杂，诸如B。或者，源极/漏极区208以n型掺杂物来掺杂，诸如P或As。源极/漏极区208可外延地生长在半导体结构204上，且因为在不同表面平面上的不同成长速率，多个小面可被形成致使源极/漏极区208具有钻石形状。
CESL 210形成在第一介电材料206与源极/漏极区208上。CESL 210由介电材料制造，诸如SiO2、Si3N4、SiCN、或前述物的组合。第二介电材料212设置在CESL 210上方。第二介电材料212可为介层电介质，且可由介电材料制造，诸如SiO2、Si3N4、SiCN、或前述物的组合。基板200可进一步包括多个栅极(未图示)，设置在半导体结构204上方并垂直于半导体结构204延伸。
在操作104，在第二介电材料212中形成沟槽214以暴露各源极/漏极区208，如图2B所绘示。通过移除第二介电材料212的一部分来形成沟槽214，而CESL210设置在各源极/漏极区208上方，且暴露各源极/漏极区208的表面216。可由任何合适移除处理形成沟槽214。在一个实例中，通过等离子体蚀刻处理形成沟槽214。
单一源极/漏极区208在各沟槽214中暴露。或者，合并的源极/漏极区208在各沟槽214中暴露，如图2B所绘示。在沟槽214的形成期间可移除源极/漏极区208的一部分。经侵蚀的源极/漏极区208具有增加的触点电阻。沟槽214形成在处理腔室中，其可为反应离子蚀刻(RIE)腔室或其他合适蚀刻腔室。
在操作106，在源极/漏极区208的暴露表面216上执行预清洁处理。预清洁处理移除在源极/漏极区208的表面216上任何污染物，诸如碳或氧化物污染物。预清洁处理可为任何合适蚀刻处理，诸如干式蚀刻、湿式蚀刻、或前述的组合。在一个实例中，预清洁处理包括湿式蚀刻处理与之后的干式蚀刻处理。湿式蚀刻处理可利用氨(NH3)或氮化氢(HF)溶液。干式蚀刻处理可为等离子体蚀刻处理且可利用含氮或含氢蚀刻剂。预清洁处理不实质地移除源极/漏极区208的任何部分。
预清洁处理在处理系统的第一处理腔室中执行，此处理腔室可与操作102和104的处理腔室为相同或不同的处理系统。在一个实例中，预清洁处理在使用远程等离子体源的处理腔室中执行。适用于执行预清洁处理的一种示例性处理腔室为可由加州圣克拉拉市的应用材料公司取得的AKTIV Pre-CleanTM腔室或SiCoNiTM清洁腔室。或者，预清洁处理可在蚀刻腔室中执行，诸如使用感应耦合等离子体(ICP)源的蚀刻腔室。一种示例性蚀刻腔室为经修改的去耦合等离子体氮化(DPN)腔室，其可由加州圣克拉拉市的应用材料公司取得。然而，料想也可应用来自其他制造者的其他合适配置的腔室以执行预清洁处理。
在操作108，在暴露的源极/漏极区208的表面216上形成经掺杂半导体层220，如图2C所绘示。经掺杂半导体层220可通过选择性外延沉积处理形成。经掺杂半导体层220形成在源极/漏极区208的暴露表面上，即，沟槽214的底部上，且由于选择性外延沉积处理而不在沟槽214的侧壁218上。经掺杂半导体层220可由与源极/漏极区208相同的材料制造，除了经掺杂半导体层220中的掺杂浓度高于源极/漏极区208中的掺杂浓度。在一个实施方式中，经掺杂半导体层220通过掺杂物浸泡处理而形成。在掺杂物浸泡处理期间，源极/漏极区208的顶部分(诸如从表面216至预定深度)被转换成经掺杂半导体层220。经掺杂半导体层220可具有从约
Figure BDA0003132551920000061
至约
Figure BDA0003132551920000062
的厚度范围。在一个实施方式中，经掺杂半导体层220中的掺杂浓度与源极/漏极区208中的掺杂浓度的比率在从约1.5:1至约10:1的范围内，例如，约2:1至约6:1。在一个实例中，经掺杂半导体层220中的掺杂浓度是约1×1019原子/cm3至约1×1022原子/cm3。经掺杂半导体层220中的增加掺杂浓度减少触点电阻。
在处理系统的第二处理腔室中执行选择性外延沉积处理。在一个实施方式中，经掺杂半导体层220形成在外延腔室中。外延腔室的一个实例为可由加州圣克拉拉市的应用材料公司取得的降低压力(RP)Epi腔室。然而，料想也可应用来自其他制造者的其他合适配置的腔室以执行选择性外延沉积处理或掺杂物浸泡处理以形成经掺杂半导体层220。
在操作110，通过选择性外延沉积处理在经掺杂半导体层220上形成金属硅化物层222，如图2C所绘示。金属硅化物层222形成在经掺杂半导体层220上，即沟槽214的底部上，且由于选择性外延沉积处理而不在沟槽214的侧壁218上。金属硅化物层222可包括硅化钛(TiSi)、硅化钴(CoSi)、硅化钌(RuSi)、或其他合适金属硅化物。金属硅化物层222可在与经掺杂半导体层220相同的处理腔室中形成。
或者，经掺杂半导体层220与金属硅化物层222可被形成在暴露的源极/漏极区208的表面上的硅化物层209取代，如图3所绘示。在一个实施方式中，通过在暴露的源极/漏极区208的表面上与第二介电材料212的表面216上方形成共形金属层来形成硅化物层209。共形金属层可为使用CVD处理、PECVD处理、高密度CVD处理、PVD处理、电镀处理、溅射处理、蒸发处理、或其他合适处理形成的耐火金属层。金属层可包括钴(Co)、镍(Ni)、钛(Ti)、钌(Ru)、钽(Ta)、钨(W)、前述金属的合金、其他合适金属硅化物、或前述物的任何组合。金属层的某些实例包括但不限于TiSi、RuSi、镍铂(NiPt)合金、镍钯(NiPd)、镍铼(NiRe)、钛钽(TiTa)、或钛铌(TiNb)。
一旦金属层已经形成，诸如通过退火处理而接着加热基板200，使得暴露的源极/漏极区208与金属层反应并形成硅化物层209。退火处理在金属层接触源极/漏极区208的任何情况下致使硅化物反应发生。取决于使用的金属层，硅化物层209可为金属层的硅化物。例如，若金属层包括Co，则硅化物层209包括CoSi。退火处理可在快速热退火(RTA)腔室中执行。一种示例性腔室为可由加州圣克拉拉市的应用材料公司取得的
Figure BDA0003132551920000071
RADOXTMRTP腔室或其他合适腔室。接着通过选择性蚀刻处理移除未反应的金属层以在基板上留下硅化物层209。
在利用硅化物层209的实施方式中，可选的盖层(cap layer)224可形成在硅化物层209上，如图3所绘示。尽管未图示，但是也可在金属硅化物层222上形成盖层224，使得盖层224设置在金属硅化物层222与阻挡层225(或者称为衬垫层)之间和/或锚定层227将被随后形成在盖层224上。盖层224可防止来自随后沉积的锚定层227和/或随后填充在沟槽214中的触点金属的金属扩散并与下方硅化物层209及/或源极/漏极区208反应。盖层224也可作为粘附层以改善随后填充在沟槽214中的触点金属与硅化物层209之间的粘附。
盖层224可为氮化物层。氮化物层可包括但不限于TiN、Si3N4、或金属硅氮化物。盖层224可包括含有过渡金属的金属材料，诸如铱(Ir)或钼(Mo)。在一个实施方式中，盖层224是通过氮化处理形成的氮化物层。氮化处理可包括将暴露的硅化物层209暴露至含氮等离子体或含氮周围环境，使得氮(N)原子与存在于硅化物层209的暴露表面处的原子化学反应以形成表面氮化物层(例如，盖层224)。在某些实施方式中，氮化物区还形成在源极/漏极区208的上部分中。
氮化处理可在使用感应耦合等离子体(ICP)源的等离子体腔室中执行，诸如可由加州圣克拉拉市的应用材料公司取得的经修改的去耦合等离子体氮化(DPN)腔室或其他合适腔室。料想盖层224也可通过任何合适沉积处理而形成，诸如ALD处理、CVD处理、PECVD处理、HDP-CVD处理、低压CVD(LPCVD)处理、PVD处理或任何合适沉积技术。在通过ALD处理形成盖层224的情况中，盖层224可形成在侧壁218与硅化物层209两者上。在此种情况中，盖层224的沉积可在ALD腔室中执行。ALD腔室的一个实例为可由加州圣克拉拉市的应用材料公司取得的OlympiaTM ALD腔室，但是也可利用其他合适腔室。
在操作112，在金属硅化物层222与沟槽214的侧壁218上形成可选的阻挡层225，如图2C所绘示。在盖层224设置在金属硅化物层222上的实施方式中，阻挡层225形成在盖层224上，造成盖层224设置在金属硅化物层222与阻挡层225之间。图3绘示一个实例，其中阻挡层225形成在盖层224与沟槽214的侧壁218上。
阻挡层225可由与盖层224相同的材料所制造。在一个实施方式中，阻挡层225包括TiN。阻挡层225可通过任何合适沉积处理形成，诸如ALD处理、CVD处理、PECVD处理、HDP-CVD处理、低压CVD(LPCVD)处理、PVD处理、或任何合适沉积技术。阻挡层225的沉积在处理系统的第三处理腔室中执行。在一个实施方式中，阻挡层225通过ALD处理而形成。一种示例性腔室为可由加州圣克拉拉市的应用材料公司取得的OlympiaTM ALD腔室，或可利用其他合适腔室。或者，阻挡层225可在与盖层224相同的处理腔室中形成。
在操作114，将锚定层227可选地形成在阻挡层225的暴露表面上，如图2C与图3所示。在不使用阻挡层225的实施方式中，锚定层227形成在金属硅化物层222上(图2C)或盖层224上(图3)。锚定层227进一步改善随后填充在沟槽214中的触点金属与硅化物层209和/或源极/漏极区208之间的粘附。锚定层227可由金属制成，诸如Co、W、Cu、Ru、铝(Al)、金(Au)、银(Ag)、前述物的合金、类似物、或前述物的组合，且可通过CVD处理、ALD处理、PVD处理、ECP处理、或其他合适沉积技术而沉积。
锚定层227的沉积在处理系统的第四处理腔室中执行。在一个实施方式中，在PVD腔室中形成锚定层227。一种示例性腔室是可由加州圣克拉拉市的应用材料公司取得的CirrusTM RT PVD腔室。然而，料想也可应用来自其他制造者的其他合适配置的腔室以执行沉积处理来形成锚定层227。
在操作116，在沟槽214中形成导体226以填充沟槽214，如图2D与图3所绘示。种晶层229可设置在锚定层227与导体226之间。种晶层229可形成在锚定层227的暴露表面上，如图2D所绘示。种晶层229与导体226可由相同或不同材料制成。导体226与种晶层229的合适材料包括但不限于Co、Cu、W、Al、Ru、Ti、Ag、铂(Pt)、钯(Pa)、前述物的合金、前述物的衍生物、或前述物的任何组合。在一个实施方式中，导体226由Co制成。导体226与种晶层229可使用一种或多种沉积处理形成在锚定层227上，诸如CVD处理、PECVD处理、ALD处理、PEALD处理、PVD处理、电镀处理、ECP处理、或其他合适沉积技术。
导体226的形成在处理系统的第五处理腔室中执行。在一个实施方式中，导体226在CVD腔室中形成。一种示例性腔室为可由加州圣克拉拉市的应用材料公司取得的VoltaTMCVD腔室。然而，料想也可应用来自其他制造者的其他合适配置的腔室以执行沉积处理来形成导体226。
在操作118，在某些实施方式中，在以导体226填充沟槽214之后，在导体226与第二介电材料212的暴露表面上形成覆盖层231。覆盖层231可包括金属，其可包括与导体226相同的材料。在一个实施方式中，覆盖层231包括Co。覆盖层231可形成在导体226与第二介电材料212的暴露表面之上，直到达到预定厚度。在覆盖层形成之后，将基板200通过上方论述的热退火处理加热至预定温度以使覆盖层231与导体226的金属回流，从而消除导体226中的缝隙或孔洞。或者，可在覆盖层的形成之前执行热退火处理。
覆盖层231可通过任何合适沉积技术形成，诸如PVD处理、ALD处理、CVD处理、PECVD处理、HDP-CVD处理、低压CVD(LPCVD)处理等等。覆盖层231的沉积可在处理系统的第六处理腔室中执行。在一个实施方式中，覆盖层231在PVD腔室中形成。一种示例性腔室为可由加州圣克拉拉市的应用材料公司取得的VersaTM XT PVD腔室。或者，覆盖层的沉积可在处理系统的第四处理腔室中执行。然而，料想也可应用来自其他制造者的其他合适配置的腔室以执行沉积处理来形成覆盖层。
在操作120，将基板200在热退火处理期间加热至预定温度。热退火处理可在从约200℃至约800℃，例如约300℃至约600℃的温度范围内执行。在热退火处理期间，沟槽214内的导体226的金属可回流以消除导体226中的缝隙或孔洞。若有任何缝隙或孔洞留在导体226中，覆盖层231也可回流以进一步填充沟槽214。热退火处理还可扩大晶粒尺寸、净化导体226(例如Co)和/或降低电阻。因此，获得高质量无孔洞导体226。
热退火处理在处理系统的第七处理腔室中执行。在一个实施方式中，热退火处理在退火腔室中执行。一种示例性腔室是可由加州圣克拉拉市的应用材料公司取得的PyraTM退火腔室。另一示例性腔室为快速热退火(RTA)腔室，诸如可由加州圣克拉拉市的应用材料公司取得的
Figure BDA0003132551920000101
RADOXTM RTP腔室。然而，料想也可应用来自其他制造者的其他合适配置的腔室以执行热退火处理。
在操作122，通过使用诸如化学机械抛光(CMP)的平坦化处理可移除过量导体226(及覆盖层231(若有使用))。平坦化处理从第二介电材料212的顶表面上移除覆盖层231与过量导体226。因此，导体226、种晶层229(若有使用)、锚定层227、阻挡层225和第二介电材料212的顶表面可为共平面。所形成的导电特征可称作触点、栓塞、等等。基板200可经受用于完成晶体管的进一步处理。
在一个实施方式中，平坦化处理在CMP系统中执行。一种示例性系统为可由加州圣克拉拉市的应用材料公司取得的
Figure BDA0003132551920000102
LK PrimeTM CMP系统。然而，料想也可应用来自其他制造者的其他合适配置的CMP系统以执行沉积处理以形成导体226。
可根据本文提供的教导合适地修改的处理系统的实例包括可由位于加州圣克拉拉市的应用材料公司商业上取得的
Figure BDA0003132551920000103
或
Figure BDA0003132551920000104
集成处理系统或其他合适处理系统。料想其他处理系统(包括来自其他制造者)可适于由本文所述的方面得益。
图4绘示根据一个实施方式的多腔室处理系统400的图解顶视图。多腔室处理系统400经配置以在一个或多个基板上执行各种半导体处理方法，诸如上述的方法100。如图标，多腔室处理系统400包括多个处理腔室402、414、416、第一传送腔室404、通过腔室(pass-through chambers)406、第二传送腔室410、装载锁定腔室412、工厂接口420、一个或多个舱430、及系统控制器480。
处理腔室402的每一个耦接至第一传送腔室404。第一传送腔室404也耦接至第一对的通过腔室406。第一传送腔室404具有置中设置的传送机器人(未图示)用以在通过腔室406与处理腔室402之间传送基板。通过腔室406耦接至第二传送腔室410，其耦接至经配置以执行预清洁处理(操作106)的处理腔室414及经配置以执行硅化物层(操作108/110)的处理腔室416。第二传送腔室410具有置中设置的传送机器人(未图示)用以在装载锁定腔室412与处理腔室414和/或处理腔室416之间传送基板。工厂接口420由装载锁定腔室412连接至第二传送腔室410。工厂接口420耦接至装载锁定腔室412的相对侧上的一个或多个舱430。舱430通常为从洁净室为可进出的前开式标准舱(FOUP)。
在某些实施方式中，提供基板至蚀刻腔室以执行沟槽形成处理(例如，操作104)。蚀刻腔室可为多腔室处理系统400的一部分，或蚀刻腔室可为分开的处理工具的一部分。基板接着传送至处理腔室414。根据一个实施方式，在传送至处理腔室414之前，将基板传送至舱430。
将基板传送至处理腔室414，其中执行预清洁处理(例如，操作106)以移除污染物，诸如来自基板的晶体管的源极/漏极区的暴露表面的碳或氧化物污染物。然后，将基板传送至处理腔室416，在该处理腔室中沉积经掺杂半导体层与金属硅化物层(例如，操作108与110)(或在一替代实施方式中，沉积硅化物层209)。在某些实施方式中，处理腔室414和/或处理腔室416与一个或多个处理腔室402的任一者交换。
将基板接着传送至一个或多个处理腔室402，在所述处理腔室中沉积阻挡层(例如，操作112，诸如TiN阻挡层的ALD)、沉积锚定层(例如，操作114，诸如Co锚定层的PVD)、用导体填充沟槽(例如，操作116，诸如Co导体的CVD)、沉积覆盖层(例如，操作118，诸如覆盖层的PVD)、及在基板上执行退火处理(例如，操作120)。因为所有的这些操作106、108、110、112、114、116、118、及120在相同处理系统内执行，所以当基板传送至各种腔室时不打破真空，其减少污染的机率并改善沉积的外延膜的质量。
系统控制器480耦接至处理系统400。系统控制器480控制处理系统400或其部件。例如，系统控制器480控制处理系统的操作，使用直接控制处理系统400的腔室402、404、406、410、412、414、416和/或工厂接口420和/或舱430，或通过控制与腔室402、404、406、410、412、414、416和/或工厂接口420和/或舱430相关的控制器。在操作中，系统控制器480能够从个别腔室进行数据收集与回馈以协调处理系统400的性能。
如图标，系统控制器480包括中央处理单元(CPU)482、存储器484、及支持电路486。CPU 482可为以工业设定使用的任何形式的通用处理器的一者。存储器484可包括非暂时性计算机可读介质和/或机器可读存储装置。存储器484可被CPU 482访问且可为一种或多种存储器，诸如随机存取存储器(RAM)、只读存储器(ROM)、软盘、硬盘、或任何其他形式的数字存储装置，本地或远程的。支持电路486耦接至CPU 482且可包括高速缓存、时钟电路、输入/输出子系统、电源及类似物。系统控制器480经配置以执行存储在存储器484中的方法100。本说明书公开的各种实施方式可被一般地在CPU 482的控制下通过执行存储在存储器484中(或在特定处理腔室的存储器)的计算机指令代码(像是例如计算机程序产品或软件例程)实行。也就是说，计算机程序产品有形地体现在存储器484(或非暂时性计算机可读介质或机器可读存储装置)上。当由CPU482执行计算机指令代码时，CPU 482控制腔室以执行根据各种实施方式的操作。
如上所述，本文提供形成触点的方法与处理系统。处理系统包括多个处理腔室，经配置以沉积、蚀刻和/或退火基板的源极/漏极区。方法包括在源极/漏极区上方沉积经掺杂半导体层、在沟槽中形成锚定层，以及在沟槽中沉积导体。
形成触点的方法通过使用集成处理造成降低的触点电阻，其容许源极/漏极触点形成的各种操作在相同处理系统内执行。因此，当基板在各种处理腔室之间传送时不打破真空，此减少污染的机率并改善沉积层的质量。
尽管前述内容涉及本发明的实施方式，但在不背离本发明的基本范围下可构思出本发明的其他与进一步实施方式，且本发明的范围由随附权利要求书所限定。

Claims (15)

1.一种处理系统，包含：
系统控制器；
第一处理腔室，其中所述系统控制器经配置以致使所述第一处理腔室在基板的源极/漏极区的暴露表面上沉积经掺杂半导体层与金属硅化物层，其中所述源极/漏极区经由形成在介电材料中的沟槽而暴露，所述介电材料形成在所述源极/漏极区上方，且所述源极/漏极区具有第一掺杂浓度而所述经掺杂半导体层具有第二掺杂浓度，所述第二掺杂浓度高于所述第一掺杂浓度；
第二处理腔室，其中所述系统控制器经配置以致使所述第二处理腔室在所述金属硅化物层上方与所述沟槽的侧壁上方形成锚定层；
第三处理腔室，其中所述系统控制器经配置以致使所述第三处理腔室以导体填充所述沟槽；和
第四处理腔室，其中所述系统控制器经配置以致使所述第四处理腔室加热所述基板以使所述导体在所述沟槽内回流。
2.如权利要求1所述的处理系统，进一步包含：
第五处理腔室，其中所述系统控制器经配置以致使所述第五处理腔室在所述锚定层上方沉积阻挡层。
3.如权利要求2所述的处理系统，其中所述系统控制器经配置以致使所述第五处理腔室在所述金属硅化物层上方沉积盖层。
4.如权利要求1所述的处理系统，进一步包含：
第五处理腔室，其中所述系统控制器经配置以致使所述第五处理腔室在所述锚定层与所述金属硅化物层之间沉积盖层。
5.如权利要求1所述的处理系统，进一步包含：
第六处理腔室，其中所述系统控制器经配置以致使所述第六处理腔室在所述导体上方沉积覆盖层。
6.如权利要求5所述的处理系统，其中所述锚定层、所述导体和所述覆盖层包含钴(Co)。
7.一种处理系统，包含：
多个处理腔室，包含：
第一处理腔室，经配置以从基板的源极/漏极区的暴露表面移除污染物，其中所述源极/漏极区经由形成在介电材料中的沟槽而暴露，所述介电材料形成在所述源极/漏极区上方；
第二处理腔室，经配置以在所述源极/漏极区上方相继沉积经掺杂半导体层与金属硅化物层，其中所述源极/漏极区具有第一掺杂浓度而所述经掺杂半导体层具有第二掺杂浓度，所述第二掺杂浓度高于所述第一掺杂浓度；
第三处理腔室，经配置以在所述金属硅化物层上与所述沟槽的侧壁上沉积阻挡层；
第四处理腔室，经配置以在所述阻挡层上方沉积锚定层；
第五处理腔室，经配置以导体填充所述沟槽；
第六处理腔室，经配置以在所述导体上方沉积覆盖层；和
第七处理腔室，经配置以加热所述基板以使所述导体在所述沟槽内回流。
8.如权利要求7所述的处理系统，其中所述第二处理腔室是外延腔室，所述第三处理腔室是原子层沉积(ALD)腔室，所述第四处理腔室是物理气相沉积(PVD)腔室，所述第五处理腔室是化学气相沉积(CVD)腔室，所述第六处理腔室是PVD腔室，并且所述第七处理腔室是退火腔室。
9.如权利要求7所述的处理系统，进一步包含：
第一传送腔室，耦接至所述多个处理腔室的一个或多个，所述第一传送腔室配置为将所述基板传送至耦接至所述第一传送腔室的所述多个处理腔室的一个或多个及从耦接至所述第一传送腔室的所述多个处理腔室的一个或多个接收所述基板。
10.如权利要求9所述的处理系统，进一步包含：
通过腔室，耦接至所述第一传送腔室；和
第二传送腔室，耦接至所述通过腔室。
11.如权利要求7所述的处理系统，其中所述锚定层、所述导体及所述覆盖层包含钴(Co)。
12.一种形成触点的方法，包含：
在基板的源极/漏极区的暴露表面上方沉积经掺杂半导体层，其中所述源极/漏极区经由形成在介电材料中的沟槽而暴露，所述介电材料形成在所述源极/漏极区上方；
在所述经掺杂半导体层上方沉积金属硅化物层；
在所述金属硅化物层上方与所述沟槽的侧壁上方形成锚定层；
以导体填充所述沟槽；和
加热所述基板以使所述导体在所述沟槽内回流；
其中所述源极/漏极区具有第一掺杂浓度，而所述经掺杂半导体层具有第二掺杂浓度，所述第二掺杂浓度高于所述第一掺杂浓度。
13.如权利要求12所述的方法，其中
在第一处理腔室中执行沉积所述经掺杂半导体层与沉积所述金属硅化物层，
在第二处理腔室中执行形成所述锚定层，
在第三处理腔室中执行以所述导体填充所述沟槽，和
在第四处理腔室中执行加热所述基板。
14.如权利要求12所述的方法，进一步包含：
在所述金属硅化物层上方沉积阻挡层；和
在所述导体上方形成覆盖层。
15.如权利要求12所述的方法，进一步包含平坦化所述基板，平坦化所述基板包含化学机械抛光(CMP)处理。
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