CN113451215B - 制造半导体器件的方法 - Google Patents
制造半导体器件的方法 Download PDFInfo
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- CN113451215B CN113451215B CN202110631750.9A CN202110631750A CN113451215B CN 113451215 B CN113451215 B CN 113451215B CN 202110631750 A CN202110631750 A CN 202110631750A CN 113451215 B CN113451215 B CN 113451215B
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- 239000011800 void material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract
本公开涉及制造半导体器件的方法。本公开提供了一种扩大用于形成源极/漏极接触件的工艺窗口的方法。该方法可以包括:接收包括源极/漏极特征的工件,该源极/漏极特征在被限定在两个栅极结构之间的源极/漏极开口中暴露;在源极/漏极开口的侧壁和源极/漏极特征的顶表面之上共形地沉积电介质层;各向异性地蚀刻电介质层,以暴露源极/漏极特征;对电介质层进行注入工艺;以及在执行注入工艺之后,对工件执行预清洁工艺。注入工艺包括非零倾斜角度。
Description
技术领域
本公开涉及制造半导体器件的方法。
背景技术
半导体集成电路(IC)行业经历了指数增长。IC材料和设计的技术进步已经产生了几代IC,每一代都具有比上一代更小和更复杂的电路。在IC演变过程中,功能密度(例如,每芯片面积的互连器件的数量)通常增大,同时几何尺寸(例如,使用制造工艺能够产生的最小组件(或线))减小。这种缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种缩小也增加了加工和制造IC的复杂度。
例如,可以在诸如源极/漏极接触件之类的接触特征的侧壁上形成电介质衬里,以防止泄漏。为了形成电介质衬里,将电介质材料共形地沉积在接触开口之上,并且执行回蚀工艺以暴露面向上方的表面。虽然电介质材料的沉积旨在是共形的,但是可能会在开口的边缘周围发生积聚,导致颈缩轮廓以及导致接触开口减小。当在接触开口中沉积金属填充层以形成金属插塞时,边缘周围的积聚可能阻碍金属填充层的沉积,在金属插塞中导致空隙或其他缺陷。这样的空隙或缺陷可能导致接触电阻增加,甚至导致接触件的故障。因此,尽管现有的形成接触特征的工艺通常足以满足其预期目的,但它们并不是在所有方面都令人满意。
发明内容
根据本公开的一个方面,提供了一种制造半导体器件的方法,包括:在暴露在工件上的源极/漏极开口中的源极/漏极特征的顶表面以及所述源极/漏极开口的侧壁之上共形地沉积电介质层;各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;对所述电介质层进行注入工艺;以及在执行所述注入工艺之后,对所述工件执行预清洁工艺,其中,所述注入工艺包括非零倾斜角度。
根据本公开的另一方面,提供了一种制造半导体器件的方法,包括:接收工件,所述工件包括:第一栅极结构,第二栅极结构,源极/漏极开口,所述源极/漏极开口位于所述第一栅极结构和所述第二栅极结构之间,以及源极/漏极特征,所述源极/漏极特征在所述源极/漏极开口中暴露;在所述源极/漏极开口的侧壁和所述源极/漏极特征的顶表面之上共形地沉积电介质层;各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;对暴露的源极/漏极特征执行第一注入工艺;在执行所述第一注入工艺之后,对所述电介质层执行第二注入工艺以形成经处理部分;以及在执行所述第二注入工艺之后,对所述工件执行预清洁工艺,其中,所述预清洁工艺以比蚀刻所述电介质层更快的速率来蚀刻所述经处理部分。
根据本公开的又一方面,提供了一种制造半导体器件的方法,包括:接收包括源极/漏极特征的工件,所述源极/漏极特征在被限定在两个栅极结构之间的源极/漏极开口中暴露;在所述源极/漏极开口的侧壁和所述源极/漏极特征的顶表面之上共形地沉积电介质层;各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;对所述电介质层执行注入工艺,以形成所述电介质层的经处理部分;在执行所述注入工艺之后,对所述工件执行预清洁工艺;在所述源极/漏极特征之上形成硅化物层;以及在所述硅化物层之上形成金属插塞,其中,所述注入工艺注入氙或氩。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应强调的是,根据行业的标准实践,各种特征没有按比例绘制。事实上,为了讨论的清楚,各种特征的尺寸可能被任意地增大或缩小了。还应强调的是,所附附图仅示出了本公开的典型实施例,因此所附附图不应被视为是对本公开范围的限制,因为本公开可以同样良好地应用于其他实施例。
图1是示出根据本公开的一个或多个方面的制造半导体器件的方法的流程图。
图2至图10示出了根据本公开的一个或多个方面的图1的方法中的各个制造阶段的工件的局部截面图。
具体实施方式
下面的公开内容提供了用于实现所提供的主题的不同特征的许多不同的实施例或示例。以下描述了组件和布置的特定示例以简化本公开。当然,这些只是示例,并不旨在进行限制。例如,在下面的描述中在第二特征之上或上形成第一特征可以包括其中第一特征和第二特征以直接接触方式形成的实施例,还可以包括可以在第一特征和第二特征之间形成附加特征,使得第一特征和第二特征可以不直接接触的实施例。此外,本公开可以在各个示例中重复附图标记和/或字母。这种重复是为了简单和清楚的目的,本身并不指示所讨论的各个实施例和/或配置之间的关系。
此外,本文可使用空间相关术语(例如,“下方”、“之下”、“低于”、“上方”、“上部”等)以易于描述图中所示的一个要素或特征相对于另外(一个或多个)要素或(一个或多个)特征的关系。这些空间相关术语意在涵盖器件在使用或操作中的除了图中所示的定向之外的不同定向。装置可以以其他方式定向(旋转90度或以其他定向),这里使用的空间相关描述符也可以相应地解释。此外,当用“约”和“近似”等来描述数字或数字范围时,该术语旨在涵盖在包括所描述的数字的合理范围内的数字,例如在所描述的数字的+/-10%内或如本领域技术人员所理解的其他值。例如,术语“约5nm”涵盖了从4.5nm至5.5nm的尺寸范围。
本公开涉及但不限于一种扩大用于形成接触特征的工艺窗口的方法。
在IC制造工艺中,正致力于减少接触特征的泄漏而不增加接触电阻。以源极/漏极接触件为例,可以沿着源极/漏极接触开口的侧壁沉积电介质衬里,以改进源极/漏极接触件和相邻的栅极接触件过孔之间的隔离,以减少泄漏。在示例工艺中,将用于电介质衬里的电介质材料共形地沉积在源极/漏极接触开口之上,然后执行回蚀工艺以暴露源极/漏极特征。即使使用回蚀工艺,电介质材料也可能在源极/漏极接触开口的边缘周围积聚,使源极/漏极接触开口具有颈缩轮廓。即,源极/漏极接触开口的顶部开口窗口可能小于源极/漏极接触开口的其余部分的开口窗口。当在源极/漏极接触开口中沉积金属填充层以形成金属插塞时,顶部开口窗口的减小可能减小工艺窗口,因为进入源极/漏极接触开口受到限制。当存在颈缩轮廓时,正在被沉积的金属填充层可能在源极/漏极接触开口基本上被金属填充层填充之前,过早地合并并且关闭顶部开口窗口。结果,可能在金属插塞中形成一个或多个空隙。金属插塞中的空隙使导电金属填充层移位,并可能增加电阻。
本公开提供了一种减少接触特征的泄漏而不增加接触电阻的方法。以形成源极/漏极接触件为例,本公开的方法包括以倾斜角度进行注入工艺,以处理电介质衬里在源极/漏极接触开口的边缘周围的积聚。注入工艺可以包括使用锗、氙、氩或硅,并且倾斜角度可以在约10°至约85°之间。由于这样的处理,边缘周围的积聚可能被损坏或被氧化,使得该积聚变得更容易受到随后的预清洁工艺的影响。预清洁工艺以比蚀刻电介质衬里的其他部分更快的速率来蚀刻经处理部分,消除或减少了边缘周围的积聚。通过将注入工艺与预清洁工艺结合使用,本公开的方法沉积电介质衬里以减少泄漏,但不会将缺陷引入源极/漏极接触件。
现在将参考附图来更详细地描述本公开的各个方面。其中,图1是示出根据本公开的一个或多个方面的形成半导体器件的方法100的流程图。方法100仅是一种示例,而并不意在将本公开限制于方法100中明确说明的内容。可以在方法100之前、期间和之后提供附加步骤,并且可以替换、消除或移动所描述的一些步骤以用于方法100的另外的实施例。为了简单起见,本文没有详细描述所有步骤。下面结合图2至图10来描述方法100,这些附图是根据方法100的实施例的在不同制造阶段的工件200的局部截面图。因为在完成制造工艺后工件200会被制造为半导体器件200,所以根据上下文需要,可以将工件200称为半导体器件200。
如图2至图10所示,将以鳍式场效应晶体管(FinFET)为例来详细描述方法100的操作和优点。然而,本公开的实施例不限于此,并且本公开的实施例可以应用于多桥沟道(MBC)晶体管。FinFET和MBC晶体管是多栅极器件的示例,它们已被引入以通过增加栅极-沟道耦合、减小截止态电流和减小短沟道效应(SCE)来改进栅极控制。FinFET的被抬升的沟道(elevated channel)在多于一侧被栅极结构围绕(例如,栅极结构围绕半导体材料的从衬底延伸的“鳍”的顶部和侧壁)。MBC晶体管的栅极结构可以部分或全部围绕沟道区域延伸,以在两侧或更多侧提供对沟道区域的进入。由于MBC晶体管的栅极结构围绕沟道区域,因此MBC晶体管也可以被称为环绕栅极晶体管(SGT)或栅极全环绕(GAA)晶体管。MBC晶体管的沟道区域可以包括纳米线、纳米片、其他纳米结构、和/或其他合适的结构。沟道区域的形状也给MBC晶体管带来了替代名称,例如纳米片晶体管或纳米线晶体管。此外,本公开的工艺实施例可以应用于形成这样的半导体器件特征,其中填充材料被沉积到被衬里内衬的开口中,并且半导体器件特征中的空隙是不期望的。
首先参考图1和图2。方法100包括块102,在块102处,在工件200之上沉积衬里222。如图2所示,工件200包括衬底202和从衬底202升起的鳍结构204。鳍结构204沿着X方向在长度方向上延伸,并且鳍结构204被划分为源极/漏极区域204SD和沟道区域204C。在图2中示出了一个源极/漏极区域204SD和两个沟道区域204C。在每个沟道区域204C之上设置栅极结构210。在每个源极/漏极区域204SD之上设置源极/漏极特征220。每个栅极结构210包括栅极电介质层206和栅极电极层208。每个栅极结构210的侧壁被第一栅极间隔件层212和第二栅极间隔件层214内衬。在每个栅极结构210之上设置栅极自对准接触(SAC)电介质层216。
衬底202可以是硅衬底。替代地或附加地,衬底202可以包括诸如锗之类的其他元素半导体材料。在一些实施例中,衬底202由诸如碳化硅、砷化镓、砷化铟或磷化铟之类的化合物半导体制成。在一些实施例中,衬底202由诸如硅锗、碳化硅锗、磷化砷化镓或磷化铟镓之类的合金半导体制成。在一些实施例中,衬底202包括一个或多个外延层。例如,衬底202可以包括在体半导体上面的外延层。在一些实施例中,衬底202可以包括埋置的绝缘体层(例如埋置的氧化硅层),并且衬底202可以是绝缘体上硅(SOI)衬底。
鳍结构204从衬底202沿着Z方向垂直地延伸。鳍结构204在X方向上延长。鳍结构204可以由衬底202形成,并且可以与衬底202共享相同的材料。替代地,鳍结构204不仅可以由衬底202形成,而且可以由形成在衬底202上的外延层形成。在这些替代实施例中,鳍结构204可以包括锗(Ge)或其他半导体材料。可以通过使用合适的工艺(例如光刻工艺和蚀刻工艺)来形成鳍结构204。在一些实施例中,使用干法蚀刻或等离子工艺来从衬底202蚀刻鳍结构204。在一些其他实施例中,可以通过双重图案光刻(DPL)工艺或多重图案光刻(MPL)工艺来形成鳍结构204。DPL是一种通过将图案分为两个交错的图案来在衬底上构造该图案的方法。DPL允许增强的特征(例如鳍)密度。形成诸如浅沟槽隔离(STI)结构之类的隔离结构(未示出)以围绕鳍结构204。在一些实施例中,鳍结构204的下部被隔离结构围绕,并且鳍结构204的上部相对于隔离结构突出。换句话说,鳍结构204的一部分被嵌入在隔离结构中。隔离结构防止电气干扰或串扰。
尽管未明确示出,但是栅极电介质层206包括设置在鳍结构204的沟道区域204C上的界面层和设置在该界面层之上的高k电介质层。此处,高k电介质层是指介电常数大于二氧化硅的介电常数(约为3.9)的电介质材料。在一些实施例中,界面层包括氧化硅和卤化硅,并且界面层可以在清洁工艺中形成。此处的示例清洁工艺可包括使用RCA SC-1(氢氧化铵、过氧化氢和水的混合物)和/或RCA SC-2(盐酸、过氧化氢和水的混合物)。然后使用原子层沉积(ALD)、化学气相沉积(CVD)和/或其他合适的方法来在界面层之上沉积高k电介质层。高k电介质层可以包括氧化铪。替代地,高k电介质层可包括其它高k电介质,例如,氧化钛(TiO2)、氧化铪锆(HfZrO)、氧化钽(Ta2O5)、氧化铪硅(HfSiO4)、氧化锆(ZrO2)、氧化锆硅(ZrSiO2)、氧化镧(La2O3)、氧化铝(Al2O3)、氧化锆(ZrO),氧化钇(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、(Ba,Sr)TiO3(BST)、氮化硅(SiN)、氮氧化硅(SiON)、前述项的组合、或其他合适材料。
然后使用ALD、物理气相沉积(PVD)、CVD、电子束蒸发或其他合适的方法来在栅极电介质层206之上沉积栅极电极层208。栅极电极层208可以包括单层结构或者替代地包括多层结构,例如,具有选定功函数以增强器件性能的金属层(功函数金属层)、衬里层、润湿层、粘附层、金属合金或金属硅化物的各种组合。举例来说,栅极电极层208可包括氮化钛(TiN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化钽铝(TaAlC)、碳氮化钽(TaCN)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)、碳化钽(TaC)、氮化钽硅(TaSiN)、铜(Cu)、其他难熔金属、或其他合适的金属材料或前述项的组合。此外,在半导体器件200包括n型晶体管和p型晶体管的情况下,可以针对n型晶体管和p型晶体管分别形成不同的栅极电极层,这些不同的栅极电极层可以包括不同的功函数金属层(例如,以提供不同的n型功函数金属层和p型功函数金属层)。
工件200可以包括沿着栅极结构210的侧壁设置的一个或多个栅极间隔件层。在图2所示的实施例中,工件200包括两个栅极间隔件—第一栅极间隔件层212和位于第一栅极间隔件层212之上的第二栅极间隔件层214。当采用后栅极工艺(或栅极替代工艺)时,首先在沟道区域204C之上形成多晶硅虚设栅极堆叠,并且在虚设栅极堆叠的侧壁之上沉积栅极间隔件层。在随后的工艺中,虚设栅极堆叠被去除并被栅极结构210替代,同时栅极间隔件层中的至少一部分保持沿着栅极结构210的侧壁设置。在一些实施例中,使用CVD、亚大气压CVD(SACVD)或ALD来共形地沉积第一栅极间隔件层212和第二栅极间隔件层214。第一栅极间隔件层212和第二栅极间隔件层214可以由选自以下项的不同电介质材料形成:氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氧化硅、碳氮氧化硅、和/或前述项的组合。在一个实施例中,第一栅极间隔件层212包括碳氮化硅,第二栅极间隔件层214包括氮化硅。
栅极SAC电介质层216可以包括氮化硅、氮氧化硅、碳氮氧化硅、或碳氮化硅。栅极SAC电介质层216的成分可以与第二栅极间隔件层214的成分相同。在图2所示的一些实施例中,在形成栅极SAC电介质层216之后,沉积第二栅极间隔件层214。在这些实施例中,在栅极结构210的顶表面和第一栅极间隔件层212的顶表面之上设置栅极SAC电介质层216。第二栅极间隔件层214沿着第一栅极间隔件层212的侧壁和栅极SAC电介质层216的侧壁连续地延伸。
取决于半导体器件200的导电类型,源极/漏极特征220可以是n型或p型。当源极/漏极特征220是n型时,它可以包括掺杂磷的硅(Si:P)、掺杂砷的硅(Si:As)、或掺杂锑的硅(Si:Sb)。当源极/漏极特征220是p型时,它可以包括掺杂硼的硅锗(SiGe:B)或掺杂镓的硅锗(SiGe:Ga)。可以使用气相外延(VPE)工艺、分子束外延(MBE)工艺、或合适的外延沉积工艺来形成源极/漏极特征220。可以在沉积工艺期间对源极/漏极特征220进行原位掺杂,或者可以使用注入工艺对其进行非原位掺杂。
在块102处,将衬里222共形地沉积在工件200之上。在一些实施例中,衬里222可以包括电介质材料。用于衬里222的示例电介质材料包括氮化硅、碳氮化硅或硅。这些示例电介质材料是致密的,并提供令人满意的防泄漏性能。在一些实施方式中,可以使用CVD、等离子体增强CVD(PECVD)、低压CVD(LPCVD)、或亚大气压CVD(SACVD)来沉积衬里222。因为衬里222是由电介质材料形成的,所以它也可以被称为电介质衬里222。如图2所示,在栅极SAC电介质层216、第二栅极间隔件层214的顶表面、第二栅极间隔件层214的侧壁、以及源极/漏极特征220的顶表面之上设置衬里222。第二栅极间隔件层214的侧壁和源极/漏极特征220的顶表面共同地限定了位于源极/漏极特征220之上的源极/漏极接触开口218。换句话说,衬里222被共形地沉积在源极/漏极接触开口218的表面之上。在图2所示的一些实施例中,用于衬里222的电介质材料可能在源极/漏极接触开口218的顶部开口窗口的边缘周围积聚,而形成边缘积聚224。边缘积聚224可导致图2所示的颈缩轮廓。对于要沉积到源极/漏极接触开口中的材料,这种颈缩轮廓可能限制接近或进入源极/漏极接触开口218。如上所述,当随后在源极/漏极接触开口218中沉积金属填充层时,图2中代表性地示出的边缘积聚224可能导致空隙。
参照图1和图3,方法100包括块104,在块104处,对衬里222进行凹陷。在一些实施例中,在块104处,对工件200进行各向异性蚀刻工艺,以去除被设置在源极/漏极特征220上的衬里222。如图3所示,在块104的操作结束时,在源极/漏极接触开口218中暴露源极/漏极特征220的至少一部分,并且衬里222的位于栅极SAC电介质层216上的部分的厚度减小。在一些实施方案中,各向异性蚀刻工艺可以包括反应离子蚀刻(RIE)工艺,其使用氢、含氟气体(例如,CF4、SF6、CH2F2、CHF3、和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4、和/或BCl3)、含溴气体(例如,HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体、和/或前述项的组合。在块104处进行凹陷之后,衬里222可具有约0.5nm至约5nm之间的厚度。在一些实施例中,在块104处的各向异性蚀刻工艺未完全去除边缘积聚224,并且基本上未减小衬里222的沿着源极/漏极接触开口218的侧壁的厚度。参照图3,源极/漏极接触开口218包括沿着X方向的底部开口宽度(W1)和顶部开口宽度(W2)。在一些实施例中,当顶部开口宽度W2在约10nm至约15nm之间时,顶部开口宽度W2比底部开口宽度W1小了约1nm至约5nm之间的颈缩偏差。
参照图1和图4,方法100包括块106,在块106处,执行第一注入工艺300。相比于n型器件的益处,执行第一注入工艺300更多地是为了p型器件的益处。在某些情况下,由于锗的聚集,p型源极/漏极特征220可能具有不均匀的锗分布,这可导致在其上形成不令人满意的硅化物。在一些实施例中,第一注入工艺300注入锗(Ge),以在p型源极/漏极特征220的暴露表面上提供均匀的锗分布。因为第一注入工艺300针对源极/漏极接触开口218下方的源极/漏极特征220,所以第一注入工艺300包括相对于Z方向的零度(0°)倾斜角度,这是垂直于衬底202的顶表面的方向。为了防止对源极/漏极特征220的损伤,第一注入工艺300包括约1keV至约10keV之间的中等离子束能量,以及约5×1013离子/cm2至约2×1014离子/cm2之间的注入剂量。在一些实施例中,第一注入工艺300在约-100℃至约300℃之间的温度下执行。第一注入工艺300可以被称为预硅化物注入工艺。
参照图1、图5和图6,方法100包括块108,在块108处,执行第二注入工艺400。与针对源极/漏极特征220的第一注入工艺300不同,第二注入工艺400的目标并非是源极/漏极特征220,而是针对边缘积聚224的。根据本公开,第二注入工艺400被配置为对边缘积聚造成损伤,以便使其更易于被随后的预清洁工艺500(将在下文中描述)影响。因此,第二注入工艺400包括为非零角度的倾斜角度θ。在一些实施例中,第二注入工艺400的倾斜角度θ相对于Z方向可以在约10°至约85°之间。因为第二注入工艺400并不旨在使源极/漏极特征220中的锗分布均匀,所以第二注入工艺400可以包括除锗(Ge)以外的离子种类。在一些实施例中,第二注入工艺400包括诸如锗(Ge)、硅(Si)、氙(Xe)或氩(Ar)之类的离子物质。在一个实施例中,第二注入工艺400包括使用氙(Xe)或氩(Ar)。因为第二注入工艺400用于对边缘积聚224造成损伤,所以第二注入工艺400的离子束能量和剂量可以大于第一注入工艺300的离子束能量和剂量。在一些实施例中,第二注入工艺400可包括约1keV与约50keV之间的离子束能量,以及约5×1013离子/cm2至约1×1016离子/cm2之间的剂量。第二注入工艺400可以在约-100℃至约500℃之间的温度下执行。在上述注入条件下,第二注入工艺400可造成对衬里222的局部损伤,并且将衬里222的在离子束的视线内的一部分转换为经处理部分2220。离子束的视线外的衬里222可基本上不被损伤或氧化。在图6所示的一些实施例中,经处理部分2220可以包括衬里222的位于栅极SAC电介质层216之上的部分以及位于边缘224周围的积聚(或边缘积聚224)附近的部分。当第二注入工艺400的真空被破坏并且工件200被暴露于含氧环境时,由于第二注入工艺400造成的损伤,经处理部分2220可被氧化。经处理部分2220可以包括氮氧化硅、碳氮氧化硅、或氧化硅。因此,经处理部分2220可以被视为衬里222的受损部分或氧化部分(如果被氧化的话)。观察到,当在第二注入工艺400中使用氙(Xe)或氩(Ar)时,可以在经处理部分2220中检测到微量的氙(Xe)或氩(Ar)。
可以调节第二注入工艺400的倾斜角度θ和离子束能量以实现经处理部分2220的不同形状或深度。例如,当倾斜角度θ在约10度至约30度之间时,第二注入工艺400的视线可以进一步向下到达源极/漏极接触开口218。结果,经处理部分2220可以进一步向下延伸至源极/漏极接触开口218。当倾斜角度θ在约30度至约60度之间时,第二注入工艺400的视线可正面影响边缘部分224并适度地向下到达源极/漏极接触开口218。当倾斜角度θ在约60度至约85度之间时,第二注入工艺400的视线不太可能向下到达源极/漏极接触开口218,并且经处理部分2220几乎不向下延伸至源极/漏极接触开口218。倾斜角度θ的确定可以是诸如接触开口尺寸、寄生电容、以及对源极/漏极特征220的损坏之类的平衡因素的结果。通常,较小的倾斜角度θ可导致源极/漏极接触开口218增大、(在栅极结构210和要形成的源极/漏极接触件之间的)寄生电容增加、以及对源极/漏极特征220的损坏。较大的倾斜角度θ可能不会使源极/漏极接触开口过多增大,但是其不太可能使寄生电容增加或者对源极/漏极特征220造成损坏。在一些实施例中,当第二注入工艺400包括足够的离子束能量时,离子物质可能渗透到第二栅极间隔件层214中,并且在第二栅极间隔件层214的靠近边缘积聚224的部分中引起局部损伤。在这些实施例中,第二注入工艺400还可以使第二栅极间隔件层214的一部分易受预清洁工艺500(将在下面描述)的影响。
参照图1和图7,方法100包括块110,在块110处,执行预清洁工艺500。在一些实施例中,预清洁工艺500可包括使用氢氟酸、氨和水。观察到,在块110处,预清洁工艺500以比其去除衬里222更快的速率来去除经处理部分2220。结果,如图7所示,块110处的预清洁工艺500可以减小边缘积聚224的厚度或隆起,以在源极/漏极接触开口218的顶部开口窗口处形成漏斗轮廓2240。漏斗轮廓2240提供了对源极/漏极接触开口218的无阻碍进入。同样如图7所示,预清洁工艺500减小了经处理部分2220的厚度,而衬里222的沿着源极/漏极接触开口218的侧壁的厚度基本上保持不变。虽然未明确示出,但是在其中第二栅极间隔件层214的靠近边缘积聚224的部分也被第二注入工艺400处理和损坏的实施例中,预清洁工艺500还可以去除第二栅极间隔件层214的经处理部分。在这些实施例中,暴露的第二栅极间隔件层214可以限定漏斗轮廓2240的侧壁的一部分。
参照图1和图8,方法100包括块112,在块112处,在源极/漏极特征220之上形成硅化物层226。在一些实施例中,为了减小接触电阻,可以通过在源极/漏极接触开口218之上沉积金属层(或金属前体层)并且执行退火工艺以在金属层和源极/漏极特征220之间产生硅化,来在暴露的源极/漏极特征220上形成硅化物层226。用于形成硅化物层226的合适的金属层可以包括钛(Ti)、钽(Ta)、镍(Ni)、钴(Co)或钨(W)。硅化物层226可以包括硅化钛(TiSi)、氮化硅钛(TiSiN)、硅化钽(TaSi)、硅化钨(WSi)、硅化钴(CoSi)、或硅化镍(NiSi)。在一些实施例中,在退火工艺之后,未被转化为硅化物层226的金属层被去除。在一些替代实施例中,未反应的金属层保留在原处以用作导电衬里。
参照图1和图9,方法100包括块114,在该块114处,在工件200之上沉积金属填充层228。在形成硅化物层226之后,可以将金属填充层228沉积到源极/漏极接触开口218中。金属填充层可以包括氮化钛(TiN)、钛(Ti)、钌(Ru)、镍(Ni)、钴(Co)、铜(Cu)、钼(Mo)、钨(W)、钽(Ta)、或氮化钽(TaN)。如图9所示,由于通过第二注入工艺400和预清洁工艺500的组合而产生的漏斗轮廓2240,用于将金属填充层228沉积到源极/漏极接触开口218中的工艺窗口被显著增大并且形成空隙的可能性被显著降低。
参照图1和图10,方法100包括块116,在块116处,工件200被平坦化。如图10所示,在沉积金属填充层228之后,可以对工件200进行平坦化工艺(例如CMP工艺),以去除多余的材料并提供平坦的顶表面。在块116处的操作结束之后,形成源极/漏极接触件230。当沿着Y方向观察时,源极/漏极接触件230包括底部230B和顶部230T,底部230B设置在衬里222的两个侧壁部分之间,顶部230T设置在经处理部分2220的两个侧壁部分之间。顶部230T设置在底部230B之上。与衬里222相比,经处理部分2220还包括氧、微量的氙(Xe)或微量的氩(Ar)。此外,由于第二注入工艺400,经处理部分2220可能比衬里222包含更多的缺陷。如图10所示,因为源极/漏极接触件230被形成在具有漏斗轮廓2240的源极/漏极接触开口218中,所以源极/漏极接触件230也共享漏斗轮廓2240。源极/漏极接触件230可以被称为金属插塞。
基于以上讨论,可以看出,本公开提供了优于相关工艺的优点。然而,应当理解,其他实施例可以提供附加的优点,并且在此不一定公开了所有优点,并且没有特定优点对于所有实施例是必需的。例如,一个优点是,当电介质材料被共形地沉积以形成衬里时,本公开中所公开的工艺利用倾斜注入工艺来处理电介质材料在接触开口的边缘周围的积聚。倾斜注入工艺可以将衬里的一部分转换为被倾斜注入工艺损坏的经处理部分。经处理部分尤其容易受到在形成硅化物层之前执行的预清洁工艺的影响。预清洁工艺可以去除或减少边缘周围的电介质材料的积聚,从而扩大接触开口的顶部开口。顶部开口可以具有漏斗形状。当将金属填充层沉积到接触开口中以形成接触特征时,扩大的顶部开口允许较大的工艺窗口。
本公开的一个方面涉及一种方法。该方法包括:在暴露在工件上的源极/漏极开口中的源极/漏极特征的顶表面以及源极/漏极开口的侧壁之上共形地沉积电介质层;各向异性地蚀刻电介质层,以暴露源极/漏极特征;对电介质层执行注入工艺;以及在执行注入工艺之后,对工件执行预清洁工艺。注入工艺包括非零倾斜角度。
在一些实施例中,电介质层包括氮化硅、碳氮化硅或硅。在一些实施方式中,注入工艺包括使用氙或氩。在一些情况下,非零倾斜角度在约10°至约85°之间。在一些实施例中,注入工艺导致电介质层的氧化以形成电介质层的氧化部分,并且预清洁工艺去除电介质层的氧化部分。在一些情况下,注入工艺导致对电介质层的损坏以形成电介质层的受损部分,并且预清洁工艺去除电介质层的受损部分。在一些情况下,该方法还可以包括在注入工艺之前,对工件执行预硅化物注入工艺。预硅化物注入工艺用锗来注入暴露的源极/漏极特征。在一些实施例中,预硅化物注入工艺包括零度倾斜角度。
本公开的另一方面涉及一种方法。该方法包括:接收工件,该工件包括第一栅极结构、第二栅极结构、位于所述第一栅极结构和所述第二栅极结构之间的源极/漏极开口、以及在所述源极/漏极开口中暴露的源极/漏极特征;在源极/漏极开口的侧壁和源极/漏极特征的顶表面之上共形地沉积电介质层;各向异性地蚀刻电介质层,以暴露源极/漏极特征;对暴露的源极/漏极特征执行第一注入工艺;在执行第一注入工艺之后,对电介质层执行第二注入工艺以形成经处理部分;以及在执行第二注入工艺之后,对工件执行预清洁工艺。预清洁工艺以比蚀刻电介质层更快的速率来蚀刻经处理部分。
在一些实施例中,工件还包括沿着源极/漏极开口的侧壁设置的栅极间隔件,并且共形地沉积电介质层将电介质层沉积在栅极间隔件上。在一些实施方式中,预清洁工艺包括使用氢氟酸、氨、或水。在一些实施方式中,电介质层包括氮化硅、碳氮化硅或硅。在一些情况下,第一注入工艺包括使用锗,并且第二注入工艺包括使用氙或氩。在一些实施例中,第一注入工艺包括零度倾斜角度,并且第二注入工艺包括非零倾斜角度。在一些实施例中,第二注入工艺的离子束能量大于第一注入工艺的离子束能量。在一些实施例中,第二注入工艺的注入剂量大于第一注入工艺的注入剂量。在一些实施方式中,第二注入工艺包括约-100℃至约500℃之间的工艺温度。
本公开的又一方面涉及一种方法。该方法包括:接收包括源极/漏极特征的工件,源极/漏极特征在被限定在两个栅极结构之间的源极/漏极开口中暴露;在源极/漏极开口的侧壁和源极/漏极特征的顶表面之上共形地沉积电介质层;各向异性地蚀刻电介质层,以暴露源极/漏极特征;对电介质层执行注入工艺,以形成电介质层的经处理部分;在执行注入工艺之后,对工件执行预清洁工艺,在源极/漏极特征之上形成硅化物层;以及在硅化物层之上形成金属插塞。注入工艺注入氙或氩。
在一些实施例中,在各向异性地蚀刻电介质层之后,源极/漏极开口包括颈缩轮廓,并且预清洁工艺通过去除经处理部分来减小颈缩轮廓。在一些实施方式中,形成硅化物层包括:在工件之上沉积金属前体;使工件退火,以在金属前体和源极/漏极特征之间引起硅化,从而形成硅化物层;以及去除沿着源极/漏极开口的侧壁的金属前体。
前述内容概述了若干实施例的特征,以便本领域技术人员可以更好地理解以下的详细描述。本领域的技术人员将理解的是,他们可以容易地使用本公开作为基础来设计或者修改其他工艺和结构,以实现与这里引入的实施例相同的目的和/或达到与这里引入的实施例相同的优点。本领域技术人员还应当认识到,这些等同构造并不脱离本公开的精神和范围,并且他们可以在不脱离本公开的精神和范围的情况下进行各种改变、替代和变更。例如,通过针对位线导体和字线导体实现不同的厚度,可以实现导体的不同电阻。但是,也可以使用改变金属导体的电阻的其他技术。
示例1.一种制造半导体器件的方法,包括:在暴露在工件上的源极/漏极开口中的源极/漏极特征的顶表面以及所述源极/漏极开口的侧壁之上共形地沉积电介质层;各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;对所述电介质层进行注入工艺;以及在执行所述注入工艺之后,对所述工件执行预清洁工艺,其中,所述注入工艺包括非零倾斜角度。
示例2.根据示例1所述的方法,其中,所述电介质层包括氮化硅、碳氮化硅、或硅。
示例3.根据示例1所述的方法,其中,所述注入工艺包括使用氙或氩。
示例4.根据示例1所述的方法,其中,所述非零倾斜角度在10°至85°之间。
示例5.根据示例1所述的方法,其中,所述注入工艺导致所述电介质层的氧化,以形成所述电介质层的氧化部分,其中,所述预清洁工艺去除所述电介质层的氧化部分。
示例6.根据示例1所述的方法,其中,所述注入工艺导致对所述电介质层的损伤,以形成所述电介质层的受损部分,其中,所述预清洁工艺去除所述电介质层的受损部分。
示例7.根据示例1所述的方法,还包括:在所述注入工艺之前,对所述工件执行预硅化物注入工艺,其中,所述预硅化物注入工艺用锗来注入暴露的源极/漏极特征。
示例8.根据示例7所述的方法,其中,所述预硅化物注入工艺包括零度倾斜角度。
示例9.一种制造半导体器件的方法,包括:接收工件,所述工件包括:第一栅极结构,第二栅极结构,源极/漏极开口,所述源极/漏极开口位于所述第一栅极结构和所述第二栅极结构之间,以及源极/漏极特征,所述源极/漏极特征在所述源极/漏极开口中暴露;在所述源极/漏极开口的侧壁和所述源极/漏极特征的顶表面之上共形地沉积电介质层;各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;对暴露的源极/漏极特征执行第一注入工艺;在执行所述第一注入工艺之后,对所述电介质层执行第二注入工艺以形成经处理部分;以及在执行所述第二注入工艺之后,对所述工件执行预清洁工艺,其中,所述预清洁工艺以比蚀刻所述电介质层更快的速率来蚀刻所述经处理部分。
示例10.根据示例9所述的方法,其中,所述工件还包括栅极间隔件,所述栅极间隔件沿着所述源极/漏极开口的侧壁设置,其中,共形地沉积所述电介质层将所述电介质层沉积在所述栅极间隔件上。
示例11.根据示例9所述的方法,其中,所述预清洁工艺包括使用氢氟酸、氨、或水。
示例12.根据示例9所述的方法,其中,所述电介质层包括氮化硅、碳氮化硅、或硅。
示例13.根据示例9所述的方法,其中,所述第一注入工艺包括使用锗,其中,所述第二注入工艺包括使用氙或氩。
示例14.根据示例9所述的方法,其中,所述第一注入工艺包括零度倾斜角度,其中,所述第二注入工艺包括非零倾斜角度。
示例15.根据示例9所述的方法,其中,所述第二注入工艺的离子束能量大于所述第一注入工艺的离子束能量。
示例16.根据示例9所述的方法,其中,所述第二注入工艺的注入剂量大于所述第一注入工艺的注入剂量。
示例17.根据示例9所述的方法,其中,所述第二注入工艺包括-100℃至500℃之间的工艺温度。
示例18.一种制造半导体器件的方法,包括:接收包括源极/漏极特征的工件,所述源极/漏极特征在被限定在两个栅极结构之间的源极/漏极开口中暴露;在所述源极/漏极开口的侧壁和所述源极/漏极特征的顶表面之上共形地沉积电介质层;各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;对所述电介质层执行注入工艺,以形成所述电介质层的经处理部分;在执行所述注入工艺之后,对所述工件执行预清洁工艺;在所述源极/漏极特征之上形成硅化物层;以及在所述硅化物层之上形成金属插塞,其中,所述注入工艺注入氙或氩。
示例19.根据示例18所述的方法,其中,在各向异性地蚀刻所述电介质层之后,所述源极/漏极开口包括颈缩轮廓,其中,所述预清洁工艺通过去除所述经处理部分来减小所述颈缩轮廓。
示例20.根据示例18所述的方法,其中,形成所述硅化物层包括:在所述工件之上沉积金属前体;使所述工件退火,以在所述金属前体和所述源极/漏极特征之间引起硅化,从而形成所述硅化物层;以及去除沿着所述源极/漏极开口的侧壁的所述金属前体。
Claims (20)
1.一种制造半导体器件的方法,包括:
在暴露在工件上的源极/漏极开口中的源极/漏极特征的顶表面以及所述源极/漏极开口的侧壁之上共形地沉积电介质层;
各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;
对所述电介质层进行注入工艺;以及
在执行所述注入工艺之后,对所述工件执行预清洁工艺,
其中,所述注入工艺包括非零倾斜角度。
2.根据权利要求1所述的方法,其中,所述电介质层包括氮化硅、碳氮化硅、或硅。
3.根据权利要求1所述的方法,其中,所述注入工艺包括使用氙或氩。
4.根据权利要求1所述的方法,其中,所述非零倾斜角度在10°至85°之间。
5.根据权利要求1所述的方法,
其中,所述注入工艺导致所述电介质层的氧化,以形成所述电介质层的氧化部分,
其中,所述预清洁工艺去除所述电介质层的氧化部分。
6.根据权利要求1所述的方法,
其中,所述注入工艺导致对所述电介质层的损伤,以形成所述电介质层的受损部分,
其中,所述预清洁工艺去除所述电介质层的受损部分。
7.根据权利要求1所述的方法,还包括:
在所述注入工艺之前,对所述工件执行预硅化物注入工艺,
其中,所述预硅化物注入工艺用锗来注入暴露的源极/漏极特征。
8.根据权利要求7所述的方法,其中,所述预硅化物注入工艺包括零度倾斜角度。
9.一种制造半导体器件的方法,包括:
接收工件,所述工件包括:
第一栅极结构,
第二栅极结构,
源极/漏极开口,所述源极/漏极开口位于所述第一栅极结构和所述第二栅极结构之间,以及
源极/漏极特征,所述源极/漏极特征在所述源极/漏极开口中暴露;
在所述源极/漏极开口的侧壁和所述源极/漏极特征的顶表面之上共形地沉积电介质层;
各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;
对暴露的源极/漏极特征执行第一注入工艺;
在执行所述第一注入工艺之后,对所述电介质层执行第二注入工艺以形成经处理部分;以及
在执行所述第二注入工艺之后,对所述工件执行预清洁工艺,
其中,所述预清洁工艺以比蚀刻所述电介质层更快的速率来蚀刻所述经处理部分。
10.根据权利要求9所述的方法,
其中,所述工件还包括栅极间隔件,所述栅极间隔件沿着所述源极/漏极开口的侧壁设置,
其中,共形地沉积所述电介质层将所述电介质层沉积在所述栅极间隔件上。
11.根据权利要求9所述的方法,其中,所述预清洁工艺包括使用氢氟酸、氨、或水。
12.根据权利要求9所述的方法,其中,所述电介质层包括氮化硅、碳氮化硅、或硅。
13.根据权利要求9所述的方法,
其中,所述第一注入工艺包括使用锗,
其中,所述第二注入工艺包括使用氙或氩。
14.根据权利要求9所述的方法,
其中,所述第一注入工艺包括零度倾斜角度,
其中,所述第二注入工艺包括非零倾斜角度。
15.根据权利要求9所述的方法,其中,所述第二注入工艺的离子束能量大于所述第一注入工艺的离子束能量。
16.根据权利要求9所述的方法,其中,所述第二注入工艺的注入剂量大于所述第一注入工艺的注入剂量。
17.根据权利要求9所述的方法,其中,所述第二注入工艺包括-100℃至500℃之间的工艺温度。
18.一种制造半导体器件的方法,包括:
接收包括源极/漏极特征的工件,所述源极/漏极特征在被限定在两个栅极结构之间的源极/漏极开口中暴露;
在所述源极/漏极开口的侧壁和所述源极/漏极特征的顶表面之上共形地沉积电介质层;
各向异性地蚀刻所述电介质层,以暴露所述源极/漏极特征;
对所述电介质层执行注入工艺,以形成所述电介质层的经处理部分;
在执行所述注入工艺之后,对所述工件执行预清洁工艺;
在所述源极/漏极特征之上形成硅化物层;以及
在所述硅化物层之上形成金属插塞,
其中,所述注入工艺注入氙或氩。
19.根据权利要求18所述的方法,
其中,在各向异性地蚀刻所述电介质层之后,所述源极/漏极开口包括颈缩轮廓,
其中,所述预清洁工艺通过去除所述经处理部分来减小所述颈缩轮廓。
20.根据权利要求18所述的方法,其中,形成所述硅化物层包括:
在所述工件之上沉积金属前体;
使所述工件退火,以在所述金属前体和所述源极/漏极特征之间引起硅化,从而形成所述硅化物层;以及
去除沿着所述源极/漏极开口的侧壁的所述金属前体。
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