TW202217919A - 擴大製程窗之方法 - Google Patents
擴大製程窗之方法 Download PDFInfo
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- TW202217919A TW202217919A TW110121215A TW110121215A TW202217919A TW 202217919 A TW202217919 A TW 202217919A TW 110121215 A TW110121215 A TW 110121215A TW 110121215 A TW110121215 A TW 110121215A TW 202217919 A TW202217919 A TW 202217919A
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Abstract
本揭露之一些實施方式提供一種擴大用於形成源極/汲極接觸的製程窗的方法。方法可包括接收工作件,工作件包括源極/汲極特徵,源極/汲極特徵暴露於被定義在二個閘極結構之間的源極/汲極開口中,在源極/汲極開口的側壁與源極/汲極特徵的頂面上共形地沉積介電層。各向異性地蝕刻介電層,以暴露源極/汲極特徵,對介電層執行佈植製程,並且在執行佈植製程之後,對工作件執行前置清洗製程。佈植製程包含非零傾斜角。
Description
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半導體積體電路(IC)行業已經歷指數增長。IC材料與設計方面的技術進步已產生數代IC,其中每一代都比上一代具有更小且更複雜的電路。在IC發展的過程中,功能密度(即每個晶片面積的內連接元件數量)普遍增加,而幾何尺寸(即可以使用製造製程創造的最小組件或線路)已減少。此按照比例減少的製程通常通過提高生產效率與降低相關成本來提供好處。這種比例減少亦增加處理與製造IC的複雜性。
舉例來說,可以在諸如源極/汲極接觸的接觸特徵的側壁上形成介電襯墊以防止洩漏。為了形成介電襯墊,介電材料被共形地沉積在接觸開口上,並且執行回蝕製程以暴露面向頂部的表面。雖然介電材料的沉積是共形的,但可能會發生在開口邊緣周圍的堆積,導致頸輪廓與接觸開口的減少。當在接觸開口中沉積金屬填充層以形成金屬插塞時,邊緣周圍的堆積物可能會阻礙金屬填充層的沉積,導致金屬插塞中出現空隙或其他缺陷。這種空隙或缺陷可能導致接觸電阻增加甚至接觸失效。因此,雖然形成接觸特徵的現有製程通常足以滿足它們的預期目的,但並非在所有方面都是令人滿意的。
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以下揭露提供用於實施本揭露之一些實施方式或實例之不同特徵。下文描述組件及配置之特定實例以簡化本揭露之一些實施方式。當然,此等組件及配置僅為實例且並非意欲為限制性的。例如,在以下描述中第一特徵於第二特徵上方或上的形成可包括第一及第二特徵直接接觸地形成的實施方式,且亦可包括附加特徵可形成在第一特徵與第二特徵之間使得第一特徵及第二特徵可不直接接觸的實施方式。此外,本揭露之一些實施方式在各種實例中可重複參考符號及/或字母。此重複係出於簡單及清楚之目的,且本身並不指明所論述之各種實施方式及/或組態之間的關係。
進一步地,為方便描述可在本揭露之一些實施方式中使用空間上相對之術語,諸如「在……之下(beneath)」、「在……下方(below)」、「下面的(lower)」、「在……上方(above)」、「上面的(upper)」及其類似物來描述如在諸圖中所描述之一個元件或特徵與另外之(諸等)元件或(諸等)特徵的關係。該等空間上相對之術語意欲除諸圖中所描述之方位外,涵蓋處於使用或操作中之元件之不同方位。元件可另外定位(經90度旋轉或在其它方位)且據此解釋本揭露之一些實施方式所用之該等空間上相對之描述詞。再者,當一個數量或一個數量範圍被描述為「約(about)」、「近似(approximately)」及其類似物,此術語應當通常意指在涵蓋所描述數量的一合理範圍,例如在所描述的數字或所屬技術領域之通常知識者理解的其他值的±10%內。例如,術語「約5nm」涵蓋從4.5nm到5.5nm的尺寸範圍。
本揭露之一些實施方式有關於,但非限制於,一種用於形成接觸特徵的擴大製程窗的方法。
在IC製造製程中,正在努力減少接觸特徵的洩漏而不增加接觸電阻。以源極/汲極接觸為例,可以沿著源極/汲極接觸開口的側壁沉積介電襯墊,以改善源極/汲極接觸與相鄰的閘極接觸通孔之間的隔離,以減少洩漏。在示例製程中,用於介電襯墊的介電材料共形地沉積在源極/汲極接觸開口上,然後執行回蝕製程以暴露源極/汲極特徵。即使採用回蝕製程,介電材料也可能在源極/汲極接觸開口的邊緣周圍堆積,從而導致源極/汲極接觸開口具有頸輪廓(necking profile)。亦即,源極/汲極接觸開口的頂部開口窗可以小於源極/汲極接觸開口的其餘部分。當在源極/汲極接觸開口中沉積金屬填充層以形成金屬插塞時,由於對源極/汲極接觸開口的通路受到限制,頂部開口窗的減少可以減少製程窗。當頸輪廓存在時,被沉積的金屬填充層可能在源極/汲極接觸開口實質上被金屬填充層填充之前,過早地合併並關閉頂部開口窗。因此,可能在金屬插塞中形成一個或多個空隙。金屬插塞中的空隙取代導電金屬填充層並且可能增加電阻。
本揭露之一些實施方式提供一種在不增加接觸電阻的情況下減少接觸特徵的洩漏之方法。以形成源極/汲極接觸為例,本揭露之一些實施方式的方法包含採用傾斜角佈植製程,以處理源極/汲極接觸開口的邊緣周圍的介電襯墊的堆積物。佈植製程可包含使用鍺、氙氣、氬氣或矽,並且傾斜角可以在約10度與約85度之間。因這種處理,邊緣周圍的堆積物可能會被損害或氧化,從而使堆積物更容易受到後續前置清洗製程的影響。前置清洗製程蝕刻處理部分比蝕刻介電襯墊的其餘部分更快,可消除或減少邊緣周圍的堆積。使用佈植製程並結合前置清洗製程,本揭露之一些實施方式的方法沉積介電襯墊以用於減少洩漏,而不將缺陷引入源極/汲極接觸。
現在將參考圖式更詳細地描述本揭露之一些實施方式的各個方面。就此而言,第1圖繪示根據本揭露之一或多個方面的形成半導體元件的方法100的流程圖。方法100僅是示例,並不意旨在將本揭露之一些實施方式的內容限制為方法100中所明確說明的內容。可以在方法100之前、期間與之後提供額外的步驟,並且可以替換、消除或移動所描述的一些步驟關於此方法的其他實施方式。為簡化起見,本揭露之一些實施方式並未詳細描述所有的步驟。以下結合第1圖以及第2圖至第10圖來描述方法100,其中第2圖至第10圖是根據方法100的實施方式在不同製造階段的工作件200的局部剖面圖。因為在製造製程結束時,工作件200將被製造成半導體元件200,所以根據上下文的需要可將工作件200視為半導體元件200。
如第2圖至第10圖所示,將使用鰭式場效電晶體(FinFET)作為示例來詳細描述方法100的操作與優點。然而,本揭露之一些實施方式並不限於此,並且可以應用於多橋通道(multi-bridge-channel;MBC)電晶體。FinFET與MBC電晶體是多閘極元件的示例,它們已被引入以通過增加閘極-通道耦合、降低斷態(off-state)電流與減少短通道效應(SCE)來改善閘極控制。FinFET具有在不止一側被閘極結構環繞的升高的通道(例如,閘極結構環繞從基板延伸的半導體材料「鰭」的頂部與側壁)。MBC電晶體具有可部分或完全圍繞通道區域延伸的閘極結構,以在兩側或更多側提供對通道區域的訪問。由於MBC電晶體的閘極結構圍繞通道區域,因此MBC電晶體也可視為圍繞閘極電晶體(surrounding gate transistor;SGT)或環繞式閘極(gate-all-around;GAA)電晶體。MBC電晶體的通道區域可包含奈米線、奈米片、其他奈米結構及/或其他合適的結構。通道區域的形狀也賦予MBC電晶體替代名稱,例如奈米片電晶體或奈米線電晶體。此外,本揭露之一些實施方式的製程實施方式可應用於半導體元件特徵的形成,其中填充材料被沉積於沿著襯墊的開口中以及半導體元件特徵中的空隙是不期望的。
參閱第1圖與第2圖。方法100包括步驟102,其中在工作件200上沉積襯墊222。如第2圖所示,工作件200包含基板202以及從基板202上升的鰭結構204。鰭結構204沿著方向X的長度方向延伸,並且區分為源極/汲極區域204SD與通道區域204C。一個源極/汲極區域204SD與二個通道區域204C繪示於第2圖。閘極結構210設置在每個通道區域204C之上。源極/汲極特徵220設置於每個源極/汲極區域204SD之上。每個閘極結構210包含閘極介電層206與閘極電極層208。第一閘極間隔層212與第二閘極間隔層214沿著每個閘極結構210的側壁成長(形成)。閘極自對準接觸(self-aligned contact;SAC)介電層216設置在每個閘極結構210之上。
基板202可以是矽基板。替代地或附加地,基板202可包含其他元素半導體材料,例如鍺。在一些實施方式中,基板202由化合物半導體製成,例如碳化矽、砷化鎵、砷化銦或磷化銦。在一些實施方式中,基板202由合金半導體製成,例如矽鍺、碳化矽鍺、磷化砷鎵或磷化鎵銦。在一些實施方式中,基板202包含一或多個磊晶層。例如,基板202可包含覆蓋於體半導體(bulk semiconductor)上的磊晶層。在一些實施方式中,基板202可包含掩埋絕緣體層,例如掩埋氧化矽層,並且可以是絕緣體上矽(SOI)基板。
鰭結構204從基板202沿著方向Z垂直延伸。鰭結構204在方向X上伸長。鰭結構204可以由基板202形成並且可以與基板202共享相同的材料。或者,鰭結構204可以不僅由基板202形成,而且還可以由形成在基板202上的磊晶層形成。在這些替代的實施方式中,鰭結構204可包含鍺(Ge)或其他半導體材料。鰭結構204可通過使用合適的製程形成,例如使用微影與蝕刻製程。在一些實施方式中,使用乾式蝕刻或電漿製程,從基板202蝕刻鰭結構204。在一些其他的實施方式中,鰭結構204可以通過雙圖案化微影(double-patterning lithography;DPL)製程或多圖案化微影(multiple-patterning lithography;MPL)製程形成。雙圖案化微影是一種通過將圖案分成二個交錯的圖案,在基板上構建圖案的方法。雙圖案化微影允許增強特徵(例如,鰭)密度。形成隔離結構(未繪示),例如淺溝槽隔離(STI)結構,以圍繞鰭結構204。在一些實施方式中,鰭結構204的下部被隔離結構圍繞,且鰭結構204的上部從隔離結構凸出。換句話說,鰭結構204的一部分嵌入隔離結構中。隔離結構可防止電性干擾(interference)或串擾(crosstalk)。
儘管未明確繪示,閘極介電層206包含設置在鰭結構204的通道區域204C上的界面層以及設置在界面層上的高介電常數(high-k)介電層。在此,高介電常數介電層是指介電常數大於二氧化矽的介電常數之介電材料,二氧化矽的介電常數約為3.9。在一些實施方式中,界面層包含氧化矽和鉿酸矽(silicon hafnate),並且可以在清洗製程中形成。清洗製程(cleaning process)之示例可包含使用RCA SC-1(氫氧化銨、過氧化氫與水的混合物)及/或RCA SC-2(鹽酸、過氧化氫與水的混合物)。然後使用原子層沉積(ALD)、化學氣相沉積(CVD)及/或其他合適的方法將高介電常數介電層沉積於界面層上。高介電常數介電層可包含氧化鉿。或者,高介電常數介電層可包含其他高介電常數介電質,例如氧化鈦(TiO
2)、氧化鉿鋯(HfZrO)、氧化鉭(Ta
2O
5)、氧化鉿矽(HfSiO
4)、氧化鋯(ZrO
2)、氧化鋯矽(ZrSiO
2)、氧化鑭(La
2O
3)、氧化鋁(Al
2O
3)、氧化鋯(ZrO)、氧化釔(Y
2O
3)、SrTiO
3(STO)、BaTiO
3(BTO)、BaZrO、鉿鑭氧化物(HfLaO)、鑭矽氧化物(LaSiO)、鋁矽氧化物(AlSiO)、鉿鉭氧化物(HfTaO)、鉿鈦氧化物(HfTiO)、(Ba,Sr)TiO
3(BST)、氮化矽(SiN)、氮氧化矽(SiON)、前述的組合,或其他合適的材料。
然後,使用原子層沉積(ALD)、物理氣相沉積(PVD)、化學氣相沉積(CVD)、電子束蒸發或其他合適的方法將閘極電極層208沉積於閘極介電層206上。閘極電極層208可包含單層或可選的多層結構,例如具有選定功函數以提高元件性能的金屬層(功函數金屬層)、襯墊層、潤濕層、黏著層、金屬合金或金屬矽化物之各種組合。舉例來說,閘極電極層208可包含氮化鈦(TiN)、鈦鋁(TiAl)、氮化鋁鈦(TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl),氮化鉭鋁(TaAlN)、碳化鉭鋁(TaAlC)、碳氮化鉭(TaCN)、鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、碳化鉭(TaC)、氮化鉭矽(TaSiN)、銅(Cu)、其他耐火金屬(refractory metals)或其他合適的金屬材料或其組合。此外,在半導體元件200包含n型電晶體與p型電晶體的情況下,對於n型電晶體與p型電晶體可以分別形成不同的閘極電極層,其可包含不同的功函數金屬層(例如,用於提供不同的n型功函數金屬層與p型功函數金屬層)。
工作件200可包含沿著閘極結構210的側壁設置的一或多個閘極間隔層。在第2圖所示的實施方式中,工作件200包含二個閘極間隔層(第一閘極間隔層212以及位於第一閘極間隔層212上的第二閘極間隔層214)。當採用閘極後(gate-last)製程(或閘極置換製程)時,首先形成多晶矽虛設閘極堆疊於通道區域204C上,以及閘極間隔層沉積於虛設閘極堆疊的側壁上。在隨後的製程中,虛設閘極堆疊被移除,並且被閘極結構210置換,同時至少一部分的閘極間隔層保持沿著閘極結構210的側壁設置。在一些實施方式中,第一閘極間隔層212與第二閘極間隔層212使用化學氣相沉積(CVD)、低於大氣壓力(subatmospheric)化學氣相沉積(SACVD)或原子層沉積(ALD)共形地沉積第一閘極間隔層212與第二閘極間隔層214。第一閘極間隔層212與第二閘極間隔層214可以由不同的介電材料形成,並選自氧化矽、氮化矽、碳化矽、氮氧化矽(silicon oxynitride)、碳氮化矽(silicon carbonitride)、碳氧化矽(silicon oxycarbide)、氧碳氮化矽(silicon oxycarbonitride)及/或其組合。在一個實施方式中,第一閘極間隔層212包含碳氮化矽,並且第二閘極間隔層214包括氮化矽。
閘極自對準接觸介電層216可包含氮化矽、氧氮化矽、氧碳氮化矽或碳氮化矽。閘極自對準接觸介電層216的組成可以與第二閘極間隔層214的組成相同。在第2圖所示的一些實施方式中,在形成閘極自對準接觸介電層216之後,沉積第二閘極間隔層214。在這些實施方式中,閘極自對準接觸介電層216設置於閘極結構210與第一閘極間隔層212的頂面上。第二閘極間隔層214連續地沿著第一閘極間隔層212的側壁與閘極自對準接觸介電層216的側壁延伸。
根據半導體元件200的導電類型,源極/汲極特徵220可以是n型或p型。當源極/汲極特徵220是n型時,源極/汲極特徵220可包含摻磷矽(phosphorus-doped silicon;Si:P)、摻砷矽(arsenic-doped silicon;Si:As)或摻銻矽(antimony-doped silicon;Si:Sb)。當源極/汲極特徵220是p型時,源極/汲極特徵220可包含摻硼矽鍺(boron-doped silicon germanium;SiGe:B)或摻鎵矽鍺(gallium-doped silicon;SiGe:Ga)。源極/汲極特徵220可使用氣相磊晶(vapor phase epitaxy;VPE)、分子束磊晶(molecular beam epitaxy;MBE)或合適的磊晶沉積製程形成。源極/汲極特徵220可以在沉積製程期間原位(in-situ)摻雜或使用佈植製程異位(ex-situ)摻雜。
在步驟102,襯墊222共形地沉積於工作件200上。在一些實施方式中,襯墊222可包含介電材料。襯墊222的示例介電材料包含氮化矽、碳氮化矽或矽。這些示例介電材料是密的並且提供令人滿意的防漏電。在一些實施方式中,可以使用化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、低壓化學氣相沉積(low-pressure CVD;LPCVD)或低於大氣壓力化學氣相沉積(SACVD)來沉積襯墊222。由於襯墊222由介電材料形成,因此它也可視為介電襯墊222。如第2圖所示,襯墊222設置於閘極自對準接觸介電層216上、第二閘極間隔層214的頂面上、第二閘極間隔層214的側壁上以及源極/汲極特徵220的頂面上。第二閘極間隔層214的側壁與源極/汲極特徵220的頂面共同定義源極/汲極特徵220上的源極/汲極接觸開口218。換句話說,襯墊222共形地沉積於源極/汲極接觸開口218的表面上。在第2圖所示的一些實施方式中,襯墊222的介電材料可堆積於源極/汲極接觸開口218的頂部開口窗的邊緣周圍,以形成邊緣堆積物224。邊緣堆積物224可導致在第2圖中所示的頸輪廓(necking profile)。關於要沉積到源極/汲極接觸開口中的材料,這種頸輪廓可能限制接近或進入源極/汲極接觸開口218。如上所述,當金屬填充層隨後沉積於源極/汲極接觸開口218中時,第2圖代表性地示出的邊緣堆積物224可能導致空隙。
參閱第1圖與第3圖,方法100包含步驟104,其中襯墊222被凹陷。在一些實施方式中,工作件200在步驟104經受各向異性(anisotropic)蝕刻製程,以移除設置於源極/汲極特徵220上的襯墊222。如第3圖所示,在步驟104的操作結束時,至少一部分的源極/汲極特徵220暴露於源極/汲極接觸開口218中,並且減少閘極自對準接觸介電層216上的襯墊222的部分的厚度。在一些實施方式中,各向異性蝕刻製程可包含反應性離子蝕刻(reactive ion etching;RIE)製程,其使用氫氣、含氟氣體(例如,CF
4、SF
6、CH
2F
2、CHF
3及/或C
2F
6)、含氯氣體(例如Cl
2、CHCl
3、CCl
4及/或BCl
3)、含溴氣體(例如HBr及/或CHBR
3)、含碘氣體、其他合適的氣體及/或電漿,及/或其組合。在步驟104所述的凹陷之後,襯墊222可具有介於約0.5奈米(nm)與約5nm之間的厚度。在一些實施方式中,步驟104的各向異性蝕刻製程並未完全移除邊緣堆積物224,並且並未實質上減少沿著源極/汲極接觸開口218的側壁之襯墊222的厚度。參閱第3圖,源極/汲極接觸開口218包含沿著方向X的底部開口寬度W1與頂部開口寬度W2。在一些實施方式中,當頂部開口寬度W2介於約10nm與約15nm之間時,頂部開口寬度W2比底部開口寬度W1小約1nm與約5nm之間的頸偏差(necking bias)。
參閱第1圖與第4圖,方法100包含步驟106,其中執行第一佈植製程300。執行第一佈植製程300更多地是為了p型元件的利益而不是為了n型元件的利益。在一些情況下,p型源極/汲極特徵220可能由於鍺聚集(aggregation)而具有不均勻的鍺分佈(distribution),這可能導致在上面形成不令人滿意的矽化物。在一些實施方式中,第一佈植製程300佈植鍺(Ge),以在p型源極/汲極特徵220的暴露表面上提供均勻的鍺分佈。因為第一佈植製程300針對位於源極/汲極接觸開口218下方的源極/汲極特徵220,第一佈植製程300包含相對於方向Z的零度(0°)傾斜角,其中方向Z是垂直於基板202的頂面的方向。為了防止源極/汲極特徵220損害,第一佈植製程300包含介於約1keV與約10keV之間的適度的離子束能量,以及介於約5×10
13離子/平方公分(ions/cm
2)與約2×10
14離子/平方公分之間的佈植劑量。在一些實施方式中,第一佈植製程300在介於約-100°C與約300°C之間的溫度下執行。第一佈植製程300可視為前置矽化物(pre-silicide)佈植製程。
參閱第1圖、第5圖與第6圖,方法100包含步驟108,其中執行第二佈植製程400。與前述針對源極/汲極特徵220的第一佈植製程300不同,第二佈植製程400遠離源極/汲極特徵220並且針對邊緣堆積物224。根據本揭露之一些實施方式,第二佈植製程400配置以對邊緣堆積物224造成損害,以使邊緣堆積物224更容易受到隨後的前置清洗製程500(將在下面描述)的影響。因此,第二佈植製程400包含非零角(non-zero)的傾斜角θ。在一些實施方式中,相對於方向Z,第二佈植製程400的傾斜角θ可介於約10度與約85度之間。因為第二佈植製程400不意旨於使源極/汲極特徵220中的鍺分佈均勻,所以第二佈植製程400可包含除鍺(Ge)之外的離子種類。在一些實施方式中,第二佈植製程400包含的離子種類如鍺(Ge)、矽(Si)、氙氣(Xe)或氬氣(Ar)。在一實施方式中,第二佈植製程400包含使用氙氣(Xe)或氬氣(Ar)。由於第二佈植製程400的作用是對邊緣堆積物224造成損害,因此第二佈植製程400的離子束能量與劑量可以大於第一佈植製程300的離子束能量與劑量。在一些實施方式中,第二佈植製程400可包含介於約1 keV與約50 keV之間的離子束能量,以及介於約5x10
13離子/平方公分與約1x10
16離子/平方公分之間的劑量。第二佈植製程400在介於約-100°C與約500°C之間的溫度下執行。在前述佈植條件下,第二佈植製程400可對襯墊222造成局部損害,並將離子束視線內的襯墊222的一部分轉化為處理部分(treated portion)2220。離子束視線外的襯墊222可能不會被實質損害或氧化。在第6圖繪示的一些實施方式中,處理部分2220可包含在閘極自對準接觸介電層216上並且鄰近邊緣部分224的堆積物(或邊緣堆積物224)周圍之襯墊222的部分。當第二佈植製程400的真空被破壞且工作件200暴露於含氧環境時,由於第二佈植製程400造成的損害,處理部分2220可被氧化。處理部分2220可包含氮氧化矽、氧碳氮化矽或氧化矽。因此,處理部分2220可視為襯墊222的損害部分(damaged portion)或氧化部分(若被氧化)。可觀察到,當在第二佈植製程400中使用氙氣(Xe)或氬氣(Ar)時,在處理部分2220中可以偵測到氙氣(Xe)或氬氣(Ar)的蹤跡(trace)。
第二佈植製程400的傾斜角θ與離子束能量可以被調整,以實現處理部分2220的不同形狀或深度。舉例來說,當傾斜角θ介於約10度與約30度之間時,第二佈植製程400的視線可以進一步向下到達源極/汲極接觸開口218。因此,處理部分2220可以進一步向下延伸到源極/汲極接觸開口218。當傾斜角θ介於約30度與約60度之間時,第二佈植製程400的視線可以正面影響邊緣部分224並且適度向下到達源極/汲極接觸開口218。當傾斜角θ在約60度與約85度之間時,第二佈植製程400的視線不太可能向下到達源極/汲極接觸開口218,並且處理部分2220很少向下延伸到源極/汲極接觸開口218。傾斜角θ的大小可能是平衡因素的結果,例如接觸開口尺寸、寄生電容以及對源極/汲極特徵220的損害。一般而言,較小的傾斜角θ可能導致源極/汲極特徵220的擴大、寄生電容(閘極結構210與待形成的源極/汲極接觸之間)的增加,以及對源極/汲極特徵220的損害。較大的傾斜角θ可能不會將源極/汲極接觸開口擴大那麼多,但不太可能增加寄生電容或是對源極/汲極特徵220造成損害。在一些實施方式中,當第二佈植製程400包含足夠的離子束能量時,離子種類可能會穿透到第二閘極間隔層214中,並且在靠近邊緣堆積物224的第二閘極間隔層214的一部分中造成局部損害。在這些實施方式中,第二佈植製程400也可以使一部分的第二閘極間隔層214容易受到前置清洗(pre-clean)製程500(將在下面描述)的影響。
參閱第1圖與第7圖,方法100包含步驟110,其中執行前置清洗製程500。在一些實施方式中,前置清洗製程500可包含使用氫氟酸(hydrofluoric acid)、氨(ammonia)及水。可觀察到,步驟110的前置清洗製程500移除處理部分2220比移除襯墊222更快。因此,如第7圖所示,步驟110的前置清洗製程500可減少邊緣堆積物的厚度或凸出(bulging),以在源極/汲極接觸開口218的頂部開口窗形成漏斗輪廓(funnel profile)2240。漏斗輪廓2240提供對源極/汲極接觸開口218的不受阻礙的通路。參閱第7圖,前置清洗製程500減少處理部分2220的厚度,而沿著源極/汲極接觸開口218的側壁的襯墊222的厚度保持實質上不變。儘管未明確繪示,在鄰近邊緣堆積物224的第二閘極間隔層214的一部分也被第二佈植製程400處理與損害之實施方式中,前置清洗製程500也可以移除第二閘極間隔層214的處理部分。在一些實施方式中,暴露的第二閘極間隔層214可定義漏斗輪廓2240的側壁的一部分。
參閱第1圖與第8圖,方法100包含步驟112,其中形成矽化物層226於源極/汲極特徵220上。在一些實施方式中,為了降低接觸電阻,矽化物層226可形成於暴露的源極/汲極特徵220上,藉由沉積金屬層(或金屬前驅物層)於源極/汲極接觸開口218上,並且執行退火製程以在金屬層與源極/汲極特徵220之間產生矽化。用於形成矽化物層226的合適金屬層可包含鈦(Ti)、鉭(Ta)、鎳(Ni)、鈷(Co),或鎢(W)。矽化物層226可包含矽化鈦(TiSi)、氮化矽鈦(TiSiN)、矽化鉭(TaSi)、矽化鎢(WSi)、矽化鈷(CoSi)或矽化鎳(NiSi)。在一些實施方式中,未轉化為矽化物層226的金屬層在退火製程之後被移除。在一些替代的實施方式中,未反應的金屬層保持在原位以作為導電襯墊。
參閱第1圖與第9圖,方法100包含步驟114,其中沉積金屬填充層228於工作件200上。在形成矽化物層226之後,金屬填充層228可沉積到源極/汲極接觸開口218中。金屬填充層228可包含氮化鈦(TiN)、鈦(Ti)、釕(Ru)、鎳(Ni)、鈷(Co)、銅(Cu)、鉬(Mo)、鎢(W)、鉭(Ta),或氮化鉭(TaN)。如第9圖所示,由於第二佈植製程400與前置清洗製程500的結合所產生的漏斗輪廓2240,用於沉積金屬填充層228到源極/汲極接觸開口218中的製程窗實質擴大並且實質減少空隙形成的可能性。
參閱第1圖與第10圖,方法100包含步驟116,其中工作件200被平坦化。如第10圖所示,在沉積金屬填充層228之後,工作件200可以經受平坦化製程,例如化學機械研磨(CMP)製程,以移除多餘的材料並且提供平坦的頂面。在步驟116的操作結束時,形成源極/汲極接觸230。當沿著方向Y觀之時,源極/汲極接觸230包含設置在襯墊222的二個側壁部分之間的底部分230B以及設置在處理部分2220的二個側壁部分之間的頂部分230T。頂部分230T設置在底部分230B上。相較於襯墊222,處理部分2220進一步包含氧氣、氙氣(Xe)的蹤跡或氬氣(Ar)的蹤跡。此外,由於第二佈植製程400,處理部分2220可包含比襯墊222更多的缺陷。如第10圖所示,因為源極/汲極接觸230形成在具有漏斗輪廓2240的源極/汲極接觸開口218中,源極/汲極接觸230也共享漏斗輪廓2240。源極/汲極接觸230可視為金屬插塞(metal plug)。
基於以上之討論,可以看出本揭露的一些實施方式提供優點。應理解到,然其他的實施方式可以提供額外的優點,並且在本揭露的一些實施方式中不必揭露所有的優點,並且無特定的優點是需要對應於所有的實施方式。舉例來說,一個優點是本揭露之一些實施方式所揭露的製程是當介電材料被共形沉積以形成襯墊時,利用傾斜佈植製程來處理介電材料在接觸開口的邊緣周圍的堆積物。傾斜佈植製程可以將襯墊的一部分轉化為被傾斜佈植製程損害的處理部分。處理部分特別容易受到在形成矽化物層之前執行的前置清洗製程的影響。前置清洗製程可移除或減少邊緣周圍的介電材料的堆積物,從而擴大接觸開口的頂部開口。頂部開口可具有漏斗形狀。當沉積金屬填充層到接觸開口中以形成接觸特徵時,擴大的頂部開口允許更大的製程窗。
本揭露之一實施方式涉及一種方法。方法包括共形地沉積介電層於源極/汲極特徵的頂面上,源極/汲極特徵暴露於工作件上的源極/汲極開口中以及源極/汲極開口的側壁中。各向異性地蝕刻介電層,以暴露源極/汲極特徵。對介電層執行佈植製程。在執行佈植製程之後,對工作件執行前置清洗製程。佈植製程包括非零傾斜角。
在一些實施方式中,介電層包括氮化矽、碳氮化矽或矽。在一些實施方式中,佈植製程包括使用氙氣或氬氣。在一些實施方式中,非零傾斜角介於約10度與約85度之間。在一些實施方式中,佈植製程導致介電層的氧化,以形成介電層的氧化部分,以及前置清洗製程移除介電層的氧化部分。在一些實施方式中,佈植製程對介電層導致損害,以形成介電層的損害部分,以及前置清洗製程移除介電層的損害部分。在一些實施方式中,方法更包括在佈植製程之前,對工作件執行前置矽化物佈植製程。前置矽化物佈植製程用鍺佈植暴露的源極/汲極特徵。在一些實施方式中,前置矽化物佈植製程包括零度傾斜角。
本揭露之另一實施方式涉及一種方法。方法包括接收工作件,工作件包括第一閘極結構、第二閘極結構、位於第一閘極結構與第二閘極結構之間的源極/汲極開口以及暴露於源極/汲極開口中的源極/汲極特徵。共形地沉積介電層於源極/汲極開口的側壁及源極/汲極特徵的頂面上。各向異性地蝕刻介電層,以暴露源極/汲極特徵。對暴露的源極/汲極特徵執行第一佈植製程。在執行第一佈植製程之後,對介電層執行第二佈植製程,以形成處理部分。在執行第二佈植製程之後,對工作件執行前置清洗製程。前置清洗製程蝕刻處理部分比蝕刻介電層快。
在一些實施方式中,工作件更包括閘極間隔,閘極間隔沿著源極/汲極開口的側壁設置,以及共形地沉積介電層係在閘極間隔上沉積介電層。在一些實施方式中,前置清洗製程包括使用氫氟酸、氨或水。在一些實施方式中,介電層包括氮化矽、碳氮化矽或矽。在一些實施方式中,第一佈植製程包括使用鍺,以及第二佈植製程包括使用氙氣或氬氣。在一些實施方式中,第一佈植製程包括零度傾斜角,以及第二佈植製程包括非零傾斜角。在一些實施方式中,第二佈植製程的離子束能量大於第一佈植製程的離子束能量。在一些實施方式中,第二佈植製程的佈植劑量大於第一佈植製程的佈植劑量。在一些實施方式中,第二佈植製程包括介於約-100°C至500°C之間的一製程溫度。
本揭露之另一實施方式涉及一種方法。方法包括接收工作件,工作件包括源極/汲極特徵,源極/汲極特徵暴露於被定義在二個閘極結構之間的源極/汲極開口中。共形地沉積介電層於源極/汲極開口的側壁及源極/汲極特徵的頂面上。各向異性地蝕刻介電層,以暴露源極/汲極特徵。對介電層執行佈植製程,以形成介電層的處理部分。在執行佈植製程之後,對工作件執行前置清洗製程。形成矽化物層於源極/汲極特徵上。形成金屬插塞於矽化物層上。佈植製程佈植氙氣或氬氣。
在一些實施方式中,各向異性地蝕刻介電層之後,源極/汲極開口包含頸輪廓,以及前置清洗製程藉由移除處理部分減少頸輪廓。在一些實施方式中,形成矽化物層包括沉積金屬前驅物於工作件上。退火工作件,使得金屬前驅物與源極/汲極特徵之間產生矽化,以形成矽化物層。沿著源極/汲極開口的側壁移除金屬前驅物。
前述內容概述若干實施方式之特徵,使得熟習此項技術者可更佳地理解本揭露之一些實施方式之態樣。熟習此項技術者應瞭解,其可易於使用本揭露之一些實施方式作為用於設計或修改用於實施本揭露之一些實施方式中引入之實施方式之相同目的及/或達成相同優勢之其他製程及結構的基礎。熟習此項技術者亦應認識到,此類等效構造並不偏離本揭露之一些實施方式之精神及範疇,且此類等效構造可在本揭露之一些實施方式中進行各種改變、取代及替代而不偏離本揭露之一些實施方式的精神及範疇。
100:方法
102:步驟
104:步驟
106:步驟
108:步驟
110:步驟
112:步驟
114:步驟
116:步驟
200:工作件(半導體元件)
202:基板
204:鰭結構
204SD:源極/汲極區域
204C:通道區域
206:閘極介電層
208:閘極電極層
210:閘極結構
212:閘極間隔層
214:閘極間隔層
216:介電層
218:源極/汲極接觸開口
220:源極/汲極特徵
2220:處理部分
222:襯墊
224:邊緣堆積物(邊緣部分)
2240:漏斗輪廓
226:矽化物層
228:金屬填充層
230:源極/汲極接觸
230B:底部分
230T:頂部分
300:第一佈植製程
400:第二佈植製程
500:前置清洗製程
W1:寬度
W2:寬度
θ:角
X:方向
Y:方向
Z:方向
本揭露之一些實施方式的態樣在與隨附圖式一起研讀時自以下詳細描述內容來最佳地理解。應注意,根據行業中之標準慣例,各種特徵未按比例繪製。實際上,各種特徵的尺寸可為了論述清楚經任意地增大或減少。
第1圖繪示根據本揭露之一或多個方面的製造半導體元件的方法之流程圖。
第2圖至第10圖繪示根據本揭露之一或多個方面之在第1圖的方法中不同製造階段的工作件的局部剖面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記)
無
國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記)
無
100:方法
102:步驟
104:步驟
106:步驟
108:步驟
110:步驟
112:步驟
114:步驟
116:步驟
Claims (20)
- 一種方法,包含: 共形地沉積一介電層,於一源極/汲極特徵的一頂面上,該源極/汲極特徵暴露於一工作件上的一源極/汲極開口中及該源極/汲極開口的側壁中; 各向異性地蝕刻該介電層,以暴露該源極/汲極特徵; 對該介電層執行一佈植製程;以及 在執行該佈植製程之後,對該工作件執行一前置清洗製程,其中該佈植製程包含一非零傾斜角。
- 如請求項1所述之方法,其中該介電層包含氮化矽、碳氮化矽或矽。
- 如請求項1所述之方法,其中該佈植製程包含使用氙氣或氬氣。
- 如請求項1所述之方法,其中該非零傾斜角介於約10度與約85度之間。
- 如請求項1所述之方法,其中該佈植製程導致該介電層的氧化,以形成該介電層的一氧化部分,其中該前置清洗製程移除該介電層的該氧化部分。
- 如請求項1所述之方法,其中該佈植製程對該介電層導致損害,以形成該介電層的一損害部分,其中該前置清洗製程移除該介電層的該損害部分。
- 如請求項1所述之方法,更包含: 在該佈植製程之前,對該工作件執行一前置矽化物佈植製程,其中該前置矽化物佈植製程用鍺佈植暴露的該源極/汲極特徵。
- 如請求項7所述之方法,其中該前置矽化物佈植製程包含一零度傾斜角。
- 一種方法,包含: 接收一工作件,包含: 一第一閘極結構; 一第二閘極結構; 一源極/汲極開口,位於該第一閘極結構與該第二閘極結構之間;以及 一源極/汲極特徵,暴露於該源極/汲極開口中; 共形地沉積一介電層,於該源極/汲極開口的側壁及該源極/汲極特徵的一頂面上; 各向異性地蝕刻該介電層,以暴露該源極/汲極特徵; 對暴露的該源極/汲極特徵執行一第一佈植製程; 在執行該第一佈植製程之後,對該介電層執行一第二佈植製程,以形成一處理部分;以及 在執行該第二佈植製程之後,對該工作件執行一前置清洗製程,其中該前置清洗製程蝕刻該處理部分比蝕刻該介電層快。
- 如請求項9所述之方法,其中該工作件更包含一閘極間隔,該閘極間隔沿著該源極/汲極開口的該些側壁設置,其中共形地沉積該介電層係在該閘極間隔上沉積該介電層。
- 如請求項9所述之方法,其中該前置清洗製程包含使用氫氟酸、氨或水。
- 如請求項9所述之方法,其中該介電層包含氮化矽、碳氮化矽或矽。
- 如請求項9所述之方法,其中該第一佈植製程包含使用鍺,其中該第二佈植製程包含使用氙氣或氬氣。
- 如請求項9所述之方法,其中該第一佈植製程包含一零度傾斜角,其中該第二佈植製程包含一非零傾斜角。
- 如請求項9所述之方法,其中該第二佈植製程的一離子束能量大於該第一佈植製程的一離子束能量。
- 如請求項9所述之方法,其中該第二佈植製程的一佈植劑量大於該第一佈植製程的一佈植劑量。
- 如請求項9所述之方法,其中該第二佈植製程包含介於約-100°C至500°C之間的一製程溫度。
- 一種方法,包含: 接收一工作件,包含一源極/汲極特徵,該源極/汲極特徵暴露於被定義在二個閘極結構之間的一源極/汲極開口中; 共形地沉積一介電層,於該源極/汲極開口的側壁及該源極/汲極特徵的一頂面上; 各向異性地蝕刻該介電層,以暴露該源極/汲極特徵; 對該介電層執行一佈植製程,以形成該介電層的一處理部分; 在執行該佈植製程之後,對該工作件執行一前置清洗製程; 形成一矽化物層,於該源極/汲極特徵上;以及 形成一金屬插塞,於該矽化物層上,其中該佈植製程佈植氙氣或氬氣。
- 如請求項18所述之方法,其中各向異性地蝕刻該介電層之後,該源極/汲極開口包含一頸輪廓,其中該前置清洗製程藉由移除該處理部分減少該頸輪廓。
- 如請求項18所述之方法,其中形成該矽化物層包含: 沉積一金屬前驅物,於該工作件上; 退火該工作件,使得該金屬前驅物與該源極/汲極特徵之間產生矽化,以形成矽化物層;以及 沿著該源極/汲極開口的該些側壁移除該金屬前驅物。
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