CN110060955B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN110060955B
CN110060955B CN201810048650.1A CN201810048650A CN110060955B CN 110060955 B CN110060955 B CN 110060955B CN 201810048650 A CN201810048650 A CN 201810048650A CN 110060955 B CN110060955 B CN 110060955B
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layer
metal
forming
dielectric layer
semiconductor device
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CN110060955A (zh
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许闵翔
柯元富
张志圣
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/893,711 priority patent/US10204826B1/en
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Abstract

本发明公开一种半导体元件及其制作方法，其中制作半导体元件的方法包括，其主要先形成一金属间介电层于一基底上，形成一开口于金属间介电层内，进行一处理制作工艺将部分金属间介电层转换为一受损层于开口旁，形成一保护层于该受损层侧壁，形成一导电层于开口内，之后再去除受损层以形成一气孔于保护层旁。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种去除镶嵌于介电层中的一受损层(damaged layer)的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
一般而言，半导体制作工艺在进入10纳米世代后接触插塞的接触面积会大幅降低，造成阻值的增加。除此之外，在制作接触插塞的过程中，特别是利用蚀刻形成接触洞时容易损伤周边的介电层而形成受损区域并影响元件的运作。因此如何在现今场效晶体管的架构下改良此问题即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法，其主要先形成一金属间介电层于一基底上，形成一开口于金属间介电层内，进行一处理制作工艺将部分金属间介电层转换为一受损层于开口旁，形成一保护层于该受损层侧壁，形成一导电层于开口内，之后再去除受损层以形成一气孔于保护层旁。
本发明另一实施利公开一种半导体元件，其主要包含：一金属间介电层设于一基底上，一金属内连线设于金属间介电层内，一气孔设于金属内连线以及金属间介电层之间以及一保护层设于气孔以及金属内连线之间，其中金属内连线下表面低于气孔下表面。
附图说明
图1至图8为本发明一实施例制作半导体元件的方法示意图；
图9为本发明一实施例的半导体元件的结构示意图。
主要元件符号说明
12 基底 14 介电层
16 图案化导电层 18 停止层
20 缓冲层 22 金属间介电层
24 硬掩模 26 开口
28 处理制作工艺 30 受损层
32 保护层 34 金属内连线
36 金属层 38 气孔
40 紫外光固化制作工艺 42 高压缩蚀刻停止层
具体实施方式
请参照图1至图8，图1至图8为本发明一实施例制作半导体元件的方法示意图。如图1所示，首先提供一基底12，基底12上可包含例如金属氧化物半导体(metal-oxidesemiconductor,MOS)晶体管等主动元件(有源元件)以及/或其他被动元件(无源元件)。更具体而言，基底12上可包含平面型或非平面型(如鳍状结构晶体管)等MOS晶体管元件、层间介电层(interlayer dielectric,ILD)覆盖MOS晶体管元件以及接触插塞设于层间介电层内并电连接MOS晶体管元件，其中MOS晶体管可包含金属栅极、源极/漏极区域、间隙壁、外延层、接触洞蚀刻停止层等晶体管元件。由于平面型或非平面型晶体管元件等相关制作工艺均为本领域所熟知技术，在此不另加赘述。
然后形成一介电层14于层间介电层(图未示)上，并于介电层14中形成多个图案化导电层16或导线电连接层间介电层内的接触插塞，其中图案化导电层16上表面较佳切齐介电层14上表面。在本实施例中，各图案化导电层16或导线较佳为一沟槽导体(trenchconductor)或接触洞导体(viaconductor)，其可更细部包含一阻障层与一金属层，其中阻障层可选自由钛(Ti)、氮化钛(TiN)、钽(Ta)以及氮化钽(TaN)所构成的群组，而金属层可选自由钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等所构成的群组，但不局限于此。
接着形成一介电堆叠结构于基底12上，例如可依序形成一停止层18、一缓冲层20、一金属间介电层22以及一硬掩模24于介电层14上，其中停止层18较佳为一蚀刻停止层(etch stop layer,ESL)，其可包含氮掺杂碳化物层(nitrogen doped carbide,NDC)或氮碳化硅(silicon carbon nitride,SiCN)，缓冲层20较佳包含四乙氧基硅烷(Tetraethylorthosilicate,TEOS)，硬掩模24则较佳由氧化硅所构成，但不局限于此。另外金属间介电层22较佳由低介电常数介电材料所构成，其可选自由含碳介电材料、含氮介电材料、含氢介电材料以及多孔介电结构所构成的群组，例如含碳二氧化硅、含氟二氧化硅、多孔二氧化硅或多孔含碳二氧化硅。
接着进行一光刻及蚀刻制作工艺，例如先形成一图案化光致抗蚀剂(图未示)于硬掩模24上，然后利用图案化光致抗蚀剂为掩模进行一蚀刻制作工艺，去除部分硬掩模24、部分金属间介电层22、部分缓冲层20以及部分停止层18，以形成开口26暴露介电层14内的图案化导电层16表面。之后可进行一溶剂清洗(solvent clean)步骤来去除开口表面的残余物，其中溶剂清洗步骤可包含一标准RCA清洗步骤，但不局限于此。
随后如图2所示，再额外进行一处理制作工艺28将部分金属间介电层22转换为一受损层30于开口26旁。更具体而言，本实施例的处理制作工艺28较佳进行一湿式清洗制作工艺，利用例如过氧化氢(hydrogen peroxide,H2O2)等蚀刻剂在不伤害硬掩模24、缓冲层20以及停止层18的情况下来损伤或改变部分金属间介电层22的表面特性，由此将暴露于开口26的部分金属间介电层22转换为受损层30。
如图3所示，然后沉积一保护层32于开口26内并同时覆盖硬掩模24上表面、硬掩模24侧壁、受损层30侧壁、缓冲层20侧壁、停止层18侧壁以及图案化导电层16表面。在本实施例中，保护层32较佳为一单层结构，其较佳包含氮化铝(aluminum nitride,AlN)，但不局限于此。
接着如图4所示，进行一干蚀刻制作工艺，例如一各向异性蚀刻去除位于硬掩模24上表面的保护层32以及图案化导电层16表面的保护层32，使剩余的保护层32仍设于硬掩模24、受损层22、缓冲层20以及停止层18侧壁。
如图5所示，然后进行一金属内连线制作工艺，以于开口26内形成金属内连线34分别连接并接触图案化导电层16。在本实施例中，形成金属内连线的方式可依序沉积一阻隔层(图未示)与一金属层36于图案化导电层16上、保护层32侧壁表面以及硬掩模24上表面并填满开口26，然后利用一平坦化制作工艺，例如一化学机械研磨(chemical mechanicalpolishing,CMP)制作工艺去除部分金属层36、部分阻隔层、部分保护层32以及硬掩模24，以于开口26中形成金属内连线34并同时暴露出镶嵌于金属间介电层22中的受损层30，其中金属内连线34上表面较佳与受损层30、金属间介电层22以及保护层32上表面切齐。在本实施例中，阻隔层较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层30较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。
如图6所示，接着依序进行一蚀刻制作工艺去除受损层30但不去除任何保护层32，以于原本受损层30的位置形成气孔38，其中气孔38的底部较佳暴露出缓冲层20上表面。在本实施例中，用来去除受损层30的蚀刻制作工艺较佳选用包含氢氟酸(HF)的蚀刻剂来去除受损层30。
然后如图7所示，进行一紫外光固化制作工艺40，其主要用来弥补一般形成气孔38时容易造成可靠度(reliability)不足的问题。在本实施例中，紫外光固化制作工艺40的温度较佳介于摄氏300度至400度且时间较佳介于60秒至140秒。
随后如图8所示，形成一具有高压缩应力的高压缩蚀刻停止层42并覆盖金属间介电层22、气孔38以及金属层36上，使气孔38被包围在缓冲层20、保护层32、高压缩蚀刻停止层42以及金属间介电层22中。在本实施例中，高压缩蚀刻停止层42较佳包含氮碳化硅(SiCN)、氮化铝或其组合。至此即完成本发明较佳实施例的半导体元件的制作。
请继续参照图9，图9为本发明一实施例的半导体元件的结构示意图。如图9所示，相较于图6以蚀刻去除受损层30时不去除任何保护层32，本发明可于图6利用蚀刻去除受损层30的时候调整蚀刻的选择比，例如以氢氟酸同时去除受损层30以及部分保护层32以于金属间介电层22以及金属内连线34之间形成气孔38，其中剩余的保护层32上表面较佳切齐缓冲层20上表面。之后再比照图7至图8的步骤依序进行紫外光固化制作工艺40以及形成一高压缩蚀刻停止层42于金属间介电层22、气孔38以及金属内连线34上。以最终结构来看，相较于图8的气孔38是由缓冲层20、保护层32、高压缩蚀刻停止层42以及金属间介电层22所环绕，本实施例所形成的气孔38较佳被缓冲层20、保护层32、金属内连线34、高压缩蚀刻停止层42以及金属间介电层22所环绕。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种制作半导体元件的方法，其特征在于，包含：
形成一金属间介电层于一基底上；
形成一开口于该金属间介电层内；
进行一处理制作工艺将部分该金属间介电层转换为一受损层于该开口旁，其中该处理制作工艺包含进行一湿式清洗制作工艺以蚀刻部分该金属间介电层以形成该受损层；
形成一保护层于该受损层侧壁；
形成一金属层于该开口内；
去除该受损层以形成一气孔于该保护层旁；以及
在形成该气孔之后进行一紫外光固化制作工艺，以弥补形成该气孔时造成可靠度不足的问题。
2.如权利要求1所述的方法，另包含：
形成一介电层于该基底上，其中该介电层内包含一图案化导电层；
形成一停止层于该介电层上；
形成一缓冲层于该停止层上；
形成该金属间介电层于该缓冲层上；以及
形成该开口于该缓冲层、该停止层以及该金属间介电层内并暴露出该图案化导电层。
3.如权利要求2所述的方法，其中该图案化导电层上表面切齐该介电层上表面。
4.如权利要求2所述的方法，另包含：
形成该保护层于该受损层、该缓冲层以及该停止层侧壁；
形成该金属层并填满该开口；以及
进行一平坦化制作工艺去除部分该金属层以形成一金属内连线。
5.如权利要求2所述的方法，另包含在该紫外光固化制作工艺之后形成一高压缩蚀刻停止层于该金属间介电层以及该金属层上。
6.如权利要求5所述的方法，其中该气孔由该缓冲层、该保护层、该高压缩蚀刻停止层以及该金属间介电层所环绕。
7.如权利要求1所述的方法，另包含利用过氧化氢来进行该湿式清洗制作工艺。
8.一种半导体元件，其特征在于，包含：
金属间介电层，设于一基底上；
金属内连线，设于该金属间介电层内；
气孔，设于该金属内连线以及该金属间介电层之间，其中该金属内连线的下表面低于该气孔的下表面；以及
保护层，设于该金属内连线的侧壁，该保护层的下表面与该金属内连线的下表面切齐，且该保护层的上表面与该气孔的下表面切齐。
9.如权利要求8所述的半导体元件，另包含停止层，设于该金属间介电层以及该基底之间。
10.如权利要求9所述的半导体元件，另包含缓冲层，设于该停止层以及该金属间介电层之间。
11.如权利要求10所述的半导体元件，另包含高压缩蚀刻停止层，设于该金属间介电层以及该金属内连线上。
12.如权利要求11所述的半导体元件，其中该气孔由该缓冲层、该保护层、该高压缩蚀刻停止层以及该金属间介电层所环绕。
13.如权利要求8所述的半导体元件，另包含介电层，设于该金属间介电层以及该基底之间，其中该介电层内包含图案化导电层。
14.如权利要求13所述的半导体元件，其中该图案化导电层上表面切齐该介电层上表面。
15.如权利要求13所述的半导体元件，其中该金属内连线直接接触该图案化导电层。
16.如权利要求8所述的半导体元件，其中该保护层包含氮化铝。
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