CN109545735B - 金属内连线结构及其制作方法 - Google Patents

金属内连线结构及其制作方法 Download PDF

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CN109545735B
CN109545735B CN201710867909.0A CN201710867909A CN109545735B CN 109545735 B CN109545735 B CN 109545735B CN 201710867909 A CN201710867909 A CN 201710867909A CN 109545735 B CN109545735 B CN 109545735B
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layer
metal
metal interconnect
cap layer
interconnect structure
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CN109545735A (zh
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陈世宪
王明俊
王廷钧
张志圣
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Blue gun Semiconductor Co.,Ltd.
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Abstract

本发明公开一种金属内连线结构及其制作方法。该制作金属内连线结构的方法为，首先提供一基底，该基底上设有一第一金属间介电层，然后形成一第一金属内连线以及一第二金属内连线于第一金属间介电层内，去除部分第一金属间介电层以于第一金属内连线以及第二金属内连线之间形成一开口，进行一固化制作工艺，再形成一第二金属间介电层于第一金属内连线以及第二金属内连线上。

Description

金属内连线结构及其制作方法
技术领域
本发明涉及一种制作金属内连线结构的方法，尤其是涉及一种于金属内连线结构中形成气孔(air gap)的方法。
背景技术
随着半导体元件尺寸的逐渐缩小，内连线结构的线宽的逐渐变窄也使得传输信号的线阻值(line resistance,R)变大。此外，导线间的间距缩小也使得寄生电容(parasiticcapacitance,C)变大。因此，使得信号因RC延迟的状况增加，导致芯片运算速度减慢，降低了芯片的效能。
寄生电容(C)与介电层的介电常数或k值(k-value)呈线性相关。低介电常数介电材料可降低芯片上整个内连线结构的电容值、降低信号的RC延迟以及增进芯片效能。降低整体的电容同时降低了耗电量。对于超大型集成电路(ULSI)的设计而言，采用低介电常数材料以及低阻值的金属材料，可以使得整个内连线结构达到最佳效能。因此，现有技术通常试图通过将金属间的间隙以低介电常数材料填满以降低RC延迟。
一般常用氧化硅材料(SiO2)作为介电材料，虽然其具有相对高的介电常数值(4.1～4.5)，但由于其具有良好的热稳定性与化学稳定性，再加上容易通过一般的氧化物蚀刻制作工艺形成高深宽比(high aspect ratio)的接触窗与介层洞，因此仍被广泛的采用。然而，随着元件尺寸缩小以及封装密度增高，势必需要缩减金属导线间的间距，以有效的连结整个集成电路。因此，目前也研发出多种低介电常数的材料以进一步降低芯片的RC值。诸如氟化二氧化硅(fluorinated SiO2)、气溶胶(aerogel)、聚合物等等。另一种降低内连线间的介电常数值的方法则是在结构中形成气隙(air gap)。一般氧化硅材料的介电常数约介于4或更高，而空气的介电常数则约为1左右。
虽然对于降低RC值而言空气为最佳的介电材料，然而要实际在集成电路制作工艺中引入气隙结构仍面临许多问题。例如：不具支撑力的气隙结构会造成半导体装置整体的结构应力强度随之减弱，可能使得结构变形，且弱化的结构更可能在后续的集成电路制作工艺中遭遇各种不同的问题。因此，需要一种内连线结构以及其制造方法来克服上述问题。
发明内容
本发明一实施例公开一种制作金属内连线结构的方法。首先提供一基底，该基底上设有一第一金属间介电层，然后形成一第一金属内连线以及一第二金属内连线于第一金属间介电层内，去除部分第一金属间介电层以于第一金属内连线以及第二金属内连线之间形成一开口，进行一固化制作工艺，再形成一第二金属间介电层于第一金属内连线以及第二金属内连线上。
本发明另一实施利公开一种金属内连线结构，其主要包含一第一金属间介电层设于基底上、第一金属内连线以及第二金属内连线设于第一金属间介电层内以及一气孔设于第一金属内连线以及第二金属内连线之间，其中气孔的顶点优选高于第一金属内连线上表面。
附图说明
图1至图7为本发明优选实施例制作一金属内连线结构的方法示意图。
主要元件符号说明
12 基底 14 层间介电层
16 第一金属间介电层 18 金属内连线
20 金属内连线 22 金属内连线
24 金属内连线 26 第一遮盖层
28 图案化光致抗蚀剂 30 开口
32 开口 34 聚合物
36 固化制作工艺 38 第二遮盖层
40 第二金属间介电层 42 气孔
44 倾斜侧壁 46 圆弧底部
具体实施方式
请参照图1至图7，图1至图7为本发明优选实施例制作一金属内连线结构的方法示意图。如图1所示，首先提供一基底12，例如一由半导体材料所构成的基底12，其中半导体材料可选自由硅、锗、硅锗复合物、硅碳化物(silicon carbide)、砷化镓(gallium arsenide)等所构成的群组。基底12上可包含例如金属氧化物半导体(metal-oxide semiconductor,MOS)晶体管等主动元件、被动元件、导电层以及例如层间介电层(interlayer dielectric,ILD)14等介电层覆盖于其上。更具体而言，基底12上可包含平面型或非平面型(如鳍状结构晶体管)等MOS晶体管元件，其中MOS晶体管可包含金属栅极以及源极/漏极区域、间隙壁、外延层、接触洞蚀刻停止层等晶体管元件，层间介电层较可设于基底12上并覆盖MOS晶体管，且层间介电层可具有多个接触插塞电连接MOS晶体管的栅极以及/或源极/漏极区域。由于平面型或非平面型晶体管以及层间介电层等相关制作工艺均为本领域所熟知技术，在此不另加赘述。
然后于层间介电层14上依序形成金属内连线结构电连接前述的接触插塞，其中金属内连线结构优选包含一选择性停止层(图未示)设于层间介电层14上、一第一金属间介电层16以及多个金属内连线18、20、22、24镶嵌于第一金属间介电层16内，且各金属内连线18、20、22、24上表面优选切齐第一金属间介电层16上表面。需注意的是，本实施例虽于第一金属间介电层16内形成四个金属内连线18、20、22、24为例，但所设置的金属内连线18、20、22、24数量并不局限于此，而可视制作工艺需求调整。
其次金属内连线结构中的各金属内连线18、20、22、24虽优选由单一沟槽导体(trench conductor)所构成，但不局限于此，依据本发明其他实施利各金属内连线18、20、22、24又可包含沟槽导体(trench conductor)、接触洞导体(via conductor)、或其组合，且各金属内连线18、20、22、24均优选依据双镶嵌制作工艺镶嵌于第一金属间介电层16以及/或停止层内并彼此电连接。由于双镶嵌制作工艺是本领域所熟知技术，在此不另加赘述。另外在本实例中金属内连线18、20、22、24优选包含铜、第一金属间介电层16优选包含氧化硅、而停止层则包含氮化硅，但不局限于此。接着形成一第一遮盖层26于第一金属间介电层16以及金属内连线18、20、22、24上，其中第一遮盖层26优选包含氮掺杂碳化物(nitrogendoped carbide,NDC)，但不局限于此。
如图2所示，然后形成一图案化掩模，例如一图案化光致抗蚀剂28于第一遮盖层26上，其中图案化光致抗蚀剂28具有一开口30暴露出部分第一遮盖层26表面。
如图3所示，接着利用图案化光致抗蚀剂28为掩模进行一蚀刻制作工艺来去除部分第一遮盖层26以及部分第一金属间介电层16以形成开口32暴露出金属内连线18、20、22、24上表面与侧壁。在本实施例中，本阶段的蚀刻制作工艺优选为一干蚀刻制作工艺，且形成开口32后第一遮盖层26表面可能残留有聚合物34。
值得注意的是，干蚀刻制作工艺所使用的蚀刻气体优选可选用由氮气以及/或氢气所构成的群组，其中氮气的流量约270～330每分钟标准毫升(standard cubiccentimeter per minute,sccm)而氢气的流量则约720～880sccm。一般而言，在利用氮气以及/或氢气的气体组合去除部分第一遮盖层26以及部分第一金属间介电层16时容易因蚀刻比的控制不佳同时去除部分金属内连线18、20、22、24造成削角的情况，进而影响后续所形成气孔的相对位置与大小。有鉴于此，本实施例可依据上述范围来调整氮气与氢气之间的流量比例，由此改善金属内连线18、20、22、24于蚀刻的过程中造成削角的问题。
随后如图4所示，进行另一蚀刻制作工艺，例如利用湿蚀刻来去除残留于第一遮盖层26上的聚合物34。
如图5所示，接着于前述湿蚀刻制作工艺后进行一固化制作工艺36来提升所沉积第一遮盖层26甚至第一金属间介电层16的强度。一般而言，当施加于介电材料上的电场强度超过临界值时，若流过该介电材料电流突然增大容易使介电材料完全失效而产生所谓的时间相依介电击穿(time-dependent dielectric breakdown,TDDB)问题。有鉴于此，本实施例优选于前述湿蚀刻制作工艺后进行上述固化制作工艺来提升所沉积介电材料的整体强度并同时改善此问题。在本实施例中，固化制作工艺可包含例如一极紫外光固化制作工艺，其温度优选介于摄氏347度至摄氏424度或最佳约摄氏385度。
然后如图6所示，形成一第二遮盖层38于第一遮盖层26以及金属内连线18、20、22、24上并填入金属内连线18、20、22、24之间的开口32内但不填满开口32。在本实施例中，第一遮盖层26以及第二遮盖层38可依据制作工艺或产品需求选用相同或不同材料，例如若两者均包含相同材料，则第一遮盖层26及第二遮盖层38均优选由氮掺杂碳化物所构成。若两者包含不同材料，则第一遮盖层26优选包含氮掺杂碳化物而第二遮盖层38则优选包含金属氮化物，其中金属氮化物优选选用氮化铝(AlN)，但不局限于此。
如图7所示，之后形成一第二金属间介电层40于第二遮盖层38上并同时形成气孔42于金属内连线18、20、22、24之间。更具体而言，各气孔42是由第二遮盖层38以及第二金属间介电层40所环绕，且各气孔42的顶点优选高于金属内连线18、20、22、24上表面。在本实施例中，各气孔42优选呈现约略水滴状，其中各气孔42的上半部优选包含二平坦的倾斜侧壁44而下半部则优选包含一圆弧底部46。以位置来看，各气孔42的最顶点优选高于第一金属间介电层16、金属内连线18、20、22、24以及第一遮盖层26上表面、高于设于金属内连线18、20、22、24正上方的第二遮盖层38上表面并略低于设于第一遮盖层26正上方的第二遮盖层38上表面，同时各气孔42的圆弧底部46则优选低于各金属内连线18、20、22、24的一半高度。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (21)

1.一种制作金属内连线结构的方法，包含：
提供一基底，该基底上设有一第一金属间介电层；
形成一第一金属内连线以及一第二金属内连线于该第一金属间介电层内；
形成一第一遮盖层于该第一金属间介电层、该第一金属内连线以及该第二金属内连线上；
进行一蚀刻制作工艺去除部分该第一遮盖层以及部分该第一金属间介电层以于该第一金属内连线以及该第二金属内连线之间形成一开口；
形成该开口后，进行一固化制作工艺；
形成一第二遮盖层于该第一遮盖层、该第一金属内连线以及该第二金属内连线上；以及
形成一第二金属间介电层于该第二遮盖层上并同时形成一气孔，其中该气孔的顶点高于未接触该第一遮盖层的部分该第二遮盖层的上表面，且低于设在该第一遮盖层正上方的该第二遮盖层的上表面。
2.如权利要求1所述的方法，其中该固化制作工艺包含一极紫外光固化制作工艺。
3.如权利要求2所述的方法，其中该第一遮盖层以及该第二遮盖层包含相同材料。
4.如权利要求3所述的方法，其中该第一遮盖层以及该第二遮盖层包含氮掺杂碳化物层(nitrogen doped carbide,NDC)。
5.如权利要求2所述的方法，其中该第一遮盖层以及该第二遮盖层包含不同材料。
6.如权利要求5所述的方法，其中该第一遮盖层包含氮掺杂碳化物以及该第二遮盖层包含金属氮化物。
7.如权利要求2所述的方法，其中该气孔是由该第二遮盖层以及该第二金属间介电层所环绕。
8.如权利要求2所述的方法，其中该气孔的顶点高于该第一金属内连线上表面。
9.如权利要求1所述的方法，其中该第一金属内连线上表面切齐该第一金属间介电层上表面。
10.如权利要求1所述的方法，其中该固化制作工艺的温度介于摄氏347度至摄氏424度。
11.如权利要求1所述的方法，其中该气孔的顶点高于该第一遮盖层的上表面。
12.一种金属内连线结构，包含：
基底，该基底上设有第一金属间介电层；
第一金属内连线以及第二金属内连线设于该第一金属间介电层内；
第一遮盖层，设于该第一金属间介电层上；
第二遮盖层，直接覆盖于该第一金属内连线以及该第二金属内连线的上表面和侧壁、该第一遮盖层，以及该第一金属内连线与该第二金属内连线之间的该第一金属间介电层的表面上；以及
气孔，设于该第一金属内连线以及该第二金属内连线之间并被该第二遮盖层环绕，其中该气孔的顶点高于该第一金属内连线的上表面，并高于未接触该第一遮盖层的部分该第二遮盖层的上表面，且低于设在该第一遮盖层正上方的该第二遮盖层的上表面。
13.如权利要求12所述的金属内连线结构，其中该第一遮盖层以及该第二遮盖层包含相同材料。
14.如权利要求13所述的金属内连线结构，其中该第一遮盖层以及该第二遮盖层包含氮掺杂碳化物层(nitrogen doped carbide,NDC)。
15.如权利要求12所述的金属内连线结构，其中该第一遮盖层以及该第二遮盖层包含不同材料。
16.如权利要求15所述的金属内连线结构，其中该第一遮盖层包含氮掺杂碳化物以及该第二遮盖层包含金属氮化物。
17.如权利要求12所述的金属内连线结构，还包含一第二金属间介电层设于该第二遮盖层上。
18.如权利要求17所述的金属内连线结构，其中该气孔是由该第二遮盖层以及该第二金属间介电层所环绕。
19.如权利要求12所述的金属内连线结构，其中该气孔的底部低于该第一金属内连线的一半高度。
20.如权利要求12所述的金属内连线结构，其中该第一金属内连线上表面切齐该第一金属间介电层上表面。
21.如权利要求12所述的金属内连线结构，其中该气孔的顶点高于该第一遮盖层的上表面。
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