JP5411436B2 - 集積回路及びその製造方法 - Google Patents
集積回路及びその製造方法 Download PDFInfo
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- JP5411436B2 JP5411436B2 JP2008052894A JP2008052894A JP5411436B2 JP 5411436 B2 JP5411436 B2 JP 5411436B2 JP 2008052894 A JP2008052894 A JP 2008052894A JP 2008052894 A JP2008052894 A JP 2008052894A JP 5411436 B2 JP5411436 B2 JP 5411436B2
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- gap
- opening
- interlayer insulating
- insulating film
- edge
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- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000011229 interlayer Substances 0.000 claims description 50
- 239000010410 layer Substances 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 2
- 238000013459 approach Methods 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
Claims (2)
- 基体の上に積層され、狭い溝を形成する間隙部及び当該間隙部につながる広い開口部が形成されたパターンを有する配線層と、
前記配線層を覆って堆積された層間絶縁膜と、を有し、
前記間隙部と前記開口部との接続部分に生じる前記配線層の前記パターンの角部は面取りされて、前記間隙部の端部が前記開口部へ向けて末広がりの形状に形成され、
前記層間絶縁膜は、その下に前記端部以外の前記間隙部を埋没させる膜厚に堆積され、
前記堆積された膜厚を有する層間絶縁膜は、前記開口部内に凹部を形成し、
前記間隙部の前記端部の前記開口部側は、前記層間絶縁膜が前記間隙部内に窪みを形成して堆積される広さまで拡大され、前記窪みが前記開口部内の前記凹部につながり、
前記パターンは前記面取りされた角部にて、前記狭い溝に平行な第1の縁、前記開口部に面し、かつ前記第1の縁に垂直な第2の縁、及び、前記第1の縁と前記第2の縁とのそれぞれに対して斜めに交差する傾斜した縁を有し、
前記間隙部に沿った或る位置での前記間隙部の端部の幅は、当該位置が前記第2の縁の延長線で定義される前記開口部の境界に近づくにつれて単調に増加すること、
を特徴とする集積回路。 - 基体の上に積層され、狭い溝を形成する間隙部及び当該間隙部につながる広い開口部が形成されたパターンを有する配線層と、前記配線層を覆って堆積された層間絶縁膜と、を有する集積回路を製造する方法において、
前記基体上に積層された前記配線層をパターニングして、前記間隙部と前記開口部との接続部分に生じる前記配線層の前記パターンの角部が面取りされ、前記間隙部の端部が前記開口部へ向けて末広がりの形状となる前記パターンを形成する配線層パターニング工程と、
パターニングされた前記配線層に、前記端部以外の前記間隙部を埋没させる膜厚の前記層間絶縁膜を堆積する層間絶縁膜堆積工程と、を有し、
前記堆積された膜厚を有する層間絶縁膜は、前記開口部内に凹部を形成し、
前記間隙部の前記端部の前記開口部側は、前記層間絶縁膜が前記間隙部内に窪みを形成して堆積される広さまで拡大され、前記窪みが前記開口部内の前記凹部につながり、
前記配線層パターニング工程は、前記面取りされた角部にて、前記狭い溝に平行な第1の縁、前記開口部に面し、かつ前記第1の縁に垂直な第2の縁、及び、前記第1の縁と前記第2の縁とのそれぞれに対して斜めに交差する傾斜した縁を形成し、
前記間隙部に沿った或る位置での前記間隙部の端部の幅は、当該位置が前記第2の縁の延長線で定義される前記開口部の境界に近づくにつれて単調に増加すること、
を特徴とする集積回路の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008052894A JP5411436B2 (ja) | 2008-03-04 | 2008-03-04 | 集積回路及びその製造方法 |
US12/379,793 US8097951B2 (en) | 2008-03-04 | 2009-03-02 | Integrated circuit having wiring layer and a pattern in which a gap is formed and method for manufacturing same |
CN200910118577.1A CN101527296B (zh) | 2008-03-04 | 2009-03-04 | 集成电路及其制造方法 |
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---|---|---|---|
JP2008052894A JP5411436B2 (ja) | 2008-03-04 | 2008-03-04 | 集積回路及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009212262A JP2009212262A (ja) | 2009-09-17 |
JP5411436B2 true JP5411436B2 (ja) | 2014-02-12 |
Family
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JP2008052894A Active JP5411436B2 (ja) | 2008-03-04 | 2008-03-04 | 集積回路及びその製造方法 |
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---|---|
US (1) | US8097951B2 (ja) |
JP (1) | JP5411436B2 (ja) |
CN (1) | CN101527296B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5460141B2 (ja) | 2009-06-26 | 2014-04-02 | ラピスセミコンダクタ株式会社 | 半導体装置 |
CN109545735B (zh) * | 2017-09-22 | 2022-01-28 | 蓝枪半导体有限责任公司 | 金属内连线结构及其制作方法 |
KR20210092916A (ko) | 2020-01-17 | 2021-07-27 | 삼성전자주식회사 | 배선 구조물 및 이를 포함하는 수직형 메모리 장치 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06105710B2 (ja) * | 1990-02-14 | 1994-12-21 | 株式会社東芝 | 半導体装置 |
JPH05129400A (ja) * | 1991-11-05 | 1993-05-25 | Sharp Corp | Tegマスクパターンのレイアウト方法 |
JPH0945686A (ja) * | 1995-08-03 | 1997-02-14 | Hitachi Ltd | 半導体装置およびその製造方法 |
US5677241A (en) * | 1995-12-27 | 1997-10-14 | Micron Technology, Inc. | Integrated circuitry having a pair of adjacent conductive lines and method of forming |
JP3311243B2 (ja) * | 1996-07-16 | 2002-08-05 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置及び半導体装置のパターン配置方法 |
JP2000031338A (ja) | 1998-07-13 | 2000-01-28 | Hitachi Ltd | 半導体装置及びその製法 |
JP4434405B2 (ja) | 2000-01-27 | 2010-03-17 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置 |
JP3779243B2 (ja) * | 2002-07-31 | 2006-05-24 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP4405865B2 (ja) * | 2004-06-24 | 2010-01-27 | 富士通マイクロエレクトロニクス株式会社 | 多層配線構造の製造方法及びfib装置 |
-
2008
- 2008-03-04 JP JP2008052894A patent/JP5411436B2/ja active Active
-
2009
- 2009-03-02 US US12/379,793 patent/US8097951B2/en active Active
- 2009-03-04 CN CN200910118577.1A patent/CN101527296B/zh active Active
Also Published As
Publication number | Publication date |
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CN101527296B (zh) | 2010-12-08 |
US8097951B2 (en) | 2012-01-17 |
US20090224373A1 (en) | 2009-09-10 |
JP2009212262A (ja) | 2009-09-17 |
CN101527296A (zh) | 2009-09-09 |
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