TWI801614B - 半導體元件及其製作方法 - Google Patents
半導體元件及其製作方法 Download PDFInfo
- Publication number
- TWI801614B TWI801614B TW108121622A TW108121622A TWI801614B TW I801614 B TWI801614 B TW I801614B TW 108121622 A TW108121622 A TW 108121622A TW 108121622 A TW108121622 A TW 108121622A TW I801614 B TWI801614 B TW I801614B
- Authority
- TW
- Taiwan
- Prior art keywords
- dielectric layer
- metal interconnection
- sidewall
- intermetal
- semiconductor device
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
本發明揭露一種製作半導體元件的方法。首先形成一第一金屬間介電層於一基底上,然後形成一第一金屬內連線於該第一金屬間介電層內,去除部分該第一金屬間介電層,形成一側壁子於該第一金屬內連線旁,形成一第二金屬間介電層於該側壁子及該第一金屬內連線上,再形成一第二金屬內連線於該第二金屬間介電層內並設於該側壁子及該第一金屬內連線上。
Description
本發明是關於一種製作金屬內連線的方法,尤指一種於金屬內連線側壁形成側壁子的方法。
隨著半導體元件尺寸的逐漸縮小,內連線結構的線寬的逐漸變窄也使得傳輸訊號的線阻值(line resistance,R)變大。此外,導線間的間距縮小也使得寄生電容(parasitic capacitance,C)變大。因此,使得訊號因RC延遲的狀況增加,導致晶片運算速度減慢,降低了晶片的效能。
寄生電容(C)係與介電層之介電常數或k值(k-value)呈線性相關。低介電常數介電材料可降低晶片上整個內連線結構的電容值、降低訊號的RC延遲以及增進晶片效能。降低整體的電容同時降低了耗電量。對於超大型積體電路(ULSI)的設計而言,採用低介電常數材料以及低阻值的金屬材料,可以使得整個內連線結構達到最佳效能。因
此,習知技術通常試圖藉由將金屬間的間隙以低介電常數材料填滿以降低RC延遲。
一般常用氧化矽材料(SiO2)作為介電材料,雖然其具有相對高的介電常數值(4.1-4.5),但由於其具有良好的熱穩定性與化學穩定性,再加上容易藉由一般的氧化物蝕刻製程形成高深寬比(high aspect ratio)的接觸窗與介層洞,因此仍被廣泛的採用。然而,隨著元件尺寸縮小以及封裝密度增高,勢必需要縮減金屬導線間的間距,以有效的連結整個積體電路。因此,目前也研發出多種低介電常數之材料以進一步降低晶片的RC值。諸如氟化二氧化矽(fluorinated SiO2)、氣溶膠(aerogel)、聚合物等等。另一種降低內連線間的介電常數值之方法則是在結構中形成氣隙(air gap)。一般氧化矽材料的介電常數約介於4或更高,而空氣的介電常數則約為1左右。
雖然對於降低RC值而言空氣為最佳的介電材料,然而要實際在積體電路製程中引入氣隙結構仍面臨許多問題。例如:不具支撐力的氣隙結構會造成半導體裝置整體的結構應力強度隨之減弱,可能使得結構變形,且弱化的結構更可能在後續的積體電路製程中遭遇各種不同的問題。因此,需要一種內連線結構以及其製造方法來克服上述問題。
本發明一實施例揭露一種製作半導體元件的方法。首先形成
一第一金屬間介電層於一基底上,然後形成一第一金屬內連線於該第一金屬間介電層內,去除部分該第一金屬間介電層,形成一側壁子於該第一金屬內連線旁,形成一第二金屬間介電層於該側壁子及該第一金屬內連線上,再形成一第二金屬內連線於該第二金屬間介電層內並設於該側壁子及該第一金屬內連線上。
本發明另一實施例揭露一種半導體元件,其主要包含一第一金屬間介電層設於一基底上、一第一金屬內連線設於該第一金屬間介電層內、一第一側壁子設於該第一金屬內連線一側並設於該第一金屬間介電層上以及一第二金屬內連線設於該第一側壁子以及該第一金屬內連線上。
12:基底
14:金屬內連線結構
16:金屬間介電層
18:金屬內連線
20:蝕刻製程
22:殘餘物
24:側壁子
26:側壁子
28:介電層
30:介電層
32:介電層
34:金屬內連線
36:金屬間介電層
38:突出部
第1圖至第4圖為本發明一實施例製作一金屬內連線結構之方法示意圖。
請參照第1圖至第4圖,第1圖至第4圖為本發明一實施例製作一金屬內連線結構之方法示意圖。如第1圖所示,首先提供一基底12,例如一由半導體材料所構成的基底12,其中半導體材料可選自由矽、鍺、矽鍺複合物、矽碳化物(silicon carbide)、砷化鎵(gallium arsenide)等所構成之群組。基底12上可包含例如金氧半導體(metal-oxide
semiconductor,MOS)電晶體等主動元件、被動元件、導電層以及例如層間介電層(interlayer dielectric,ILD)(圖未示)等介電層覆蓋於其上。更具體而言,基底12上可包含平面型或非平面型(如鰭狀結構電晶體)等MOS電晶體元件,其中MOS電晶體可包含金屬閘極以及源極/汲極區域、側壁子、磊晶層、接觸洞蝕刻停止層等電晶體元件,層間介電層較可設於基底12上並覆蓋MOS電晶體,且層間介電層可具有複數個接觸插塞電連接MOS電晶體之閘極以及/或源極/汲極區域。由於平面型或非平面型電晶體與層間介電層等相關製程均為本領域所熟知技藝,在此不另加贅述。
然後於層間介電層上形成至少一組金屬內連線結構14電連接前述之接觸插塞,其中金屬內連線結構14包含一金屬間介電層16以及複數個金屬內連線18鑲嵌於金屬間介電層16中。需注意的是,本實施例雖僅以一組金屬內連線結構14為例,但所設置的金屬內連線結構數量並不局限於此,而可視製程需求調整。其次金屬內連線結構14中的各金屬內連線18可包含溝渠導體(trench conductor)以及/或接觸洞導體(via conductor),且各金屬內連線18均較佳依據雙鑲嵌製程鑲嵌於金屬間介電層16中並彼此電連接,由於雙鑲嵌製程乃本領域所熟知技藝,在此不另加贅述。另外在本實例中金屬內連線18較佳包含銅且金屬間介電層16較佳包含氧化矽,但不侷限於此。
然後如第2圖所示,先進行一蝕刻製程20,例如可直接以所暴露出的金屬內連線18為遮罩去除部分金屬間介電層16,使剩餘的金屬間介電層16上表面略低於金屬內連線18的上表面,並藉此暴露出部
分金屬內連線18的部分側壁。需注意的是,本階段所進行的蝕刻製程20又可細部包含一乾蝕刻製程以及一濕蝕刻製程,其中乾蝕刻製程可利用例如CxFy以及/或氮氣(N2)等氣體來去除部分金屬間介電層,接著進行一濕蝕刻製程,利用例如過氧化氫(H2O2)以及/或稀釋氫氟酸(dHF)來去除附著於金屬間介電層16與金屬內連線18表面的殘餘物22。
接著如第3圖所示,先覆蓋一遮蓋層(圖未示),例如一低介電常數介電材料於金屬間介電層16與金屬內連線18上,然後進行一回蝕刻製程或更具體而言一乾蝕刻製程,利用CxFy為主要蝕刻氣體成分來去除部分介電材料,以於各金屬內連線18的左右側壁上分別形成一側壁子24、26。在本實施例中,側壁子24、26較佳與金屬間介電層16為不同材料,其中側壁子24、26可由氧化物、氮化物、金屬氧化物或金屬氮化物所構成。依據本發明一實施例側壁子24、26可包含但不侷限於氧化矽、氮化矽、氮氧化矽(SiON)、氮碳化矽(SiCN)、氮氧化矽(SiOC)、氮化鈦、氮化鋁、氮化鉭、氮化鉿、氧化鈦、氧化鋁、氧化鉭或氧化鉿。
需注意的是,本實施例雖較佳如第2圖控制剩餘的金屬間介電層16上表面略低於金屬內連線18的上表面,但不侷限於此,若金屬內連線18同時包含溝渠導體與接觸洞導體,本發明又可依據製程需求調整剩餘金屬間介電層20的高度,例如可將剩餘的金屬間介電層16上表面控制與溝渠導體底表面齊平。如此後續所形成的側壁子24、26底部將與溝渠導體的底部齊平,此實施例也屬本發明所涵蓋的範圍。
接著如第4圖所示,形成另一金屬間介電層36於金屬間介電層16上並覆蓋各金屬內連線18,例如可先形成一介電層28於金屬間介電層16表面,一介電層30於介電層28上以及另一介電層32於介電層30表面。在本實施例中,介電層28較佳包含氮化矽,介電層30包含氧化矽,介電層32則包含低介電常數介電層。隨後形成複數個金屬內連線34於介電層28、30、32內電連接下方的金屬內連線18或其他導線,其中部分金屬內連線34在連接下層金屬內連線18時較佳偏移下層金屬內連線18的中心且延伸出金屬內連線18一側的側壁並同時跨在金屬內連線18一側的側壁子24上。至此即完成本發明一實施例之一金屬內連線結構的製作。如同金屬內連線18,本階段所形成的各金屬內連線34可包含溝渠導體以及/或接觸洞導體,且各金屬內連線34均較佳依據雙鑲嵌製程鑲嵌於介電層28、30、32中,由於雙鑲嵌製程乃本領域所熟知技藝,在此不另加贅述。另外在本實例中金屬內連線34較佳包含銅,但不侷限於此。
請再參照第4圖,第4圖另揭露本發明一實施例之一半導體元件之結構示意圖。如第4圖所示,半導體元件主要包含金屬間介電層16設於基底12上,複數個金屬內連線18設於金屬間介電層16內,側壁子24設於各金屬內連線18一側並設於金屬間介電層16上,側壁子26設於各金屬內連線18另一側,金屬內連線34設於側壁子24與金屬內連線18上以及金屬間介電層36設於金屬間介電層16上並環繞金屬內連線18,其中金屬間介電層36又細部包含介電層28、介電層30以及介電層32。
從細部來看,例如以圖中最左側的金屬內連線34連接金屬內
連線18為例,金屬內連線34較佳向左側延伸超過金屬內連線18邊緣且向下延伸形成一突出部38接觸下方的金屬內連線18側壁及設於金屬內連線18左側的側壁子24,同時金屬內連線34側壁較佳切齊側壁子24側壁。整體來看設於金屬內連線18左側的側壁子24與設於金屬內連線18右側的側壁子26較佳為不對稱結構,其中所謂不對稱結構可代表兩者具有不同高度、不同寬度、以及/或不同形狀。在本實施例中,左側的側壁子24上表面較佳低於右側的側壁子26上表面,且左側的側壁子24上表面由於在形成上方金屬內連線34的突出部38時被部分去除,因此左側的側壁子24上表面較佳呈現一平坦表面,而右側的側壁子26則整體呈現半月形。
綜上所述,本發明主要於金屬內連線製程時先去除部分金屬間介電層,形成側壁子於下層金屬內連線的左右側壁,接著形成上層金屬內連線電連接下層金屬內連線,其中上層金屬內連線略為偏移下層金屬內連線的中心點並同時跨在部分下層金屬內連線與下層金屬內連線一側的側壁子上。由於習知下層金屬內連線的側壁並未設置任何阻擋結構,因此連接上層金屬內連線連與下層金屬內連線時所形成如第4圖所示的突出部38或虎牙結構常因下方無任何阻擋繼續向下延伸並導致嚴重漏電。為了改善此問題本發明主要依據前述製程於下層金屬內連線側壁形成側壁子作為上層金屬內連線的阻隔結構,如此即可避免上層金屬內連線與下層金屬內連線連接時不至因突出部過度延伸而造成漏電。以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之
均等變化與修飾,皆應屬本發明之涵蓋範圍。
12:基底
14:金屬內連線結構
16:金屬間介電層
18:金屬內連線
24:側壁子
26:側壁子
28:介電層
30:介電層
32:介電層
34:金屬內連線
36:金屬間介電層
38:突出部
Claims (13)
- 一種製作半導體元件的方法,其特徵在於,包含:形成一第一金屬間介電層於一基底上,其中該第一金屬間介電層包括單層結構;形成一第一金屬內連線於該第一金屬間介電層內,其中該第一金屬內連線的一底面與該第一金屬間介電層的一底面切齊;去除部分該第一金屬間介電層;形成一側壁子於該第一金屬內連線旁,其中該第一金屬間介電層的一頂面與該第一側壁子的一底面切齊;形成一第二金屬間介電層於該側壁子及該第一金屬內連線上,其中形成該第二金屬間介電層包括:形成一第一介電層,覆蓋該第一側壁子以及該第一金屬內連線的一頂面;於該第一介電層上形成一第二介電層;以及於該第二介電層上形成一第三介電層;以及形成一第二金屬內連線穿過該第三介電層、該第二介電層和該第一介電層,以與該側壁子及該第一金屬內連線直接接觸。
- 如申請專利範圍第1項所述之方法,其中該第一介電層包含氮化矽。
- 如申請專利範圍第1項所述之方法,其中該第二介電層包含 氧化矽。
- 如申請專利範圍第1項所述之方法,其中該第三介電層包含低介電常數介電層。
- 如申請專利範圍第1項所述之方法,其中該第二金屬內連線側壁切齊該側壁子側壁。
- 一種半導體元件,其特徵在於,包含:一第一金屬間介電層設於一基底上,其中該第一金屬間介電層包括單層結構;一第一金屬內連線設於該第一金屬間介電層內,其中該第一金屬內連線的一底面與該第一金屬間介電層的一底面切齊;一第一側壁子設於該第一金屬內連線一側並設於該第一金屬間介電層上,其中該第一金屬間介電層的一頂面與該第一側壁子的一底面切齊;一第二金屬間介電層設於該第一金屬間介電層上,其中該第二金屬間介電層包括:一第一介電層,覆蓋該第一側壁子以及該第一金屬內連線的一頂面;一第二介電層,設於該第一介電層上;以及一第三介電層,設於該第二介電層上;以及一第二金屬內連線完全穿過該第三介電層、該第二介電層和該第一介電層,以與該第一側壁子以及該第一金屬內連線直接接觸。
- 如申請專利範圍第6項所述之半導體元件,其中該第一介電層包含氮化矽。
- 如申請專利範圍第6項所述之半導體元件,其中該第二介電層包含氧化矽。
- 如申請專利範圍第6項所述之半導體元件,其中該第三介電層包含低介電常數介電層。
- 如申請專利範圍第6項所述之半導體元件,其中該第二金屬內連線側壁切齊該第一側壁子側壁。
- 如申請專利範圍第6項所述之半導體元件,另包含一第二側壁子設於該第一金屬內連線另一側。
- 如申請專利範圍第11項所述之半導體元件,其中該第一側壁子及該第二側壁子不對稱。
- 如申請專利範圍第15項所述之半導體元件,其中該第一側壁子上表面低於該第二側壁子上表面。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108121622A TWI801614B (zh) | 2019-06-21 | 2019-06-21 | 半導體元件及其製作方法 |
US16/518,928 US11456207B2 (en) | 2019-06-21 | 2019-07-22 | Semiconductor device including metal interconnections having sidewall spacers thereon, and method for fabricating the same |
US17/888,502 US11791203B2 (en) | 2019-06-21 | 2022-08-16 | Semiconductor device including metal interconnections having sidewall spacers thereon, and method for fabricating the same |
US18/243,096 US20230420292A1 (en) | 2019-06-21 | 2023-09-06 | Semiconductor device and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108121622A TWI801614B (zh) | 2019-06-21 | 2019-06-21 | 半導體元件及其製作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202101671A TW202101671A (zh) | 2021-01-01 |
TWI801614B true TWI801614B (zh) | 2023-05-11 |
Family
ID=74038314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108121622A TWI801614B (zh) | 2019-06-21 | 2019-06-21 | 半導體元件及其製作方法 |
Country Status (2)
Country | Link |
---|---|
US (3) | US11456207B2 (zh) |
TW (1) | TWI801614B (zh) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090166881A1 (en) * | 2007-12-27 | 2009-07-02 | Sridhar Balakrishnan | Air-gap ild with unlanded vias |
US20170221891A1 (en) * | 2016-01-29 | 2017-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5981395A (en) | 1997-10-18 | 1999-11-09 | United Microelectronics Corp. | Method of fabricating an unlanded metal via of multi-level interconnection |
US7026714B2 (en) * | 2003-03-18 | 2006-04-11 | Cunningham James A | Copper interconnect systems which use conductive, metal-based cap layers |
KR100532437B1 (ko) * | 2003-05-26 | 2005-11-30 | 삼성전자주식회사 | 반도체 메모리 소자 및 그 제조 방법 |
US7649239B2 (en) * | 2006-05-04 | 2010-01-19 | Intel Corporation | Dielectric spacers for metal interconnects and method to form the same |
US7973409B2 (en) * | 2007-01-22 | 2011-07-05 | International Business Machines Corporation | Hybrid interconnect structure for performance improvement and reliability enhancement |
KR20130007378A (ko) * | 2011-07-01 | 2013-01-18 | 삼성전자주식회사 | 반도체 장치 |
US9396990B2 (en) | 2013-01-31 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Capping layer for improved deposition selectivity |
US9312222B2 (en) * | 2013-03-12 | 2016-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Patterning approach for improved via landing profile |
KR102289376B1 (ko) * | 2015-01-19 | 2021-08-17 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체 장치 및 그 제조방법 |
US9685368B2 (en) * | 2015-06-26 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure having an etch stop layer over conductive lines |
US9984967B2 (en) * | 2015-12-21 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
US9653347B1 (en) * | 2016-03-31 | 2017-05-16 | International Business Machines Corporation | Vertical air gap subtractive etch back end metal |
US10453749B2 (en) * | 2017-02-14 | 2019-10-22 | Tokyo Electron Limited | Method of forming a self-aligned contact using selective SiO2 deposition |
US10840133B2 (en) * | 2018-09-27 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with staggered selective growth |
US11594485B2 (en) * | 2019-06-04 | 2023-02-28 | Intel Corporation | Local interconnect with air gap |
-
2019
- 2019-06-21 TW TW108121622A patent/TWI801614B/zh active
- 2019-07-22 US US16/518,928 patent/US11456207B2/en active Active
-
2022
- 2022-08-16 US US17/888,502 patent/US11791203B2/en active Active
-
2023
- 2023-09-06 US US18/243,096 patent/US20230420292A1/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090166881A1 (en) * | 2007-12-27 | 2009-07-02 | Sridhar Balakrishnan | Air-gap ild with unlanded vias |
US20170221891A1 (en) * | 2016-01-29 | 2017-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US20220392798A1 (en) | 2022-12-08 |
US20230420292A1 (en) | 2023-12-28 |
US11791203B2 (en) | 2023-10-17 |
US20200402837A1 (en) | 2020-12-24 |
TW202101671A (zh) | 2021-01-01 |
US11456207B2 (en) | 2022-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11532512B2 (en) | Fin field effect transistor (FinFET) device structure with interconnect structure | |
US11664237B2 (en) | Semiconductor device having improved overlay shift tolerance | |
KR101742925B1 (ko) | 다마신 구조물의 구조물 및 형성방법 | |
US10134669B2 (en) | Method for forming fin field effect transistor (FinFET) device structure with interconnect structure | |
CN106033741B (zh) | 金属内连线结构及其制作方法 | |
KR101653460B1 (ko) | 이중 다마신 구조체 및 그 형성 방법 | |
JP2003514397A (ja) | 自己整合されたビア構造における空隙誘電体 | |
KR20160140314A (ko) | 반도체 소자 구조물의 상호 연결 구조물의 비아 윤곽을 형성하는 방법 | |
TWI686880B (zh) | 半導體裝置和其製造方法 | |
KR102024971B1 (ko) | 반도체 디바이스 및 그 제조 방법 | |
TWI724434B (zh) | 半導體裝置及其製造方法 | |
CN109545735B (zh) | 金属内连线结构及其制作方法 | |
TWI801614B (zh) | 半導體元件及其製作方法 | |
CN110838464A (zh) | 金属内连线结构及其制作方法 | |
US11699589B2 (en) | Method for forming patterned mask layer | |
US11658067B2 (en) | Semiconductor structure and formation method thereof | |
CN115954324B (zh) | 一种半导体结构及其制作方法 | |
KR100678003B1 (ko) | 듀얼 다마신 패턴 형성 방법 | |
CN112838048A (zh) | 互连结构以及其制作方法 |