TWI515802B - 電荷儲存裝置、系統及方法 - Google Patents
電荷儲存裝置、系統及方法 Download PDFInfo
- Publication number
- TWI515802B TWI515802B TW101105342A TW101105342A TWI515802B TW I515802 B TWI515802 B TW I515802B TW 101105342 A TW101105342 A TW 101105342A TW 101105342 A TW101105342 A TW 101105342A TW I515802 B TWI515802 B TW I515802B
- Authority
- TW
- Taiwan
- Prior art keywords
- charge storage
- polysilicon
- dielectric
- storage structure
- opening
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 146
- 229920005591 polysilicon Polymers 0.000 claims description 146
- 239000004065 semiconductor Substances 0.000 claims description 100
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 29
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 24
- 229910052732 germanium Inorganic materials 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 17
- 229910052796 boron Inorganic materials 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 15
- 230000005641 tunneling Effects 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 11
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 9
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 9
- 239000003989 dielectric material Substances 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 15
- 229910052707 ruthenium Inorganic materials 0.000 claims 15
- 210000003298 dental enamel Anatomy 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims 2
- 239000012528 membrane Substances 0.000 claims 1
- 238000010276 construction Methods 0.000 description 73
- 229910004298 SiO 2 Inorganic materials 0.000 description 27
- 229910000420 cerium oxide Inorganic materials 0.000 description 15
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 15
- 239000000758 substrate Substances 0.000 description 14
- 230000015654 memory Effects 0.000 description 12
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 8
- 239000010409 thin film Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 2
- 238000007865 diluting Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229940119177 germanium dioxide Drugs 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 125000005577 anthracene group Chemical group 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- AJXBBNUQVRZRCZ-UHFFFAOYSA-N azanylidyneyttrium Chemical compound [Y]#N AJXBBNUQVRZRCZ-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
非揮發性半導體記憶體(NVSM)廣泛地用於諸多電子器件(諸如,個人數位助理(PDA)、膝上型電腦、行動電話及數位相機)中。此等記憶體中之某些記憶體具有電荷儲存電晶體(諸如,浮動閘極電晶體)陣列。
在隨附圖式之各圖中以實例方式而非限制方式圖解說明某些實施例。
根據本發明之各種實施例之一電荷儲存器件陣列可用作一記憶體器件(諸如,一「反及」(NAND)記憶體器件)中之一記憶體胞陣列。
圖1係根據本發明之各種實施例之一半導體構造100之一個三維視圖。出於簡潔及清晰之目的,在圖1至圖8通篇中,半導體構造100中之層及區域將藉由相同元件符號來識別。包括薄膜電晶體(TFT)之一電荷儲存器件陣列欲形成於半導體構造100中,如本文中下文將闡述。根據本發明之各種實施例,半導體構造100包括記憶體胞之NAND串之一陣列。
半導體構造100包含一半導體材料(諸如,未經摻雜之多晶矽110)與一電介質120之交替層。每一電介質層120處於未經摻雜之多晶矽層110中之兩者之間且與未經摻雜之多晶矽層110中之該兩者接觸。根據本發明之各種實施例,電介質120可包括(舉例而言)二氧化矽(SiO2)、氧氮化物或
氮化氧化物(nitrided oxide)。一硬遮罩(未展示)可形成於半導體構造100之頂部處之未經摻雜之多晶矽層110中之一者上。根據本發明之各種實施例,該硬遮罩可係(舉例而言)二氧化矽(SiO2)、氮化矽(Si3N4)或多晶矽。圖1中展示三個未經摻雜之多晶矽層110及兩個電介質層120,且根據本發明之各種實施例,半導體構造100可包含(舉例而言)與電介質層120交替地形成之8個、16個、24個、32個、40個、48個或48個以上未經摻雜之多晶矽層110。根據本發明之各種實施例,p型或n型多晶矽可替代未經摻雜之多晶矽110用於半導體構造100中。
圖2係根據本發明之各種實施例之半導體構造100之一個三維視圖。開口(諸如,孔220)係穿過未經摻雜之多晶矽層110及電介質層120而蝕刻至半導體構造100中。根據本發明之各種實施例,可(諸如)藉由使用一單個乾式蝕刻(例如,一反應性離子蝕刻)而穿過半導體構造100圖案化並蝕刻孔220。
圖3係根據本發明之各種實施例之半導體構造100之一個三維視圖。半導體構造100接收一p型摻雜劑,諸如,硼。舉例而言,硼可藉助電漿輔助沈積(PLAD)來植入。藉由孔220曝露之未經摻雜之多晶矽110之部分透過孔220接收硼以產生環繞孔220之p+型多晶矽環306。p+型多晶矽環306係由硼未到達之未經摻雜之多晶矽110之部分環繞。硬遮罩(未展示)實質上防止硼到達該硬遮罩下方之半導體構造100。根據本發明之各種實施例,半導體構造100可摻雜有
除硼之外的一p型摻雜劑。
藉由孔220曝露之接收硼之未經摻雜之多晶矽110之部分可不為環。因此,根據本發明之各種實施例,該等部分可僅部分地環繞每一孔220。
另一選擇係,一p型多晶矽可在孔220中形成(例如,沈積)為插塞以使得一p型摻雜劑(諸如,硼)能夠自該p型多晶矽擴散至毗鄰於孔220之未經摻雜之多晶矽110中。一旦已形成p+型多晶矽環306,便自孔220選擇性地移除該等p型多晶矽插塞。根據本發明之各種實施例,p+型多晶矽環306亦可藉由氣相摻雜或固相摻雜來形成。根據本發明之各種實施例,可將P+型多晶矽環306摻雜成n型或保持未經摻雜,惟以不同於欲被選擇性地蝕刻之剩餘多晶矽之方式摻雜多晶矽環306。
圖4係根據本發明之各種實施例之半導體構造100之一個三維視圖。一穿隧電介質428形成於孔220內部電介質120及p+型多晶矽環306上方。穿隧電介質428可係(舉例而言)二氧化矽(SiO2)或氮化矽(Si3N4)且可經沈積或生長而成。一薄矽膜442形成(例如,沈積)於孔220內部穿隧電介質428上。薄矽膜442具有介於大約3奈米至大約15奈米之範圍中之一厚度及介於大約30奈米至大約100奈米之範圍中之一外尺寸(在圖4中,係一直徑)。薄矽膜442可用作用於包含p+型多晶矽環306之TFT之一通道。
圖5係根據本發明之各種實施例之半導體構造100之一個三維視圖。一垂直槽560可經蝕刻穿過未經摻雜之多晶矽
層110及電介質層120且在孔220之間以分割半導體構造100。根據本發明之各種實施例,可(諸如)藉由使用一單個乾式蝕刻(例如,一反應性離子蝕刻)來圖案化並蝕刻垂直槽560。
圖6係根據本發明之各種實施例之半導體構造100之一個三維視圖。藉由一蝕刻移除未經摻雜之多晶矽110之部分(例如,至少實質上所有未經摻雜之多晶矽110)以留下p+型多晶矽環306及電介質層120。可藉由(舉例而言)氫氧化四甲銨(TMAH)蝕刻選擇性地移除未經摻雜之多晶矽110。在TMAH蝕刻期間,保持先前所闡述之硬遮罩(未展示)。P+型多晶矽環306可係約10奈米至15奈米厚且可在半導體構造100中用作電荷儲存結構,諸如,浮動閘極。可藉由移除電介質120之部分之一濕式蝕刻來加寬原來由未經摻雜之多晶矽110佔據之處於電介質層120之間的空隙670。可相對於p+型多晶矽環306藉由濕式蝕刻底切電介質120,以使得p+型多晶矽環306以一懸垂方式自電介質120突出。
圖7係根據本發明之各種實施例之半導體構造100之一個三維視圖。處於電介質120之間的經加寬空隙670可容納一第一閘極間電介質(IGD),諸如,圍繞p+型多晶矽306環形成之一第一多晶矽間電介質(IPD)層。可藉由(舉例而言)稀釋氫氟酸或氫氧化銨來蝕刻電介質120。可將P+型多晶矽環306曝露至氧以形成二氧化矽(SiO2)710作為第一IPD層。二氧化矽(SiO2)710可選擇性地生長於p+型多晶矽環306上直至p+型多晶矽306環與電介質120之間的一邊緣。
圖8係根據本發明之各種實施例之半導體構造100之一個三維視圖。氮化矽(Si3N4)820可沈積於包含二氧化矽(SiO2)710及電介質120之半導體構造100上。二氧化矽(SiO2)824可在空隙670中沈積於氮化矽(Si3N4)820上。二氧化矽(SiO2)710及824以及氮化矽(Si3N4)820一起構成p+型多晶矽環306與字線840之間的一個氧化物-氮化物-氧化物(SiO2Si3N4SiO2或「ONO」)IPD。該IPD可替代地包括氧化鋯(ZrOx)、氧化鉿(HfOx)、氧化鋁(AlOx)或氧化鈦(TiOx)。關於字線840,金屬可形成(例如,沈積)於半導體構造100上且經選擇性地蝕刻以在電介質層120之間形成金屬字線840以便填充空隙670以使得金屬字線840實質上彼此隔離。根據本發明之各種實施例,該金屬可藉由一反應性離子蝕刻來蝕刻。根據本發明之各種實施例,該金屬可係(舉例而言)氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或鎢(W)。二氧化矽(SiO2)710及824、氮化矽(Si3N4)820以及金屬字線840至少部分地環繞(例如,在某些情形下,完全環繞)p+型多晶矽環306。
根據本發明之各種實施例,半導體構造100中之每一薄矽膜442可用於為一NAND串870中之複數個電荷儲存電晶體860提供一通道。電荷儲存電晶體860亦可稱為記憶體胞。每一電荷儲存電晶體860包含藉由穿隧電介質428而與薄矽膜442分離之一電荷儲存結構的p+型多晶矽環306中之一者之至少一部分。每一電荷儲存電晶體860亦包含藉由IPD(例如,二氧化矽(SiO2)710及824以及氮化矽
(Si3N4)820)而與p+型多晶矽環306分離之字線840中之一者之至少一部分。存取器件(未展示)形成於半導體構造100下方以透過薄矽膜442存取該等電荷儲存電晶體。將每一NAND串展示為包含三個電荷儲存電晶體860,且圖8中展示構成電荷儲存電晶體860或記憶體胞之一陣列之四個NAND串870。根據本發明之各種實施例,每一NAND串870可包含更多個電荷儲存電晶體,且半導體構造100可包含更多個NAND串。
圖9係根據本發明之各種實施例之一半導體構造900之一個三維視圖。出於簡潔及清晰之目的,在圖9至圖19通篇中,半導體構造900中之層及區域將藉由相同元件符號來識別。包括TFT之一電荷儲存器件陣列欲形成於半導體構造900中,如本文中下文將闡述。根據本發明之各種實施例,半導體構造900包括記憶體胞之NAND串之一陣列。
多晶矽可經沈積以形成半導體構造900之一多晶矽基底904。將凹部圖案化並蝕刻至多晶矽基底904中,且細長氮化矽(Si3N4)906部分可沈積於該等凹部中。多晶矽基底904亦可經蝕刻以清除其周邊之多晶矽。根據本發明之各種實施例,多晶矽基底904可藉助一反應性離子蝕刻來蝕刻。細長氮化矽(Si3N4)906部分可經受在多晶矽基底904處停止之平坦化,諸如,化學機械平坦化(CMP)。
可以其他方式形成多晶矽基底904及氮化矽(Si3N4)906。舉例而言,可沈積多晶矽且然後可沈積氮化矽(Si3N4)。可圖案化並蝕刻氮化矽(Si3N4),該蝕刻在多晶矽上停止。然
後可沈積厚多晶矽並使其經受在氮化矽(Si3N4)上停止之平坦化(諸如,CMP)以使多晶矽平坦。可藉由在多晶矽基底904上氮化矽(Si3N4)906上方形成額外多晶矽而環繞氮化矽(Si3N4)906。根據本發明之各種實施例,可使用一蝕刻(諸如,一反應性離子蝕刻)來移除多晶矽基底904之周邊上之多晶矽(例如,連同字線金屬)。
圖10係根據本發明之各種實施例之半導體構造900之一個三維視圖。一半導體材料(諸如,未經摻雜之多晶矽1010)與一電介質1008之交替層形成於多晶矽基底904上以使得每一電介質1008處於未經摻雜之多晶矽層1010中之兩者之間或多晶矽基底904與未經摻雜之多晶矽1010之間,且與未經摻雜之多晶矽層1010中之該兩者或多晶矽基底904及未經摻雜之多晶矽1010接觸。根據本發明之各種實施例,電介質1008可包括(舉例而言)二氧化矽(SiO2)、氧氮化物或氮化氧化物。一硬遮罩1030形成於半導體構造900之頂部處之未經摻雜之多晶矽層1010中之一者上。硬遮罩1030可係(舉例而言)二氧化矽(SiO2)、氮化矽(Si3N4)或多晶矽。圖10中展示三個未經摻雜之多晶矽層1010及三個電介質層1008,然而,根據本發明之各種實施例,半導體構造900可包含(舉例而言)與電介質1008交替地形成之8個、16個、24個、32個、40個、48個或48個以上未經摻雜之多晶矽層1010。根據本發明之各種實施例,p型或n型多晶矽可替代未經摻雜之多晶矽1010用於半導體構造100中。
圖11係根據本發明之各種實施例之半導體構造900之一個三維視圖。在半導體構造900中圖案化並蝕刻開口(諸如,孔1140)。孔1140經圖案化以與細長氮化矽906部分之端部對準。孔1140經蝕刻穿過硬遮罩1030、未經摻雜之多晶矽層1010及電介質層1008,在細長氮化矽906部分中停止。孔1140中之兩者延伸至細長氮化矽906部分中之每一者之各別端部中,在任一端部處一個孔1140,以使得每一細長氮化矽906部分延伸於孔1140中之兩者之間。雖然將孔1140圖解說明為實質上方形,但其可係實質上圓形或實質上橢圓形或可具有任何適合幾何形狀。根據本發明之各種實施例,(諸如)藉由使用一單個乾式蝕刻(例如,一反應性離子蝕刻)來蝕刻孔1140。
圖12係根據本發明之各種實施例之半導體構造900之一個三維視圖。半導體構造900接收一p型摻雜劑,諸如,硼。舉例而言,硼可藉助PLAD來植入。藉由孔1140曝露之未經摻雜之多晶矽1010之部分接收硼以產生圍繞孔1140之p+型多晶矽環1270。p+型多晶矽環1270係由硼未到達之未經摻雜之多晶矽1010之部分環繞。p+型多晶矽環1270具有一方形形狀,此乃因孔1140係方形的。因此,環1270通常將具有與孔1140之幾何形狀一致之一形狀。硬遮罩1030實質上防止硼到達硬遮罩1030下方之半導體構造900。根據本發明之各種實施例,半導體構造900可摻雜有除硼之外的一p型摻雜劑。
另一選擇係,一p型多晶矽可在孔1140中形成(例如,沈
積)為插塞以使得一p型摻雜劑(諸如,硼)能夠自該p型多晶矽擴散至毗鄰於孔1140之未經摻雜之多晶矽1010中。一旦已形成p+型多晶矽環1270,便自孔1140選擇性地移除該等p型多晶矽插塞。根據本發明之各種實施例,p+型多晶矽環1270亦可藉由氣相摻雜或固相摻雜來形成。根據本發明之各種實施例,可將p+型多晶矽環1270摻雜成n型或保持未經摻雜,惟以不同於欲選擇性地蝕刻之剩餘多晶矽之方式摻雜多晶矽環1270。
根據本發明之各種實施例,藉由孔1140曝露之接收硼之未經摻雜之多晶矽1010之部分可係不為環之p+型多晶矽之部分,以使得該等部分僅部分地環繞每一孔1140。
圖13係根據本發明之各種實施例之半導體構造900之一個三維視圖。藉助一濕式硝酸鹽條帶(WNS)透過孔1140選擇性地移除細長氮化矽906部分。細長氮化矽906部分之移除在多晶矽基底904中留下細長腔。每一細長腔向孔1140中之兩者敞開,在每一端部處一個孔1140,以在半導體構造900中形成U形管1380。每一U形管1380係一開口,該開口包含:穿過硬遮罩1030、未經摻雜之多晶矽層1010及電介質層1008之孔1140中之一者;由被移除之細長氮化矽906部分留下之腔;及穿過未經摻雜之多晶矽層1010及電介質層1008以及硬遮罩1030之孔1140中之一第二者。雖然圖13中展示六個U形管1380,但根據本發明之各種實施例更大或更小數目個U形管1380可形成於半導體構造900中。
圖14係根據本發明之各種實施例之半導體構造900之一
個三維視圖。一穿隧電介質1492形成於U形管1380內部硬遮罩1030、電介質1008及p+型多晶矽環1270上。根據本發明之各種實施例,穿隧電介質1492可係(舉例而言)二氧化矽(SiO2)或氮化矽(Si3N4)且可經沈積或生長而成。一薄矽膜形成(例如,沈積)於U形管1380內部穿隧電介質1492上。每一U形管1380中之薄矽膜提供一U形管通道1496。該薄矽膜具有介於大約3奈米至大約15奈米之範圍中之一厚度,以使得U形管通道1496具有介於大約3奈米至大約15奈米之範圍中之一厚度及介於30奈米至100奈米之範圍中之一外尺寸。半導體構造900經受平坦化(諸如,CMP)以移除U形管通道1496之多餘部分。
圖15係根據本發明之各種實施例之半導體構造900之一個三維視圖。一個二氧化矽(SiO2)遮罩1516形成於半導體構造900上以覆蓋硬遮罩1030及U形管通道1496。舉例而言,半導體構造900可在一高溫下曝露至原矽酸四乙酯(TEOS)以形成二氧化矽(SiO2)遮罩1516。
圖16係根據本發明之各種實施例之半導體構造900之一個三維視圖。垂直槽1628係蝕刻於半導體構造900中穿過遮罩1516、硬遮罩1030及未經摻雜之多晶矽層1010及電介質層1008。垂直槽1628係蝕刻於U形管通道1496之孔1140之間且結束於恰好在多晶矽基底904上方之電介質1008中以使得U形管通道1496不被垂直槽1628破壞。將每一垂直槽1628展示為蝕刻於三個所繪示U形管通道1496之孔1140之間,然而,根據本發明之各種實施例,每一垂直槽1628
可蝕刻於半導體構造900中之一或多個U形管通道之孔之間。根據本發明之各種實施例,(諸如)藉由使用一單個乾式蝕刻(例如,一反應性離子蝕刻)來穿過半導體構造900圖案化並蝕刻垂直槽1628。
圖17係根據本發明之各種實施例之半導體構造900之一個三維視圖。藉由一蝕刻移除未經摻雜之多晶矽1010之至少實質上所有剩餘部分以留下p+型多晶矽環1270及電介質層1008。根據本發明之各種實施例,可藉由TMAH蝕刻來選擇性地移除未經摻雜之多晶矽1010之部分。在TMAH蝕刻期間,保持硬遮罩1030及遮罩1516。p+型多晶矽環1270可係約10奈米至15奈米厚且可在半導體構造900中用作電荷儲存結構,諸如,浮動閘極。根據本發明之各種實施例,欲成為電荷儲存結構之p+型多晶矽之部分可不係完整環;因此,可形成部分環以部分地環繞每一孔1140。可藉由移除電介質1008之部分之一濕式蝕刻來加寬原來由未經摻雜之多晶矽1010佔據之處於電介質層1008之間的空隙1732。可相對於p+型多晶矽環1270藉由濕式蝕刻底切電介質1008,以使得p+型多晶矽環1270自電介質1008突出。
圖18係根據本發明之各種實施例之半導體構造900之一個三維視圖。處於電介質1008之間的經加寬空隙1732(圖17中所展示)可容納IPD。電介質1008可藉由(舉例而言)稀釋氫氟酸或氫氧化銨來蝕刻。p+型多晶矽環1270可曝露至氧以形成二氧化矽(SiO2)1838。二氧化矽(SiO2)1838可生長於p+型多晶矽環1270上直至p+型多晶矽環1270與電介質
120之間的一邊緣。氮化矽(Si3N4)1842可沈積於半導體構造900上,包含藉由垂直槽1628曝露之二氧化矽(SiO2)1838、遮罩1516、硬遮罩1030及電介質1008。然後二氧化矽(SiO2)1846可在空隙1732中沈積於氮化矽(Si3N4)1842上。二氧化矽(SiO2)1838及1846以及氮化矽(Si3N4)1842一起構成p+型多晶矽環1270與字線1852之間的一ONO IPD。關於字線1852,金屬可形成(例如,沈積)於由包含二氧化矽(SiO2)1838及1846以及氮化矽(Si3N4)1842之IPD覆蓋之電介質1008之間以填充空隙1732。根據本發明之各種實施例,該金屬可係(舉例而言)氮化鈦(TiN)、鉭(Ta)或鎢(W)。該金屬經選擇性地蝕刻以在空隙1732中形成實質上彼此隔離之金屬字線1852。該金屬可藉由(舉例而言)一反應性離子蝕刻來蝕刻。二氧化矽(SiO2)1838及1846、氮化矽(Si3N4)1842及金屬字線1852至少部分地環繞(例如,在某些情形下,完全環繞)p+型多晶矽環1270。
圖19係根據本發明之各種實施例之半導體構造900之一個三維視圖。垂直槽1628填充有一電介質1966,諸如(舉例而言),二氧化矽(SiO2)。U形管通道1496中之內部空間可包括一氣隙或可填充有多晶矽或一電介質,諸如(舉例而言),二氧化矽(SiO2)。
根據本發明之各種實施例,半導體構造900中之每一U形管通道1496可為一NAND串1990中之複數個電荷儲存電晶體1980提供一通道。電荷儲存電晶體1980亦可稱為記憶體胞。每一電荷儲存電晶體1980包含藉由穿隧電介質1492而
與U形管通道1496分離之一電荷儲存結構的p+型多晶矽環1270中之一者之至少一部分U形。每一電荷儲存電晶體1980亦包含藉由IPD(例如,二氧化矽(SiO2)1838及1846以及氮化矽(Si3N4)1842)而與p+型多晶矽環1270分離之金屬字線1852中之一者之至少一部分。存取器件(未展示)形成於半導體構造900下方以透過U形管通道1496存取通道及電荷儲存電晶體1980。將每一NAND串1990展示為包含三個電荷儲存電晶體1980,且圖19中展示構成電荷儲存電晶體1980或記憶體胞之一陣列之六個NAND串1990。根據本發明之各種實施例,每一NAND串可包含更多個電荷儲存電晶體,且半導體構造900可包含更多個NAND串。
圖20係根據本發明之各種實施例之一種方法2000之一流程圖。在方塊2010中,方法2000開始。在方塊2020中,在包括多晶矽與一第一電介質之交替層之一半導體構造中形成一開口。在方塊2030中,透過該開口將一p型摻雜劑添加至藉由該開口曝露之多晶矽之部分。在方塊2040中,移除未接收p型摻雜劑之至少實質上所有剩餘多晶矽以留下包括p型多晶矽之複數個電荷儲存結構,每一電荷儲存結構在其層中至少部分地環繞該開口。在方塊2050中,在每一電荷儲存結構之一第一表面上(例如,在電荷儲存結構與開口之間)形成一第二電介質。在方塊2060中,在每一電荷儲存結構之一第二表面上(例如,在多晶矽被移除之處)形成一第三電介質。在方塊2070中,在每一第三電介質上形成一金屬閘極。在方塊2080中,方法2000結束。各
種實施例可具有比圖20中所展示之活動更多或更少之活動。在某些實施例中,可重複及/或以連續或並行方式執行該等活動。
製作多層式半導體器件可係昂貴的,此乃因難以在多個半導體材料層中形成特徵。發明人已發現,可藉由在一半導體構造中形成一開口來應對上文所述之該等挑戰中之至少某些挑戰以及其他挑戰,其中該半導體構造包括(舉例而言)多晶矽與一電介質之交替層。可將摻雜劑添加至藉由該開口曝露之多晶矽且移除未接收該摻雜劑之至少實質上所有多晶矽以留下圍繞該開口之經摻雜多晶矽之部分。圍繞經摻雜多晶矽之該等部分中之每一者形成電介質。經摻雜之多晶矽之該等部分因此實質上彼此電隔離以使得涉及一者之操作實質上不影響經摻雜之多晶矽之相鄰部分。舉例而言,當經摻雜之多晶矽之該等部分中之一者被程式化或讀取為一電荷儲存結構時,作為一結果,相鄰部分之電位實質上未改變。
圖21係圖解說明根據本發明之各種實施例之一系統2100之一圖示。系統2100可包含一處理器2110、一記憶體器件2120、一記憶體控制器2130、一圖形控制器2140、一輸入與輸出(I/O)控制器2150、一顯示器2152、一鍵盤2154、一指標器件2156及一周邊器件2158。一匯流排2160將所有此等器件耦合在一起。一時脈產生器2170耦合至匯流排2160以透過匯流排2160將一時脈信號提供至系統2100之該等器件中之至少一者。時脈產生器2170可包含在一電路板(諸
如,一母板)中之一振盪器。系統2100中所展示之兩個或兩個以上器件可形成於一單個積體電路晶片中。根據本發明之各種實施例,記憶體器件2120可包括(諸如)本文中所闡述及各圖中所展示之記憶體胞之NAND串870之一陣列及/或記憶體胞之NAND串1990之一陣列的器件。匯流排2160可係一電路板上之互連跡線或可係一或多個電纜。匯流排2160可藉由無線方式(諸如,藉由電磁輻射,舉例而言,無線電波)耦合系統2100之該等器件。耦合至I/O控制器2150之周邊器件2158可係一印表機、一光學器件(諸如,一CD-ROM及一DVD讀取器及寫入器)、一磁性器件讀取器及寫入器(諸如,一軟磁碟機)或一音訊器件(諸如,一麥克風)。
圖21所表示之系統2100可包含:電腦(例如,桌上型電腦、膝上型電腦、手持式電腦、伺服器、Web器具、路由器等)、無線通信器件(例如,蜂巢式電話、無繩電話、傳呼機、個人數位助理等)、電腦相關周邊設備(例如,印表機、掃描器、監視器等)、娛樂器件(例如,電視、無線電設備、立體音響設備、磁帶及光碟播放器、錄影機、攝錄影機、數位相機、MP3(運動圖像專家組,音訊層3)播放器、視訊遊戲、表等)及諸如此類。
本文中所闡述之電路或系統中之任一者可稱作一模組。根據各種實施例,一模組可包括一電路及/或韌體。
本發明已闡述製作電荷儲存電晶體之實例性結構及方法。儘管已闡述特定實施例,但將顯而易見,可對此等實
施例做出各種修改及改變。因此,應將說明書及圖式視為具有一說明性意義而非一限制性意義。
提供本發明之摘要以符合37 C.F.R.§ 1.72(b),其需要允許讀者快速斷定技術性發明之性質之一摘要。該摘要係在其將不用於闡釋或限制申請專利範圍之理解下提交的。另外,在前述實施方式中,可看到,出於簡化本發明之目的,將各種特徵一起組合於一單個實施例中。不應將本發明之此方法闡釋為限制申請專利範圍。因此,將以下申請專利範圍併入至實施方式中,其中每一請求項獨立地作為一單獨實施例。
100‧‧‧半導體構造
110‧‧‧未經摻雜之多晶矽/未經摻雜之多晶矽層
120‧‧‧電介質/電介質層
220‧‧‧孔
306‧‧‧p+型多晶矽環
428‧‧‧穿隧電介質
442‧‧‧薄矽膜
560‧‧‧垂直槽
670‧‧‧空隙
710‧‧‧二氧化矽
820‧‧‧氮化矽
824‧‧‧二氧化矽
840‧‧‧金屬字線
860‧‧‧電荷儲存電晶體
870‧‧‧「反及」串
900‧‧‧半導體構造
904‧‧‧多晶矽基底
906‧‧‧氮化矽
1008‧‧‧電介質/電介質層
1010‧‧‧未經摻雜之多晶矽/未經摻雜之多晶矽層
1030‧‧‧硬遮罩
1140‧‧‧孔
1270‧‧‧p+型多晶矽環
1380‧‧‧U形管
1492‧‧‧穿隧電介質
1496‧‧‧U形管通道
1516‧‧‧二氧化矽遮罩
1628‧‧‧垂直槽
1732‧‧‧空隙
1838‧‧‧二氧化矽
1842‧‧‧氮化矽
1846‧‧‧二氧化矽
1852‧‧‧金屬字線
1966‧‧‧電介質
1980‧‧‧電荷儲存電晶體
1990‧‧‧「反及」串
2100‧‧‧系統
2110‧‧‧處理器
2120‧‧‧記憶體器件
2130‧‧‧記憶體控制器
2140‧‧‧圖形控制器
2150‧‧‧輸入與輸出控制器
2152‧‧‧顯示器
5154‧‧‧鍵盤
2156‧‧‧指標器件
2158‧‧‧周邊器件
2160‧‧‧匯流排
2170‧‧‧時脈產生器
圖1係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖2係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖3係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖4係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖5係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖6係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖7係根據本發明之各種實施例之一半導體構造之一個
三維視圖;圖8係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖9係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖10係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖11係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖12係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖13係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖14係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖15係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖16係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖17係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖18係根據本發明之各種實施例之一半導體構造之一個三維視圖;圖19係根據本發明之各種實施例之一半導體構造之一個
三維視圖;圖20係根據本發明之各種實施例之方法之一流程圖;且圖21係圖解說明根據本發明之各種實施例之一系統之一圖示。
100‧‧‧半導體構造
110‧‧‧未經摻雜之多晶矽/未經摻雜之多晶矽層
120‧‧‧電介質/電介質層
Claims (38)
- 一種電荷儲存方法,其包括:在一半導體材料層及一電介質層中形成一開口;處理藉由該開口曝露之該半導體材料層之一部分以使得以不同於該層中之剩餘半導體材料之方式摻雜該部分;移除該層之至少實質上所有該剩餘半導體材料,其中該半導體材料層之該以不同方式摻雜之部分包括一電荷儲存結構;在該電荷儲存結構之一第一表面上形成一穿隧電介質;及在該電荷儲存結構之一第二表面上形成一閘極間電介質。
- 如請求項1之方法,其中在一半導體材料層及一電介質層中形成一開口包括在多晶矽與電介質之交替層中形成該開口,且其中處理藉由該開口曝露之該多晶矽層之一部分以使得以不同於該層中之該剩餘多晶矽之方式摻雜該部分包括處理藉由該開口曝露之該等多晶矽層中之每一者之一各別部分以使得以不同於該等層之該剩餘多晶矽之方式摻雜該等各別部分。
- 如請求項1之方法,其中處理藉由該開口曝露之該半導體材料層之一部分以使得以不同於該層中之該剩餘半導體材料之方式摻雜該部分包括:摻雜一多晶矽層之一部分,其中該層之該剩餘多晶矽包括未經摻雜之多晶矽。
- 如請求項3之方法,其中摻雜該多晶矽層之該部分包括:透過該開口將一p型摻雜劑添加至藉由該開口曝露之多晶矽之該部分。
- 如請求項3之方法,其中摻雜該多晶矽層之該部分包括:在該開口中形成一p型多晶矽插塞及使一p型摻雜劑自該插塞擴散至該部分中。
- 如請求項3之方法,其中摻雜該多晶矽層之該部分包括植入硼。
- 如請求項1之方法,其中形成一開口包括形成一孔。
- 一種電荷儲存方法,其包括:在一半導體構造中形成一開口,該半導體構造包括未經摻雜之多晶矽與一電介質之交替層;將摻雜劑添加至至少部分地環繞該開口之該等未經摻雜之多晶矽層之各別部分;移除該等層之實質上所有剩餘未經摻雜之多晶矽;及在經摻雜之多晶矽之該等部分中之每一者之相對表面上形成電介質。
- 如請求項8之方法,其進一步包括在該開口中形成一矽膜。
- 如請求項8之方法,其進一步包括形成毗鄰於經摻雜之多晶矽之該等部分中之每一者之一導電閘極。
- 如請求項8之方法,其中添加該摻雜劑包括透過該開口將p型摻雜劑添加至藉由該開口曝露之多晶矽之部分。
- 如請求項8之方法,其中移除該等層之實質上所有剩餘 未經摻雜之多晶矽包括留下至少部分地環繞該開口的複數個電荷儲存結構。
- 如請求項12之方法,其中留下複數個電荷儲存結構包括留下複數個p型多晶矽電荷儲存結構。
- 如請求項8之方法,進一步包括形成毗鄰於經摻雜之多晶矽之該等部分中之每一者之一金屬閘極。
- 一種電荷儲存裝置,其包括:一矽膜以為一反及(NAND)串中之複數個電荷儲存電晶體提供一通道;一第一電荷儲存結構,其在一第一位置處至少部分地環繞該矽膜;一第二電荷儲存結構,其在一第二位置處至少部分地環繞該矽膜;及一電介質,其處於該第一電荷儲存結構與該矽膜之間且處於該第二電荷儲存結構與該矽膜之間,其中該等電荷儲存電晶體中之一第一者包括該第一電荷儲存結構及一第一字線之至少一部分,且其中該等電荷儲存電晶體中之一第二者包括該第二電荷儲存結構及一第二字線之至少一部分。
- 如請求項15之裝置,其中該矽膜係大約3奈米至大約15奈米厚。
- 如請求項15之裝置,其中該第一字線可導電且至少部分地環繞該第一電荷儲存結構。
- 如請求項17之裝置,其進一步包括處於該第一電荷儲存 結構與該第一字線之間的一閘極間電介質(IGD)。
- 如請求項15之裝置,其中該電介質包括一穿隧電介質。
- 如請求項15之裝置,其中該矽膜之一剖面係U形的。
- 如請求項19之裝置,其進一步包括處於該第一電荷儲存結構與該第二電荷儲存結構之間的一隔離電介質。
- 如請求項15之裝置,其中該第一電荷儲存結構包括在該第一位置處圍繞該矽膜之一經摻雜之多晶矽環。
- 如請求項22之裝置,其中該電介質包括一穿隧電介質,且進一步包括至少部分地環繞該經摻雜之多晶矽環之一閘極間電介質(IGD)。
- 如請求項23之裝置,其中該第一字線至少部分地環繞該經摻雜之多晶矽環,其中該IGD處於該第一字線與該經摻雜之多晶矽環之間。
- 一種電荷儲存裝置,其包括:一矽膜,其延伸穿過一對第一電介質中之一開口以為一反及(NAND)串中之複數個電荷儲存電晶體提供一通道;一多晶矽閘極,其在該對第一電介質之間至少部分地環繞該矽膜;一第二電介質,其處於該多晶矽閘極與該矽膜之間;及一第三電介質,其處於該多晶矽閘極與一控制閘極之間。
- 如請求項25之裝置,其中:該對第一電介質包括一對二氧化矽層; 該第二電介質包括二氧化矽或氮化矽;且該第三電介質包括二氧化矽、氮化矽及二氧化矽。
- 如請求項25之裝置,其中該矽膜係大約3奈米至大約15奈米厚。
- 如請求項25之裝置,其中該多晶矽閘極包括p型多晶矽、n型多晶矽或未經摻雜之多晶矽。
- 一種電荷儲存裝置,其包括:一矽膜以為一反及(NAND)串中之複數個電荷儲存電晶體提供一通道;一第一電荷儲存結構,其在一第一位置處至少部分地環繞該矽膜;一第二電荷儲存結構,其在一第二位置處至少部分地環繞該矽膜;一第一電介質,其位於該第一電荷儲存結構及該第二電荷儲存結構之間;及一第二電介質,其位於該第一電荷儲存結構及該矽膜之間,且位於該第二電荷儲存結構及該矽膜之間,其中該等電荷儲存電晶體中之一第一者包括該第一電荷儲存結構及一第一字線之至少一部分,且其中該等電荷儲存電晶體中之一第二者包括該第二電荷儲存結構及一第二字線之至少一部分。
- 如請求項29之裝置,其中該第一電介質包括一隔離電介質。
- 如請求項29之裝置,其中該矽膜係大約3奈米至大約15 奈米厚。
- 如請求項29之裝置,其中該第二電介質包括一穿隧電介質。
- 如請求項29之裝置,其中該第一電荷儲存結構包括在該第一位置處圍繞該矽膜之一經摻雜之多晶矽環。
- 一種電荷儲存裝置,其包括:一矽膜,其小於大約15奈米厚以為一反及(NAND)串中之複數個電荷儲存電晶體提供一通道;一第一電荷儲存結構,其在一第一位置處至少部分地環繞該矽膜;一第二電荷儲存結構,其在一第二位置處至少部分地環繞該矽膜;及一電介質,其位於該第一電荷儲存結構及該矽膜之間,且位於該第二電荷儲存結構及該矽膜之間。
- 如請求項34之裝置,其中:該矽膜係大約3奈米至大約15奈米厚;該等電荷儲存電晶體中之一第一者包括該第一電荷儲存結構及一第一字線之至少一部分;及該等電荷儲存電晶體中之一第二者包括該第二電荷儲存結構及一第二字線之至少一部分。
- 如請求項34之裝置,其中該第一電荷儲存結構包括在該第一位置處圍繞該矽膜之一經摻雜之多晶矽環。
- 如請求項36之裝置,其中該電介質包括一穿隧電介質,且進一步包括至少部分地環繞該經摻雜之多晶矽環之一 閘極間電介質(IGD)。
- 如請求項37之裝置,其進一步包括至少部分地環繞該經摻雜之多晶矽環之一導電字線,其中該IGD處於該字線與該經摻雜之多晶矽環之間。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/035,700 US8759895B2 (en) | 2011-02-25 | 2011-02-25 | Semiconductor charge storage apparatus and methods |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201246396A TW201246396A (en) | 2012-11-16 |
TWI515802B true TWI515802B (zh) | 2016-01-01 |
Family
ID=46718390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101105342A TWI515802B (zh) | 2011-02-25 | 2012-02-17 | 電荷儲存裝置、系統及方法 |
Country Status (7)
Country | Link |
---|---|
US (6) | US8759895B2 (zh) |
EP (1) | EP2678882B1 (zh) |
JP (1) | JP5877210B2 (zh) |
KR (1) | KR101571944B1 (zh) |
CN (1) | CN103403861B (zh) |
TW (1) | TWI515802B (zh) |
WO (1) | WO2012116207A2 (zh) |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8803214B2 (en) | 2010-06-28 | 2014-08-12 | Micron Technology, Inc. | Three dimensional memory and methods of forming the same |
US9397093B2 (en) | 2013-02-08 | 2016-07-19 | Sandisk Technologies Inc. | Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof |
US8759895B2 (en) | 2011-02-25 | 2014-06-24 | Micron Technology, Inc. | Semiconductor charge storage apparatus and methods |
KR101794017B1 (ko) * | 2011-05-12 | 2017-11-06 | 삼성전자 주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
US9178077B2 (en) | 2012-11-13 | 2015-11-03 | Micron Technology, Inc. | Semiconductor constructions |
US8778762B2 (en) | 2012-12-07 | 2014-07-15 | Micron Technology, Inc. | Methods of forming vertically-stacked structures, and methods of forming vertically-stacked memory cells |
US9105737B2 (en) | 2013-01-07 | 2015-08-11 | Micron Technology, Inc. | Semiconductor constructions |
US8853769B2 (en) | 2013-01-10 | 2014-10-07 | Micron Technology, Inc. | Transistors and semiconductor constructions |
US8946807B2 (en) * | 2013-01-24 | 2015-02-03 | Micron Technology, Inc. | 3D memory |
US9064970B2 (en) | 2013-03-15 | 2015-06-23 | Micron Technology, Inc. | Memory including blocking dielectric in etch stop tier |
US9184175B2 (en) | 2013-03-15 | 2015-11-10 | Micron Technology, Inc. | Floating gate memory cells in vertical memory |
US9276011B2 (en) | 2013-03-15 | 2016-03-01 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
US9159845B2 (en) | 2013-05-15 | 2015-10-13 | Micron Technology, Inc. | Charge-retaining transistor, array of memory cells, and methods of forming a charge-retaining transistor |
US9728584B2 (en) * | 2013-06-11 | 2017-08-08 | Micron Technology, Inc. | Three dimensional memory array with select device |
US9275909B2 (en) | 2013-08-12 | 2016-03-01 | Micron Technology, Inc. | Methods of fabricating semiconductor structures |
US9437604B2 (en) | 2013-11-01 | 2016-09-06 | Micron Technology, Inc. | Methods and apparatuses having strings of memory cells including a metal source |
US9136278B2 (en) | 2013-11-18 | 2015-09-15 | Micron Technology, Inc. | Methods of forming vertically-stacked memory cells |
US10141322B2 (en) | 2013-12-17 | 2018-11-27 | Intel Corporation | Metal floating gate composite 3D NAND memory devices and associated methods |
KR102128465B1 (ko) | 2014-01-03 | 2020-07-09 | 삼성전자주식회사 | 수직 구조의 비휘발성 메모리 소자 |
US20150194321A1 (en) * | 2014-01-09 | 2015-07-09 | Micron Technology, Inc. | Methods of Processing Polysilicon-Comprising Compositions |
US9171862B2 (en) * | 2014-01-24 | 2015-10-27 | Macronix International Co., Ltd. | Three-dimensional memory and method of forming the same |
CN104810326B (zh) * | 2014-01-28 | 2017-09-08 | 旺宏电子股份有限公司 | 三维存储器及其制造方法 |
CN103904035B (zh) * | 2014-03-05 | 2016-09-21 | 清华大学 | Tcat结构及其形成方法 |
CN103904034A (zh) * | 2014-03-05 | 2014-07-02 | 清华大学 | P-BiCS结构及其形成方法 |
US9917096B2 (en) * | 2014-09-10 | 2018-03-13 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
CN104269406B (zh) * | 2014-09-16 | 2017-04-19 | 华中科技大学 | 一种芯壳型纳米线三维nand闪存器件及其制备方法 |
US9741569B2 (en) * | 2014-12-16 | 2017-08-22 | Macronix International Co., Ltd. | Forming memory using doped oxide |
WO2016135849A1 (ja) * | 2015-02-24 | 2016-09-01 | 株式会社 東芝 | 半導体記憶装置及びその製造方法 |
WO2016139725A1 (ja) * | 2015-03-02 | 2016-09-09 | 株式会社 東芝 | 半導体記憶装置及びその製造方法 |
CN107534045B (zh) | 2015-03-17 | 2021-03-30 | 美光科技公司 | 替换控制栅极的方法及设备 |
US9608000B2 (en) | 2015-05-27 | 2017-03-28 | Micron Technology, Inc. | Devices and methods including an etch stop protection material |
WO2016194211A1 (ja) * | 2015-06-04 | 2016-12-08 | 株式会社 東芝 | 半導体記憶装置及びその製造方法 |
US9806089B2 (en) | 2015-09-21 | 2017-10-31 | Sandisk Technologies Llc | Method of making self-assembling floating gate electrodes for a three-dimensional memory device |
JP2017163044A (ja) | 2016-03-10 | 2017-09-14 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
KR102456494B1 (ko) * | 2016-03-29 | 2022-10-20 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
KR102626838B1 (ko) | 2016-06-20 | 2024-01-18 | 삼성전자주식회사 | 수직형 비휘발성 메모리 소자 및 그 제조방법 |
US9673216B1 (en) * | 2016-07-18 | 2017-06-06 | Sandisk Technologies Llc | Method of forming memory cell film |
US10559752B2 (en) * | 2016-12-05 | 2020-02-11 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US10707121B2 (en) * | 2016-12-31 | 2020-07-07 | Intel Corporatino | Solid state memory device, and manufacturing method thereof |
US10217755B2 (en) * | 2017-04-01 | 2019-02-26 | Intel Corporation | Flash memory cells, components, and methods |
US10141221B1 (en) * | 2017-07-18 | 2018-11-27 | Macronix International Co., Ltd. | Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same |
US11282845B2 (en) * | 2017-08-24 | 2022-03-22 | Micron Technology, Inc. | Semiconductor devices comprising carbon-doped silicon nitride and related methods |
US10777566B2 (en) * | 2017-11-10 | 2020-09-15 | Macronix International Co., Ltd. | 3D array arranged for memory and in-memory sum-of-products operations |
US10355014B1 (en) * | 2017-12-22 | 2019-07-16 | Micron Technology, Inc. | Assemblies having vertically-extending structures |
US10957392B2 (en) | 2018-01-17 | 2021-03-23 | Macronix International Co., Ltd. | 2D and 3D sum-of-products array for neuromorphic computing system |
US10719296B2 (en) | 2018-01-17 | 2020-07-21 | Macronix International Co., Ltd. | Sum-of-products accelerator array |
US11138497B2 (en) | 2018-07-17 | 2021-10-05 | Macronix International Co., Ltd | In-memory computing devices for neural networks |
CN112956030A (zh) | 2018-10-09 | 2021-06-11 | 美光科技公司 | 包含具有增加阈值电压的晶体管的半导体装置及其相关方法与系统 |
US11636325B2 (en) | 2018-10-24 | 2023-04-25 | Macronix International Co., Ltd. | In-memory data pooling for machine learning |
US11562229B2 (en) | 2018-11-30 | 2023-01-24 | Macronix International Co., Ltd. | Convolution accelerator using in-memory computation |
US11934480B2 (en) | 2018-12-18 | 2024-03-19 | Macronix International Co., Ltd. | NAND block architecture for in-memory multiply-and-accumulate operations |
US11119674B2 (en) | 2019-02-19 | 2021-09-14 | Macronix International Co., Ltd. | Memory devices and methods for operating the same |
US10783963B1 (en) | 2019-03-08 | 2020-09-22 | Macronix International Co., Ltd. | In-memory computation device with inter-page and intra-page data circuits |
US11132176B2 (en) | 2019-03-20 | 2021-09-28 | Macronix International Co., Ltd. | Non-volatile computing method in flash memory |
US10777576B1 (en) * | 2019-04-03 | 2020-09-15 | Micron Technology, Inc. | Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies |
US10910393B2 (en) | 2019-04-25 | 2021-02-02 | Macronix International Co., Ltd. | 3D NOR memory having vertical source and drain structures |
US11244954B2 (en) | 2019-08-22 | 2022-02-08 | Micron Technology, Inc. | Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies |
CN111063683B (zh) * | 2019-12-06 | 2022-08-30 | 中国科学院微电子研究所 | 具有u形沟道的半导体装置及包括其的电子设备 |
US11621273B2 (en) | 2020-05-13 | 2023-04-04 | Micron Technology, Inc. | Integrated assemblies and methods of forming integrated assemblies |
US20210391354A1 (en) * | 2020-06-15 | 2021-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device |
US11935956B2 (en) * | 2020-06-26 | 2024-03-19 | Intel Corporation | TMD inverted nanowire integration |
US11417683B2 (en) | 2020-10-22 | 2022-08-16 | Macronix International Co., Ltd. | Flash memory and method of fabricating the same |
TWI745132B (zh) * | 2020-10-22 | 2021-11-01 | 旺宏電子股份有限公司 | 快閃記憶體 |
US11737274B2 (en) | 2021-02-08 | 2023-08-22 | Macronix International Co., Ltd. | Curved channel 3D memory device |
CN112885837A (zh) * | 2021-03-22 | 2021-06-01 | 长江存储科技有限责任公司 | 三维存储器和制备三维存储器的方法 |
US11916011B2 (en) | 2021-04-14 | 2024-02-27 | Macronix International Co., Ltd. | 3D virtual ground memory and manufacturing methods for same |
US11710519B2 (en) | 2021-07-06 | 2023-07-25 | Macronix International Co., Ltd. | High density memory with reference memory using grouped cells and corresponding operations |
WO2024039982A2 (en) * | 2022-08-17 | 2024-02-22 | NEO Semiconductor, Inc. | 3d memory cells and array architectures |
Family Cites Families (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3651689B2 (ja) | 1993-05-28 | 2005-05-25 | 株式会社東芝 | Nand型不揮発性半導体記憶装置及びその製造方法 |
US5352619A (en) * | 1993-07-22 | 1994-10-04 | United Microelectronics Corporation | Method for improving erase characteristics and coupling ratios of buried bit line flash EPROM devices |
EP0755540B1 (en) | 1994-04-13 | 2003-04-09 | Ericsson Inc. | Efficient addressing of large memories |
JP2002176114A (ja) | 2000-09-26 | 2002-06-21 | Toshiba Corp | 半導体装置及びその製造方法 |
EP1271652A3 (en) | 2001-06-22 | 2004-05-06 | Fujio Masuoka | A semiconductor memory and its production process |
US6753224B1 (en) * | 2002-12-19 | 2004-06-22 | Taiwan Semiconductor Manufacturing Company | Layer of high-k inter-poly dielectric |
JP2005038909A (ja) * | 2003-07-15 | 2005-02-10 | Fujio Masuoka | 不揮発性メモリ素子の駆動方法、半導体記憶装置及びそれを備えてなる液晶表示装置 |
US7788451B2 (en) | 2004-02-05 | 2010-08-31 | Micron Technology, Inc. | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system |
US20050283743A1 (en) | 2004-06-07 | 2005-12-22 | Mulholland Philip J | Method for generating hardware information |
US20060277355A1 (en) | 2005-06-01 | 2006-12-07 | Mark Ellsberry | Capacity-expanding memory device |
WO2006132158A1 (ja) * | 2005-06-10 | 2006-12-14 | Sharp Kabushiki Kaisha | 不揮発性半導体記憶装置およびその製造方法 |
US7636881B2 (en) | 2005-06-30 | 2009-12-22 | International Business Machines Corporation | Displaying a portal with render-when-ready portlets |
US7462550B2 (en) | 2005-10-24 | 2008-12-09 | Semiconductor Components Industries, L.L.C. | Method of forming a trench semiconductor device and structure therefor |
US7409491B2 (en) | 2005-12-14 | 2008-08-05 | Sun Microsystems, Inc. | System memory board subsystem using DRAM with stacked dedicated high speed point to point links |
KR100707217B1 (ko) | 2006-05-26 | 2007-04-13 | 삼성전자주식회사 | 리세스-타입 제어 게이트 전극을 구비하는 반도체 메모리소자 및 그 제조 방법 |
JP2008034456A (ja) * | 2006-07-26 | 2008-02-14 | Toshiba Corp | 不揮発性半導体記憶装置 |
US7642160B2 (en) | 2006-12-21 | 2010-01-05 | Sandisk Corporation | Method of forming a flash NAND memory cell array with charge storage elements positioned in trenches |
JP2008160004A (ja) | 2006-12-26 | 2008-07-10 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP5118347B2 (ja) | 2007-01-05 | 2013-01-16 | 株式会社東芝 | 半導体装置 |
JP4939955B2 (ja) | 2007-01-26 | 2012-05-30 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR100866966B1 (ko) | 2007-05-10 | 2008-11-06 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 제조 방법 및 반도체 패키지 |
SG148901A1 (en) | 2007-07-09 | 2009-01-29 | Micron Technology Inc | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
JP4957500B2 (ja) | 2007-10-12 | 2012-06-20 | 日本電気株式会社 | 文字列照合回路 |
KR20090037690A (ko) | 2007-10-12 | 2009-04-16 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법 |
KR101226685B1 (ko) * | 2007-11-08 | 2013-01-25 | 삼성전자주식회사 | 수직형 반도체 소자 및 그 제조 방법. |
JP2009158775A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
US8198667B2 (en) | 2007-12-27 | 2012-06-12 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
US7906818B2 (en) | 2008-03-13 | 2011-03-15 | Micron Technology, Inc. | Memory array with a pair of memory-cell strings to a single conductive pillar |
JP5086851B2 (ja) | 2008-03-14 | 2012-11-28 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP5072696B2 (ja) | 2008-04-23 | 2012-11-14 | 株式会社東芝 | 三次元積層不揮発性半導体メモリ |
JP5283960B2 (ja) | 2008-04-23 | 2013-09-04 | 株式会社東芝 | 三次元積層不揮発性半導体メモリ |
JP2009277770A (ja) | 2008-05-13 | 2009-11-26 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP5230274B2 (ja) | 2008-06-02 | 2013-07-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7732891B2 (en) | 2008-06-03 | 2010-06-08 | Kabushiki Kaisha Toshiba | Semiconductor device |
KR20100001260A (ko) | 2008-06-26 | 2010-01-06 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
KR101052921B1 (ko) * | 2008-07-07 | 2011-07-29 | 주식회사 하이닉스반도체 | 버티컬 플로팅 게이트를 구비하는 플래시 메모리소자의제조방법 |
JP5321589B2 (ja) | 2008-08-13 | 2013-10-23 | 日本電気株式会社 | 有限オートマトン生成装置、パターンマッチング装置、有限オートマトン回路生成方法およびプログラム |
KR101498676B1 (ko) | 2008-09-30 | 2015-03-09 | 삼성전자주식회사 | 3차원 반도체 장치 |
JP5193796B2 (ja) | 2008-10-21 | 2013-05-08 | 株式会社東芝 | 3次元積層型不揮発性半導体メモリ |
KR101495803B1 (ko) | 2008-11-12 | 2015-02-26 | 삼성전자주식회사 | 비휘발성 메모리 장치의 제조 방법 및 이에 따라 제조된 비휘발성 메모리 장치 |
US8148763B2 (en) | 2008-11-25 | 2012-04-03 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor devices |
JP5317664B2 (ja) * | 2008-12-17 | 2013-10-16 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JP5388600B2 (ja) * | 2009-01-22 | 2014-01-15 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
US7878507B1 (en) | 2009-02-09 | 2011-02-01 | John Joseph Dimond | Spatial game apparatus |
KR101539699B1 (ko) | 2009-03-19 | 2015-07-27 | 삼성전자주식회사 | 3차원 구조의 비휘발성 메모리 소자 및 그 제조방법 |
JP4897009B2 (ja) * | 2009-03-24 | 2012-03-14 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JP2011009409A (ja) | 2009-06-25 | 2011-01-13 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2011035228A (ja) * | 2009-08-04 | 2011-02-17 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
US8508997B2 (en) | 2009-12-23 | 2013-08-13 | Intel Corporation | Multi-cell vertical memory nodes |
US8803214B2 (en) | 2010-06-28 | 2014-08-12 | Micron Technology, Inc. | Three dimensional memory and methods of forming the same |
US8193054B2 (en) * | 2010-06-30 | 2012-06-05 | SanDisk Technologies, Inc. | Ultrahigh density vertical NAND memory device and method of making thereof |
US8237213B2 (en) | 2010-07-15 | 2012-08-07 | Micron Technology, Inc. | Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof |
US8759895B2 (en) | 2011-02-25 | 2014-06-24 | Micron Technology, Inc. | Semiconductor charge storage apparatus and methods |
KR20130046700A (ko) | 2011-10-28 | 2013-05-08 | 삼성전자주식회사 | 3차원적으로 배열된 메모리 요소들을 구비하는 반도체 장치 |
-
2011
- 2011-02-25 US US13/035,700 patent/US8759895B2/en active Active
-
2012
- 2012-02-17 TW TW101105342A patent/TWI515802B/zh active
- 2012-02-23 KR KR1020137025314A patent/KR101571944B1/ko active IP Right Grant
- 2012-02-23 JP JP2013555567A patent/JP5877210B2/ja active Active
- 2012-02-23 CN CN201280010535.6A patent/CN103403861B/zh active Active
- 2012-02-23 WO PCT/US2012/026358 patent/WO2012116207A2/en active Application Filing
- 2012-02-23 EP EP12749034.0A patent/EP2678882B1/en active Active
-
2014
- 2014-06-20 US US14/310,790 patent/US9231117B2/en active Active
-
2016
- 2016-01-04 US US14/987,370 patent/US9754953B2/en active Active
-
2017
- 2017-08-30 US US15/691,442 patent/US10586802B2/en active Active
-
2020
- 2020-03-09 US US16/813,332 patent/US11581324B2/en active Active
-
2023
- 2023-02-13 US US18/108,970 patent/US20230269937A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
CN103403861B (zh) | 2017-05-17 |
CN103403861A (zh) | 2013-11-20 |
US20230269937A1 (en) | 2023-08-24 |
EP2678882B1 (en) | 2020-08-05 |
WO2012116207A2 (en) | 2012-08-30 |
US9754953B2 (en) | 2017-09-05 |
US20200303391A1 (en) | 2020-09-24 |
JP2014509454A (ja) | 2014-04-17 |
US20160118392A1 (en) | 2016-04-28 |
EP2678882A4 (en) | 2017-01-04 |
JP5877210B2 (ja) | 2016-03-02 |
EP2678882A2 (en) | 2014-01-01 |
WO2012116207A3 (en) | 2012-12-06 |
US20140302650A1 (en) | 2014-10-09 |
US20170365614A1 (en) | 2017-12-21 |
US11581324B2 (en) | 2023-02-14 |
TW201246396A (en) | 2012-11-16 |
US10586802B2 (en) | 2020-03-10 |
US8759895B2 (en) | 2014-06-24 |
US9231117B2 (en) | 2016-01-05 |
KR101571944B1 (ko) | 2015-11-25 |
US20120217564A1 (en) | 2012-08-30 |
KR20140016301A (ko) | 2014-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI515802B (zh) | 電荷儲存裝置、系統及方法 | |
USRE49375E1 (en) | Field effect transistor having fin base and at least one fin protruding from fin base | |
US10692879B2 (en) | Semiconductor device including different orientations of memory cell array and peripheral circuit transistors | |
US9147691B2 (en) | Multi-tiered semiconductor devices and associated methods | |
US9196630B2 (en) | Semiconductor devices having carbon-contained porous insulation over gate stack structures | |
US9166012B2 (en) | Semiconductor memory devices including an air gap and methods of fabricating the same | |
TWI652729B (zh) | 製造半導體裝置的方法 | |
CN110301037B (zh) | 三维存储器结构及其制造方法 | |
US20160086943A1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP2007081301A (ja) | 半導体装置の製造方法および半導体装置 | |
CN111180450B (zh) | 一种半导体器件及其制作方法、电子装置 | |
KR100884975B1 (ko) | 플래시 메모리 소자의 형성 방법 | |
JP2009076636A (ja) | 不揮発性半導体記憶装置の製造方法 | |
CN114551456A (zh) | 半导体器件的制作方法、半导体器件及存储器系统 |