TWI470735B - 絕緣層上覆矽(soi)基板之製造方法 - Google Patents
絕緣層上覆矽(soi)基板之製造方法 Download PDFInfo
- Publication number
- TWI470735B TWI470735B TW97141660A TW97141660A TWI470735B TW I470735 B TWI470735 B TW I470735B TW 97141660 A TW97141660 A TW 97141660A TW 97141660 A TW97141660 A TW 97141660A TW I470735 B TWI470735 B TW I470735B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- nitrogen
- layer
- semiconductor
- containing layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007283669 | 2007-10-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200943477A TW200943477A (en) | 2009-10-16 |
| TWI470735B true TWI470735B (zh) | 2015-01-21 |
Family
ID=40583361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW97141660A TWI470735B (zh) | 2007-10-31 | 2008-10-29 | 絕緣層上覆矽(soi)基板之製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US7696058B2 (https=) |
| JP (1) | JP5542256B2 (https=) |
| KR (1) | KR101497353B1 (https=) |
| CN (1) | CN101425454B (https=) |
| TW (1) | TWI470735B (https=) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7696058B2 (en) * | 2007-10-31 | 2010-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| US7883990B2 (en) * | 2007-10-31 | 2011-02-08 | International Business Machines Corporation | High resistivity SOI base wafer using thermally annealed substrate |
| JP2009141093A (ja) | 2007-12-06 | 2009-06-25 | Toshiba Corp | 発光素子及び発光素子の製造方法 |
| JP5548395B2 (ja) * | 2008-06-25 | 2014-07-16 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
| JP5663150B2 (ja) * | 2008-07-22 | 2015-02-04 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
| KR20120059509A (ko) * | 2009-08-25 | 2012-06-08 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제작 방법 |
| JP2011077504A (ja) * | 2009-09-02 | 2011-04-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| US8655138B2 (en) | 2010-05-10 | 2014-02-18 | Cornell University | Waveguide structure and related fabrication method |
| JP5917036B2 (ja) | 2010-08-05 | 2016-05-11 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
| US9269582B2 (en) * | 2011-03-24 | 2016-02-23 | Entegris, Inc. | Cluster ion implantation of arsenic and phosphorus |
| FR2975222A1 (fr) * | 2011-05-10 | 2012-11-16 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat semiconducteur |
| JP6016532B2 (ja) | 2011-09-07 | 2016-10-26 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US8575666B2 (en) * | 2011-09-30 | 2013-11-05 | Raytheon Company | Method and structure having monolithic heterogeneous integration of compound semiconductors with elemental semiconductor |
| JP2016511934A (ja) * | 2013-01-16 | 2016-04-21 | キューマット インコーポレイテッドQmat, Inc. | 光電子デバイスを形成する技術 |
| KR20150056316A (ko) * | 2013-11-15 | 2015-05-26 | 삼성디스플레이 주식회사 | 소자 기판 제조 방법 및 상기 방법을 이용하여 제조한 표시 장치 |
| US9577110B2 (en) | 2013-12-27 | 2017-02-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including an oxide semiconductor and the display device including the semiconductor device |
| WO2016081367A1 (en) | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION |
| JP6749394B2 (ja) * | 2015-11-20 | 2020-09-02 | グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. | 滑らかな半導体表面の製造方法 |
| SG11201913769RA (en) * | 2017-07-14 | 2020-01-30 | Sunedison Semiconductor Ltd | Method of manufacture of a semiconductor on insulator structure |
| WO2020092647A1 (en) | 2018-10-30 | 2020-05-07 | North Carolina State University | Torque ripple reduction in ac machines |
| US11527701B2 (en) * | 2019-10-28 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Piezoelectric device and method of forming the same |
| CN112885713A (zh) * | 2021-01-29 | 2021-06-01 | 合肥维信诺科技有限公司 | 改善膜质的方法和显示面板 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032043A1 (en) * | 2003-09-08 | 2007-02-08 | Akihiko Endo | Soi wafer and its manufacturing method |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0254532A (ja) * | 1988-08-17 | 1990-02-23 | Sony Corp | Soi基板の製造方法 |
| KR100232886B1 (ko) * | 1996-11-23 | 1999-12-01 | 김영환 | Soi 웨이퍼 제조방법 |
| JPH1197379A (ja) * | 1997-07-25 | 1999-04-09 | Denso Corp | 半導体基板及び半導体基板の製造方法 |
| US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
| JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
| JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
| CN1118087C (zh) * | 1999-09-27 | 2003-08-13 | 中国科学院半导体研究所 | 一种制备半导体衬底的方法 |
| US6566233B2 (en) * | 1999-12-24 | 2003-05-20 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded wafer |
| WO2001093334A1 (en) * | 2000-05-30 | 2001-12-06 | Shin-Etsu Handotai Co.,Ltd. | Method for producing bonded wafer and bonded wafer |
| JP3675312B2 (ja) * | 2000-07-10 | 2005-07-27 | 松下電器産業株式会社 | 薄膜構造体、及びその応力調整方法 |
| JP4507395B2 (ja) | 2000-11-30 | 2010-07-21 | セイコーエプソン株式会社 | 電気光学装置用素子基板の製造方法 |
| US6583440B2 (en) * | 2000-11-30 | 2003-06-24 | Seiko Epson Corporation | Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus |
| US6376336B1 (en) * | 2001-02-01 | 2002-04-23 | Advanced Micro Devices, Inc. | Frontside SOI gettering with phosphorus doping |
| DE10124030A1 (de) * | 2001-05-16 | 2002-11-21 | Atmel Germany Gmbh | Verfahren zur Herstellung eines Silizium-Wafers |
| US7420147B2 (en) * | 2001-09-12 | 2008-09-02 | Reveo, Inc. | Microchannel plate and method of manufacturing microchannel plate |
| FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
| US20070032040A1 (en) * | 2003-09-26 | 2007-02-08 | Dimitri Lederer | Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses |
| FR2871172B1 (fr) * | 2004-06-03 | 2006-09-22 | Soitec Silicon On Insulator | Support d'epitaxie hybride et son procede de fabrication |
| KR100634528B1 (ko) * | 2004-12-03 | 2006-10-16 | 삼성전자주식회사 | 단결정 실리콘 필름의 제조방법 |
| JP5128761B2 (ja) * | 2005-05-19 | 2013-01-23 | 信越化学工業株式会社 | Soiウエーハの製造方法 |
| US20070111468A1 (en) * | 2005-07-19 | 2007-05-17 | The Regents Of The University Of California | Method for fabricating dislocation-free stressed thin films |
| US7268051B2 (en) | 2005-08-26 | 2007-09-11 | Corning Incorporated | Semiconductor on glass insulator with deposited barrier layer |
| EP1981064B1 (en) | 2005-12-27 | 2021-04-14 | Shin-Etsu Chemical Co., Ltd. | Process for producing a soi wafer |
| JP2008004821A (ja) * | 2006-06-23 | 2008-01-10 | Sumco Corp | 貼り合わせウェーハの製造方法 |
| CN101796613B (zh) * | 2007-09-14 | 2012-06-27 | 株式会社半导体能源研究所 | 半导体装置及电子设备 |
| JP2009135430A (ja) * | 2007-10-10 | 2009-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| US7696058B2 (en) * | 2007-10-31 | 2010-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
-
2008
- 2008-10-28 US US12/259,833 patent/US7696058B2/en not_active Expired - Fee Related
- 2008-10-29 TW TW97141660A patent/TWI470735B/zh not_active IP Right Cessation
- 2008-10-29 CN CN200810173827.7A patent/CN101425454B/zh not_active Expired - Fee Related
- 2008-10-29 JP JP2008278152A patent/JP5542256B2/ja not_active Expired - Fee Related
- 2008-10-31 KR KR1020080108090A patent/KR101497353B1/ko not_active Expired - Fee Related
-
2010
- 2010-01-25 US US12/692,768 patent/US8207045B2/en not_active Expired - Fee Related
-
2012
- 2012-05-09 US US13/467,082 patent/US9837300B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032043A1 (en) * | 2003-09-08 | 2007-02-08 | Akihiko Endo | Soi wafer and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20090045130A (ko) | 2009-05-07 |
| US20100120225A1 (en) | 2010-05-13 |
| US7696058B2 (en) | 2010-04-13 |
| US9837300B2 (en) | 2017-12-05 |
| TW200943477A (en) | 2009-10-16 |
| CN101425454B (zh) | 2014-11-05 |
| US20120282757A1 (en) | 2012-11-08 |
| KR101497353B1 (ko) | 2015-03-02 |
| JP2009135465A (ja) | 2009-06-18 |
| JP5542256B2 (ja) | 2014-07-09 |
| US20090111236A1 (en) | 2009-04-30 |
| CN101425454A (zh) | 2009-05-06 |
| US8207045B2 (en) | 2012-06-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |