TWI455194B - 清潔基板表面之方法及設備 - Google Patents
清潔基板表面之方法及設備 Download PDFInfo
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- TWI455194B TWI455194B TW100135339A TW100135339A TWI455194B TW I455194 B TWI455194 B TW I455194B TW 100135339 A TW100135339 A TW 100135339A TW 100135339 A TW100135339 A TW 100135339A TW I455194 B TWI455194 B TW I455194B
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- Prior art keywords
- substrate
- chamber
- plasma
- cleaning
- oxygen
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- 239000000463 material Substances 0.000 claims description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 23
- 239000001301 oxygen Substances 0.000 claims description 23
- 229910052760 oxygen Inorganic materials 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 15
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 9
- 229910052707 ruthenium Inorganic materials 0.000 claims description 9
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052762 osmium Inorganic materials 0.000 claims description 4
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 230000008569 process Effects 0.000 description 65
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- VHHHONWQHHHLTI-UHFFFAOYSA-N hexachloroethane Chemical compound ClC(Cl)(Cl)C(Cl)(Cl)Cl VHHHONWQHHHLTI-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/08—Reaction chambers; Selection of materials therefor
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- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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- H—ELECTRICITY
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
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- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
- H01L21/02661—In-situ cleaning
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/976—Temporary protective layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Description
本發明之實施例一般涉及一種用於處理半導體基板之方法及設備,特別是一種用於清潔矽基板表面之方法及設備。
積體電路係形成在矽及其他半導體基板內及上方。在單晶矽之實施例中,係藉由自一熔化矽浴中生長矽晶錠(ingot),並接著將結晶之矽晶錠鋸開成為多個晶圓而製成基板。磊晶矽層可接著形成在單晶矽晶圓上,以形成摻雜或未摻雜之無缺陷矽層。半導體元件(例如電晶體)係由磊晶矽層製成。所形成之磊晶矽層的電學特性通常較單晶矽基板之特性還要佳。
單晶矽及磊晶矽層之表面當暴露於一般周遭條件時容易受到污染。因此,在執行多個半導體處理(例如形成磊晶層)之前,基板需要清潔以移除矽晶圓表面上之不純物及微粒。
於習知技術中,半導體基板係利用濕式清潔處理或習知之電漿清潔處理以進行清潔。然而,濕式清潔處理具有「排隊時間」的問題,由於一批中的晶圓具有不同的閒置時間,故會造成一批晶圓中的晶圓與晶圓之間產生差異。習知之遠端或原位(in situ)電漿清潔處理極具挑戰性,此乃因為於氣相或清潔處理過程中所產生之不期望存在的物種而造成腔室及腔室中待處理之基板的污染。該些不期望存在之物種會限制期望物種之清潔作用,或是將其他的困難導入清潔處理中。
因此,需要一種清潔基板表面的方法及設備,特別是在執行磊晶沉積製程之前用於清潔基板表面的方法及設備。
本發明一般係提供一種用於處理基板的設備,該設備包括一低能量清潔腔室、一磊晶層沉積腔室以及一傳輸室。該低能量清潔腔室包括:形成一處理區域之一或多個壁;適於傳送電磁能至處理區域的一電漿產生源;適於傳送一含矽氣體至處理區域的第一氣源;適於傳送氧化氣體至處理區域的一第二氣源。該傳輸室具有圍出一傳輸區域的一或多個壁,以及適於將基板傳輸於低能量清潔腔室中的一第一位置以及磊晶層沉積腔室中的一第一位置之間的一機械手。
本發明的實施例更包括用於執行低能量清潔處理的一設備,該設備包括:形成一處理區域的一或多個壁;適於傳送電磁能至處理區域的一電漿產生源;設置在處理區域中的一屏蔽,其中該屏蔽的材料係選自由矽、釔、氧化釔、鍺、硼、磷及矽鍺化合物所組成之群組而製成;一基板支撐件,具有一基板支撐表面以及適於被RF功率源所偏壓之一偏壓電極;適於傳送一氧化氣體至處理區域的第一氣源;適於傳送惰性氣體至處理區域的一第二氣源;以及適於傳送一含矽氣體至處理區域的第三氣源。
本發明之實施例更提供一種用於形成一磊晶層的方法,該方法包括:在一腔室部件的一表面上沉積一集除層(gettering layer),而該腔室部件係設置於一清潔腔室中的一處理區域內;將基板放置在清潔腔室之處理區域中的基板支撐件上;將放置在基板支撐件上的基板表面進行氧化;自放置在該基板支撐件上的該基板移除至少一部分的氧化表面;在移除至少一部分的氧化表面之後,藉由將基板表面暴露於含氫氣體而鈍化該基板表面;將基板由清潔腔室傳輸至磊晶層沉積腔室;以及在至少一部分的鈍化表面上沉積一磊晶層。
本發明之實施例更提供一種用於執行低能量清潔處理的設備,該設備包括:形成處理區域的一或多個壁,其中該一或多個壁之至少其中之一者含有熱交換裝置,以控制該一或多個壁之至少其中之一者的溫度;適於傳送電磁能至處理區域的一電漿產生源;設置在處理區域中的一屏蔽;一基板支撐件,具有一基板支撐表面、適於被RF功率源所偏壓的一偏壓電極,以及用於控制基板支撐表面溫度的一基板支撐件熱交換裝置;適於傳送氧化氣體至處理區域的一第一氣源;以及適於傳送蝕刻氣體至處理區域的一第二氣源。
本發明一般提供用於在半導體基板(或晶圓)上形成乾淨及無傷害之表面的設備及方法。本發明之一實施例提供一系統,其含有一清潔腔室,該清潔腔室係適以在基板表面上形成磊晶層之前,將該基板表面暴露於電漿清潔處理。在一實施例中,係使用一方法以減少在清潔腔室中進行處理之基板的污染,其係藉由在基板上執行清潔處理之前,於清潔腔室之內表面上沉積一集除物質(gettering material)。集除物質會傾向補抓在清潔腔室中的污染物,因而確保待處理之基板為乾淨的,且即將在清潔腔室中進行處理之基板亦具有相同之期望的乾淨成果。在一實施例中,於清潔腔室中之基板上執行的氧化及蝕刻步驟係重複進行的,以在基板上暴露或產生一乾淨表面,而此表面接著可在其上設置磊晶薄膜。在一實施例中,在蝕刻步驟過程中係使用低能量電漿。電漿之低能量可藉由下列方式達成:降低基板RF偏壓功率、調整施加跨越基板之偏壓電位、將用於在處理腔室中產生之RF功率進行脈衝、脈衝基板RF偏壓功率、形成含有輕(light)原子物種之電漿、使用電漿屏蔽以限制電漿、調整基板相對於電漿之處理位置及/或其組合。
「第1圖」係概要繪示根據本發明之一實施例的清潔腔室100之剖面側視圖。清潔腔室100為感應耦合電漿處理腔室,其能夠在處理區域122中清潔基板102。在一實施例中,清潔腔室100為經修改之去耦電漿氮化(DPN)腔室,其可購自加州聖克拉拉之應用材料公司(Applied Material),該腔室係利用感應耦合射頻(RF)源。適以執行此處所述之一或多個處理的DPN腔室之詳細描述可參見:美國專利第6,660,659號,專利名稱為「用於處理基板之電漿方法及設備(Plasma Method and Apparatus for Processing a Substrate)」;以及美國專利第7,122,454號,專利名稱為「用於改善電漿氮化閘極介電層中之氮分佈的方法(Method for improving nitrogen profile in plasma nitrided gate dielectric layers)」,在此將其全文併入以做為參考。
清潔腔室100一般包括一RF源組件191、一處理腔室組件193及一基板支撐組件194。處理腔室組件193通常包括多個用於在處理區域122中形成真空之部件,藉此可在其中執行電漿處理。一般來說,處理腔室組件193包括密封地圍繞處理區域122之腔室基座127、腔室壁128及腔室蓋129。處理區域122可利用真空幫浦110而抽氣至期望真空壓力,而真空幫浦110係穿過腔室基座127及/或腔室壁128而連接至處理區域122。一般來說,腔室壁128及腔室基座127可以由金屬形成,例如鋁或其他適合金屬。
在一實施例中,腔室壁128及腔室蓋129可以為溫控的。可使用習知之方法及/或熱交換裝置來加熱及冷卻各個腔室部件。舉例來說,可以藉由設置在處理腔室組件193外的加熱器(圖中未示,例如為燈組)來加熱腔室壁128及腔室蓋129。在另一實施例中,可將冷卻氣體循環於處理腔室組件193外側,藉以冷卻腔室壁128及腔室蓋129。在另一實施例中,嵌設在腔室壁128及腔室蓋129中的加熱及/或冷卻導管可連接至流體加熱器/冷卻器裝置以控制溫度。可用於控制處理腔室組件193之方法及設備可參見美國專利第6,083,323號,專利名稱為「用於在處理期間控制反應腔室壁的溫度之方法(Method for Controlling the Temperature of the Walls of a Reaction Chamber During Processing)」,在此將其併入以做為參考。
在一實施例中,RF源組件191為感應型(inductive)RF源,其通常包含RF產生器108及RF匹配電路108A,而RF匹配電路108A係連接至線圈109。線圈109係鄰近腔室蓋129。在一實施例中,RF產生器108可以在約400 kHz~約60MHz之頻率下而於約0~約3000W(瓦)下操作。在一實例中,RF產生器108係在13.56 MHz之頻率下操作。在一實施例中,RF產生器108可以提供RF能量脈衝至線圈109,以產生具有較低能量層級及/或電漿密度之電漿。
腔室蓋129通常為介電部件(例如:石英、陶瓷物質【如:氧化鋁】),其係適以允許來自感應型RF源組件191在處理區域122中形成電漿。
在一實施例中,處理腔室組件193亦含有氣體輸送系統150,而該氣體輸送系統150係適於將一或多種處理氣體輸送至處理區域122內,而處理區域122係由腔室基座127、腔室壁128及腔室蓋129所界定出。在一實施例中,處理區域122之周圍係圍繞有一或多個屏蔽130,而該些屏蔽130係用於保護腔室壁128及/或腔室蓋129免受所產生之電漿以及在腔室中進行之準備處理的傷害。在一實施例中,氣體輸送系統150包括臭氧產生器,其係配置以產生含有高濃度臭氧(O3
)的氣流。在一實施例中,氣體輸送系統係適於輸送反應性氣體,例如含矽氣體(例如矽烷)、含氫氣體(例如氫氣)、含鍺氣體、含氯氣體、含氧氣體(例如氧氣)、三氟化氮(NF3
)、含硼氣體(例如二硼烷)及/或含磷氣體(例如膦)(僅列出少數)。在一實施例中,氣體輸送系統係適於輸送惰性氣體,例如氬氣(Ar)、氦氣(He)、氪氣(Kr)及/或氮氣(N2
)。處理區域122中的壓力之調整可以藉由調整由氣體輸送系統150進行輸送之氣體的流速以及真空幫浦110的抽氣速率。節流閥111可用於調整真空幫浦110的抽氣速率。
基板支撐組件194一般包括基板支撐件162,其含有基板支撐構件162A。基板支撐構件162A可以為用於在處理過程中主動支托基板之習知的靜電吸座,或者是包括簡單的基板支撐件。溫度控制器161係通常適於利用溫度控制器161及熱交換裝置來加熱及/或冷卻基板支撐構件162A至一期望溫度,熱交換裝置例如為嵌設之電阻加熱元件或耦接至習知的熱交換器之流體冷卻通道(圖中未示)。在一實施例中,溫度控制器161係適以操作並加熱設置在基板支撐構件162A上的基板102至介於約20℃~約800℃之溫度。
在處理過程中,基板支撐件162可以連接至RF產生器123,藉此,RF偏壓可以施加至設置在基板支撐件162之一部分中的導電元件,以將處理區域122中所形成的電漿吸引至基板102的表面。在一實施例中,RF產生器123係適以在基板清潔處理的一或多個部分過程中於基板上產生陰極或陽極偏壓,藉以調整基板上所保有的電荷,及/或控制基板表面之離子及電漿轟擊量。在一實施例中,基板支撐構件162A為接地,或是為直流(DC)偏壓。在另一實施例中,基板支撐構件162A以及基板在電漿處理過程中為電性浮置,以使得基板102之離子轟擊傷害降到最低。
參照「第1圖」,將來自RF產生器108的RF能量輸送至處理區域122會導致處理區域122中的氣體原子產生離子化。在清潔處理過程中,當基板暴露於處理區域122中所產生的電漿,基板102表面的污染會被擊出,或是自表面而去吸附(desorb),此乃因為由電漿中之離子化原子所傳輸之能量撞擊基板102表面所致。在一實施例中,由於透過基板支撐構件162A而施加至基板102的偏壓,電漿中的離子化氣體原子可以吸附至基板102的表面。
在一實施例中,藉由RF產生器108而傳送至線圈109之RF功率係經脈衝以形成低能量電漿。在一實施例中,脈衝電漿處理通常為藉由RF產生器108所作用之線圈109而以時間為函數之一系列傳送至處理區域122之連續能量脈衝。將感應型RF源進行脈衝,以激發處理區域122中的電漿,其會使得通常形成在習知電漿處理腔室中之電漿電位(plasma potential)對於基板表面所造成之傷害降至最低。將對於基板表面所造成之任何傷害利用清潔處理而最小化或消除之需求,對於單晶基板來說是關鍵的,單晶基板係製備而用於在其上形成磊晶層。對於基板表面之傷害需要被最小化,藉以減少在所形成之磊晶層中的缺陷數量及應力。因此,對感應型RF源功率進行脈衝係允許產生並維持一低電子溫度及低離子能量電漿。一般來說,由脈衝RF感應電漿所產生之離子,其所產生之離子為具有低離子能量(例如<10 eV),而其不會對於設置在電漿中的基板造成傷害。可以適用並受益於本發明之一或多個實施例之脈衝RF功率的方法之實例係進一步討論於共同受讓之美國專利第6,831,021號(2003年6月12日申請),在此將其併入以做為參考。
「第2A圖」係概要繪示根據本發明之另一實施例的清潔腔室100a之剖面側視圖。清潔腔室100a為電容耦合電漿腔室。清潔腔室100a包括腔室蓋129,其密封地耦接至處理腔室組件196,並界定一處理區域133。在此配置中,腔室蓋組件130包括氣體分配板(亦稱之為噴氣頭)132及基座板131,而該基座板131具有一阻隔板134,且阻隔板134係實質平行於氣體分配板132。氣體分配板132係利用電性絕緣體135而與腔室壁128隔離。腔室蓋組件130係連接至氣體輸送系統150。來自氣體輸送系統150之反應物及/或清潔氣體可以透過氣體通道136而流入處理區域133。RF源組件191係耦接至基座板131以提供用於電漿產生之RF功率源。用於電容電漿產生之RF源通常包括一射頻(RF)功率源,例如13.56 MHz之RF產生器。在處理過程中,基板支撐構件162A可以為接地。在基板支撐構件162A與基座板131之間的偏壓電位可以點燃處理區域133中的電漿。在電漿中經激發之物種可以用於處理基板102。在處理過程中,基板支撐構件162A可以連接至RF產生器123,藉此,RF偏壓可以施加至設置在基板支撐構件162A之部分中的導電元件,藉以將已在處理區域122中產生之電漿中的離子吸引至基板102表面。針對電容耦合電漿反應器之更詳細的描述可以參見美國專利第6,495,233號,專利名稱為「在化學氣相沉積系統中分配氣體的設備(Apparatus for distributing gases in a chemical vapor deposition system)」,在此將其併入以做為參考。
描述於上之清潔腔室100、100a(「第1及2圖」)可以用於清潔半導體基板。更特定的說,本發明之清潔腔室100、100a可以用於對矽表面執行無傷害之清潔。
在另一實施例中,清潔腔室可以使用微波能量源(圖中未示)來產生電漿,而該電漿可用於執行本發明所述之清潔處理。
「第3圖」繪示根據本發明之一實施例而用於清潔半導體基板之方法200的流程圖。在一實施例中,方法200可以在上述之清潔腔室100、100a中執行。在一實施例中,清潔處理通常提供一種使用電漿清潔處理而形成乾淨且無傷害之半導體基板表面的方法。
在步驟212,清潔腔室(例如清潔腔室100或100a)的內表面係經過再生(regenerated)。在一實施例中,步驟212包括執行一蝕刻處理以移除清潔腔室之各個內表面上的不期望存在之殘留物質及/或污染。可執行習知之濺射蝕刻及/或化學輔助蝕刻處理以再生清潔腔室之內表面,例如腔室壁或屏蔽130。
在一實施例中,反應性氣體之遠端或原位電漿可以用於移除清潔腔室之內表面上的污染。反應性氣體可以選自廣範圍之氣體,包括普遍使用之鹵素及鹵素化合物。舉例來說,視待移除之沉積物質而定,反應性氣體可以為氯、氟或其化合物,例如三氟化氮(NF3
)、四氟化碳(CF4
)、六氟化硫(SF6
)、六氟乙烷(C2
F6
)、四氯化碳(CCl4
)、六氯乙烷(C2
Cl6
)或其組合。
在一實施例中,例如為氬氣、氮氣、氦氣、氫氣或氧氣之載氣係傳送至清潔腔室之處理區域中,以幫助不期望存在之物種的移除,及/或協助蝕刻處理、或幫助清潔腔室中之電漿的起始及/或穩定。
在一實施例中,清潔氣體可以傳送至清潔腔室中,以蝕刻包括集除物質(gettering material)(將於下討論之)之塗層,例如在清潔腔室之內表面上的矽(Si)。清潔氣體可以包括加熱之三氟化氮(NF3
)、氯化氫(HCl)或其組合。在一實施例中,習知之遠端電漿源(RPS)可以耦接至處理腔室之處理區域。RPS通常提供具有反應性之清潔劑,例如解離氟,其將沉積及其他處理副產物自腔室部件移除,並利用真空幫浦110排出。
在步驟214,可使用一遮盤或一仿真基板(dummy substrate)覆蓋住基板支撐構件(例如「第1及2A圖」之基板支撐構件162A)的頂表面。遮盤或仿真基板可以用於預防在接續的沉積過程中(例如步驟216),於基板支撐構件上產生沉積,藉此,待處理之基板不會與任何形成在清潔腔室內的塗層接觸。覆蓋住基板支撐構件亦可防止當基板支撐構件為配置以在處理過程中支托基板的靜電吸座時會產生的吸附問題。
在步驟216,於一實施例中,一或多個清潔腔室部件,例如腔室壁128、屏蔽130、遮蔽環138、腔室蓋129,可以藉由在其上沉積一集除塗層而調理(condition)之。集除塗層可包括一或多個集除物質。所謂的「集除物質」通常是指在清潔處理之前或是清潔處理過程中用於固定及/或吸附(即,物理性吸附或化學性吸附)在清潔腔室中的不純物之任何物質。集除物質係經選擇以移除在清潔腔室中不期望存在的副產物,且不會衍生其他問題,例如新副產物的生成、產生微粒物質、RF功率的不期望消散情形或是移除處理區域122中期望存在的物種。在步驟216所形成之沉積集除塗層的厚度係介於約10~約1 μm。在內表面上的塗層可用於減低或預防接續處理之基板的污染。塗層可包括純矽物質(例如磊晶矽層、多晶矽層、非晶矽層)、含矽層、含鍺層,及/或含有期望層級之一或多個常見摻質物質(例如硼B、磷P)之矽或鍺層,或其混合物。相信由純矽所形成之塗層對於矽基板上常見之多數污染具有強力之集除效應,而此矽基板即將具有形成於其上之磊晶層。矽的使用係有利於微粒污染對於裝置產量之效應的最小化,而此微粒污染是後續形成在基板之經過清潔的表面上之磊晶層的金屬污染所造成。在一實例中,集除塗層係利用含矽烷(SiH4
)氣體而進行沉積的,而含矽烷氣體係傳送至處理腔室之處理區域,其壓力為約0.1~約5.0托(Torr),RF功率介於約200瓦~約2千瓦,而腔室部件溫度係維持在約200℃~約500℃。
在一實施例中,配置以集除氧氣之集除物質層可沉積在清潔腔室之內表面上。在一實施例中,塗層包括厚度為約10~約1 μm的矽層。可以使用典型之CVD或ALD型處理而沉積矽塗層,而該些處理係將含矽前驅物傳送至設置在腔室之處理區域中的加熱部件。接收到集除物質之部件可以使用外部燈、嵌設之電阻加熱元件來進行加熱,及/或使用RF電漿來進行加熱。
於步驟216中所沉積之集除物質的塗層能夠將清潔處理中產生之不期望存在物種固定、吸收或吸附。最終,隨著活性表面被覆蓋,或是變得較不具反應性,則塗層的集除能力會降低。為了補償此問題,可以藉由重複進行步驟212、214、216而在處理區域122之部件上形成集除物質之新塗層。在一實施例中,於清潔腔室中處理各個基板之前,重複進行步驟212、214、216。在另一實施例中,於清潔腔室中處理多個基板之後,重複進行步驟212、214、216。
在沉積集除物質層之後,將遮盤、仿真盤或仿真基板自清潔腔室中移除。接著,將待清潔之基板放置在清潔腔室中。由於清潔腔室係保持在真空狀態下,在基板表面上存在之污染及微粒物質(例如,氧、碳、氟、矽及氯)可以被去吸附或是被移開,並利用形成在清潔腔室之內表面上之塗層而集除。
接著,執行一或多個氧化及蝕刻步驟(於下將討論)來清潔基板。氧化處理係用於消耗掉基板表面上之已污染或已傷害的矽。所形成之氧化層接著被移除以暴露出新鮮且乾淨之矽表面。氧化處理描述於步驟220,蝕刻步驟則描述於步驟222。
在步驟220,氧化劑係傳送至清潔腔室,以在待清潔之基板的頂部層上產生氧化物。在一實施例中,氧化劑包括臭氧(O3
),其使得矽的氧化在相對低的溫度下進行。在一實施例中,將氧暴露於電漿、紫外光(UV)能量或是電漿與UV能量之組合,而在臭氧產生器中產生臭氧。在一實施例中,設置有UV燈145以在處理過程中,將能量傳送至基板表面。在一實施例中(圖中未示),設置有UV燈以將UV光傳送通過形成在腔室壁128其中之一者的一通口。針對氧化方法之詳細描述可以參見美國專利申請第2006/0223315號,專利名稱為「使用臭氧以進行矽的熱氧化(Thermally Oxidizing Silicon Using Ozone)」,以及美國專利申請第2002/0115266號,專利名稱為「用於將磊晶矽層密接在基板上之方法及系統(Method and a System For Sealing An Epitaxial Silicon Layer On A Substrate)」,在此將兩者皆併入以做為參考。
在一實施例中,基板表面係利用高溫氧化處理而進行氧化。在此實例中,基板在基板支撐構件(例如「第1圖」之基板支撐構件162A)上加熱至介於約400℃~約700℃。在氧化過程中,清潔腔室係維持在低於基板的溫度。舉例來說,包括有氣體輸送路徑之清潔腔室部件(例如壁、屏蔽)係維持在小於400℃,或是實質低於400℃。在一實施例中,基板支撐構件/加熱器係維持在約700℃,而清潔腔室係維持在約350℃。在一實施例中,利用流經處理腔室壁中的通道之流體而對壁進行溫度控制。
在步驟222,接著進行蝕刻處理以移除在步驟220所形成之氧化物。可以使用物理、化學或物理及化學蝕刻技術之組合而進行該蝕刻處理。
在化學蝕刻之實例中,蝕刻氣體係傳送進入清潔腔室,而電漿係經點燃以產生會與基板上之物質發生化學反應之反應性物種。反應的揮發性副產物可以藉由連接至清潔腔室之真空系統移除,及/或利用在步驟216而形成在腔室部件表面上的塗層集除。蝕刻氣體包括氯、氟或是其他適於在步驟220中將形成在基板表面之氧化物移除的其他化合物。在一實施例中,蝕刻氣體包括三氟化氮(NF3
)、氯離子(Cl-
)以及載氣(例如氬氣)。
物理蝕刻之進行係藉由產生用於提供激發物種之電漿而執行,該激發物種係用於轟擊基板表面,以將物質物理性地自基板表面移除。在部分實例中,係期望提供基板支撐件一偏壓,以加速在電漿中形成的離子朝向基板表面移動。轟擊離子係藉由濺射蝕刻作用而物理性地移除在基板表面上的物質。一般期望基板表面之低能量物理性轟擊可以減少對於基板表面之矽晶格的傷害。低功率偏壓可用於移除氧化層,並且將對於基板表面之傷害最小化。習知之乾式蝕刻處理通常用於快速移除物質,而並不需考量到電漿輔助物質移除處理所產生的基板物質晶格傷害。習知之濺射蝕刻技術並不期望用於在磊晶沉積步驟執行之前清潔基板,此乃因為轟擊離子之高能及/或副產物的存在。更特定的說,本發明之蝕刻處理包括調整在蝕刻處理過程中形成之離子的能量,以使得在步驟222中於基板表面暴露出之結晶物質的傷害最小化。在一實施例中,藉由在腔室中使用低RF功率物質移除處理,且此腔室中具有集除物質,則在步驟222所進行之物質移除處理會在基板上形成無傷害且乾淨的表面,而此對於在接續之沉積處理步驟中確保形成高品質磊晶層是十分重要的。在一實施例中,RF產生器123係適於傳送約25瓦~約500瓦之平均RF偏壓功率至設置在基板支撐件162中的導電元件,以執行蝕刻處理。
在方法200之選擇性實施例中,步驟216是在步驟220之後且在步驟222之前進行。在此選擇性實施例之一實施態樣中,步驟220及222在不同的腔室中進行,故在執行步驟222之前,不會在氧化基板之表面上沉積集除層(步驟216)。在使用單一腔室之選擇性實施例的另一實施態樣中,步驟220係在基板上執行,接著將基板自清潔腔室中移除,則可置入仿真基板以允許步驟216之進行而不會將集除物質塗覆在氧化基板的表面上,接著,將仿真基板移除,並將氧化基板重新置入而可進行步驟222。
「第4圖」係概要繪示清潔腔室300之部分剖面側視圖,其繪示用於進行物理蝕刻處理之構件。清潔腔室300具有界定出處理區域302之腔室主體301。待清潔之基板303可設置在基板支撐件304上而位於處理區域302中。線圈305係設置在腔室主體301之上方部分的外側,藉以在處理區域302的上方部分產生電漿308。RF源306係連接至線圈305,以提供用於產生電漿之能量。偏壓源307可耦接至基板支撐件304,以提供偏壓電位給基板303及/或基板支撐件304。在電漿308中產生的活化物種309或離子310係吸引至基板303的頂表面303A,以移除在其上的物質。
在一實施例中,活化物種309及/或離子310的能量可經過調整,藉此在物質移除的過程中,不會對頂表面303A造成物理性的傷害。上述之調整可藉由下列方式達成:降低基板RF偏壓功率、調整施加跨越基板的偏壓電位、將傳送至電漿產生部件(例如感應耦合裝置【例如線圈】、將電容耦合裝置【例如噴氣頭、微波源】)之RF功率進行脈衝、脈衝基板RF偏壓功率、形成含有在蝕刻氣體中之輕原子物種的電漿、使用電漿屏蔽以限制電漿、調整基板相對於電漿之處理位置及/或上述之組合。
在一實施例中,可以藉由使用傳送至基板支撐件之較低的RF偏壓功率以降低活化物種的能量。在一實施例中,偏壓源(例如「第4圖」中的偏壓源307)的功率可設定為約50瓦,以將基板頂表面上的二氧化矽移除。
在一實施例中,偏壓源(例如「第4圖」中的偏壓源307)的電位可調整為較不陰極性(cathodic),以降低基板上的偏壓。在一實施例中,可省略偏壓源,且基板設置在接地的基板支撐件上。在另一實施例中,可施加逆向偏壓(reversed bias),藉以對電漿中的離子及反應性離子物種施加排斥力。舉例來說,當清潔絕緣層上覆矽(silicon-on-insulator)基板時,可以使用逆向偏壓。
在一實施例中,係藉由脈衝RF源及/或基板偏壓源來降低電漿能量,可以藉由調整傳送至電漿產生部件(例如,線圈、噴氣頭、微波源)的RF脈衝之工作週期(duty cycle)以控制能量降低的程度。脈衝RF源會降低由RF源產生之電漿中的活化物種之密度。在一實施例中,RF源係經脈衝以在清潔處理過程中維持清潔腔室中的低能量電漿。脈衝RF源會降低在電漿處理區域中的總電漿及活化物種密度,因而降低轟擊物種的能量及數量,以避免對基板造成傷害。針對脈衝電漿處理之詳細討論可參照美國專利申請序號第11/614,019號,於2007年12月20日申請,專利名稱為「使用低能量電漿設備以製造高介電常數之電晶體閘極的方法及設備(Method and Apparatus for Fabricating a High Dielectric Constant Transistor Gate Using a Low Energy Plasma Apparatus)」,在此將其併入以做為參考。
在一實施例中,蝕刻氣體包括一或多個較輕的物種,其係用於產生低能量電漿,藉以使得物理蝕刻處理產生在基板表面上之任何傷害降低或最小化。在一實施例中,較輕的氣體物種,例如氦氣(He)、氖氣(Ne)、氫氣(H2
)或其混合物,可以添加至蝕刻氣體中,而蝕刻氣體包含有其他處理氣體,例如氬氣(Ar)。在一實施例中,蝕刻氣體包括氬氣及氦氣。在另一實施例中,蝕刻氣體實質包括氬氣、氦氣及氫氣。在另一實施例中,蝕刻氣體包括氬氣及氫氣。在另一實施例中,蝕刻氣體包括氬氣及氮氣。在又另一實施例中,蝕刻氣體實質包括氦氣(He)、氖氣(Ne)或氫氣(H2
)。
在另一實施例中,電漿屏蔽140(「第2B圖」)在處理過程中係設置在基板表面附近。「第2B圖」概要繪示清潔腔室100之一實施例的剖面側視圖,而該清潔腔室100包含一電漿屏蔽140。電漿屏蔽係用於使得接近基板表面之轟擊物種的數量及/或能量降低或最小化。電漿屏蔽140為經穿孔或是多孔的物質,其允許部分的電漿及/或處理氣體在處理過程中通過。在一實施例中,穿孔為穿過電漿屏蔽的複數個孔洞141。在一實施例中,電漿屏蔽由介電材料製成,或是塗覆有介電材料,而其與電漿及處理氣體相容(例如,石英、SiO2
)。在一實施例中,電漿屏蔽係由與腔室之其他部件的相同材料製成,例如腔室蓋129或腔室壁128之製成材料。在一實施例中,電漿屏蔽係由一材料製成,該材料係選自由矽、釔、氧化釔、鍺、硼、磷及矽鍺化合物所組成之群組。
在另一實施例中,待處理之基板與清潔腔室中所產生之電漿的相對位置可經調整,而藉以對電漿中轟擊基板表面之離子或活化物種的量進行調整。相似的調整方式係描述於共同受讓之美國專利申請第2006/0105114號,專利名稱為「用於低溫多晶矽TFTs之多層高品質閘極介電層(Multi-Layer High Quality Gate Dielectric for Low-Temperature Poly-Silicon TFTs)」,在此將其併入以做為參考。
再往回參照「第3圖」,步驟222之示範性蝕刻處理可以在類似於「第1圖」之清潔腔室100的清潔腔室中進行,藉以移除在基板之頂表面上形成之氧化矽。在處理過程中,腔室壓力係維持在約1毫托~約1托。在一實施例中,腔室壓力係維持在約20毫托~約800毫托。包括氦氣及氬氣之蝕刻氣體可提供至處理區域。在一實施例中,腔室壓力為約5毫托~約20毫托,且蝕刻氣體主要包括氦氣。正在進行處理之基板亦可加熱至高達約700℃。清潔腔室可以維持在約20℃~約400℃。在一實施例中,腔室係維持在約30℃之溫度。相信將腔室壁維持在較低溫度下可以協助減少腔室壁之腐蝕。
回到「第3圖」,步驟220、222可以重複進行一或多次,直到基板乾淨為止。一旦基板表面是乾淨的,則接著在經過清潔的基板表面上進行步驟224及/或步驟226。
在步驟224,在經過清潔之基板上執行鈍化處理,則基板會保持乾淨直到接續之磊晶沉積製程進行為止。在一實施例中,鈍化處理包括流入一鈍化氣體及產生鈍化氣體的電漿。在一實施例中,鈍化氣體包括具有稀釋濃度的氫氣(H2
),其係利用氫來終接(terminate)經過清潔之矽表面。在一實施例中,鈍化處理包括傳送包含約1%氫氣的含氫氣體,且同時基板係維持在約50~500℃之溫度。
在步驟226,於磊晶腔室中,磊晶矽層係形成在經過清潔之基板上。為了使用CVD製程以生長矽磊晶層,基板係放置在設定於升高溫度(例如約500℃~800℃)以及降低壓力狀態或大氣壓力下的磊晶腔室中。在維持於升高溫度及降低壓力狀態下之同時,將含矽氣體(例如單矽烷氣體或二氯矽烷氣體)供應至磊晶腔室中,並利用氣相生長以生長矽磊晶層,並形成具有與基板(半導體層生長在其上)相同之結晶定向的半導體層。製程可以在壓力介於約0.1托~約760托之間操作。用於沉積含矽薄膜之硬體包括購自加州聖克拉拉之應用材料公司(Applied Materials,Inc.)的Epi Centura RTM system以及Poly Gen RTM system。針對磊晶腔室之詳細描述可參照美國專利申請序號第11/767,619號,專利名稱為「300mm之模組式CVD EPI 反應器(Modular CVD EPI 300mm Reactor)」,於2007年6月25日申請,在此將其併入以做為參考。
方法200可以在包括有清潔腔室及磊晶腔室之群集式工具(cluster tool)中進行。在習知之配置中,基板在進行習知的清潔處理(例如濕式清潔處理)之後,必須等待一段時間,然後才可進入磊晶沉積腔室以形成磊晶層。等待的過程會影響基板表面的潔淨度,因而對晶圓與晶圓之間的製程結果造成影響。在一實施例中,步驟224完成以及接續之磊晶層沉積製程(即,步驟226)之間的時間係經過安排,藉此基板可以在完成鈍化處理之後立即轉移至磊晶腔室。使用控制器147以控制製程時間或時間排程,以增進製程的可重複性及裝置產量。在一實施例中,於步驟224之前可以加入排隊步驟(queuing step),以排除鈍化之後的等待。在另一實施例中,直到控制器147確認當步驟222及/或步驟224完成時,磊晶沉積室將會準備好接收基板之後,步驟226才會開始。
在一實施例中,步驟220在第一清潔腔室100中進行,步驟222在第二清潔腔室100中進行,以減少步驟220與步驟222對彼此之間的影響。在一實施例中,第一清潔腔室100進行步驟212~220,第二清潔腔室100進行步驟212~216及步驟222~224。
控制器147一般係設計成促進第一清潔腔室100及系統400(「第5圖」)之控制及自動化操作,並典型地包括中央處理單元(CPU)(圖中未示)、記憶體(圖中未示)及支援電路(或I/O)(圖中未示)。CPU可以為任一形式之電腦處理器,並可用於控制各腔室製程及硬體(例如:偵測器、馬達、流體輸送設備等)的工業設定,並監控系統及腔室製程(例如:基板位置、製程時間、偵測器訊號等)。記憶體係連接至CPU,並可以為容易存取之記憶體的一或多種,例如隨機存取記憶體(RAM)、唯讀記憶體(ROM)、軟碟、硬碟或是其他任何形式之數位存儲器,且可為本地的或是遠端的。軟體指令及數據可經過編碼並儲存在記憶體中,以提供CPU指令。支援電路亦以一習知方式而連接至CPU以支援處理器。支援電路可以包括高速緩衝記憶體(cache)、電源供應、時鐘電路、輸入/輸出電路、子系統(subsystem)等。可以由控制器147所讀取之程式(或電腦指令)係決定在基板上執行何種任務。較佳的,程式為可以由控制器147讀取之軟體,其包括用於產生及儲存至少有製程配方順序、基板位置資訊、各個受控部件的移動順序、製程控制、製程時間、時間排程、排隊步驟及其任意組合的編碼。
「第5圖」繪示根據本發明之一實施例的用於半導體處理之群集式工具400的平面視圖。群集式工具為一模組式的系統,其包括多個腔室,以在半導體製造過程中執行多個功能。群集式工具400包括中央傳輸室401,其透過一對加載鎖定室405而連接至前端環境404。工廠界面機械手408A、408B係設置在前端環境404中,並配置以將基板傳送於加載鎖定室405及複數個裝設在前端環境404之艙(pod)403之間。
複數個腔室407、408、409及410係裝設至中央傳輸室401以執行期望製程。中央機械手406設置在中央傳輸室401中,並配置以將基板傳送於加載鎖定室405及腔室407、408、409、410之間,或是腔室407、408、409、410之間。
在一實施例中,群集式工具400包括清潔腔室(例如「第1圖」的清潔腔室100)以及二磊晶腔室407、408。腔室410可以為清潔腔室,例如描述於「第1圖」之清潔腔室100。腔室410係配置以在磊晶生長製程之前用於清潔基板。腔室407、408為能夠進行磊晶生長製程之磊晶腔室。示範性之磊晶腔室係描述於美國專利申請序號第11/767,619號,專利名稱為「300mm之模組式CVD EPI反應器(Modular CVD EPI 300mm Reactor)」,於2007年6月25日申請,在此將其併入以做為參考。
群集式工具400可以用於執行上述之方法200。在處理過程中,待處理之基板到達群集式工具400的艙403。接著利用工廠界面機械手408A或408B而將基板由艙403傳送至真空相容的加載鎖定室405。接著傳輸室401中的中央機械手406拾取基板,而傳輸室401一般保持在真空狀態下。中央機械手406將基板裝載至清潔腔室410中,而清潔腔室410之內表面已透過所描述之方法200的步驟212、214、216而進行再生並塗覆。可以在清潔腔室410中對基板進行包括方法200之步驟220、222、224的清潔處理。中央機械手406接著自清潔腔室410拾取基板,並將其裝載至磊晶腔室407或408(視可利用之腔室而定)。磊晶層則在磊晶腔室407或408中生長於已經過清潔的基板上。
在一實施例中,群集式工具400係配置而包含有二清潔腔室100(或100a),其係位於腔室409及腔室410之位置(「第5圖」),而二磊晶腔室則位於腔室407或腔室408之位置。如上所提及,在此配置中,於磊晶腔室407或408中進行磊晶層沉積步驟226之前,係期望在一清潔腔室(例如腔室410)中執行步驟220,並且在另一清潔腔室(例如腔室409)中執行步驟222及224。
在另一實施例中,群集式工具包括電漿浸漬離子佈植(P3I)腔室。舉例來說,腔室409為P3I腔室,其係配置以將一或多個摻質佈植至基板上的磊晶層中。示範性的P3I腔室係描述於美國專利第6,939,434號,專利名稱為「具有離子分佈之磁性控制的外部激發超環面電漿源(Externally Excited Torroidal Plasma Source with Magnetic Control of Ion Distribution)」,以及美國專利第6,893,907號,專利名稱為「使用電漿浸漬離子佈植以製造絕緣層上覆矽結構(Fabrication of Silicon-on-Insulator Structure Using Plasma Immersion Ion Implantation)」,在此皆將其併入以做為參考。
惟本發明雖以較佳實施例說明如上,然其並非用以限定本發明,任何熟習此技術人員,在不脫離本發明的精神和範圍內所作的更動與潤飾,仍應屬本發明的技術範疇。
100,100a...腔室
102...基板
108...產生器
108A...匹配電路
109...線圈
110...幫浦
111...節流閥
122,133...處理區域
123...RF產生器
127...基座
128...壁
129...蓋
130...屏蔽/腔室蓋組件
131...基座板
132...氣體分配板
134...阻隔板
135...絕緣體
136...氣體通道
138...遮蔽環
140...屏蔽
141...孔洞
145...燈
147...控制器
150...氣體輸送系統
161...溫度控制器
162...基板支撐件
162A...基板支撐構件
191...RF源組件
193,196...處理腔室組件
194...基板支撐組件
200...方法
212,214,216,220,222,224,226...步驟
300...清潔腔室
301...腔室主體
302...處理區域
303...基板
303A...頂表面
304...基板支撐件
305...線圈
306...RF源
307...偏壓源
308...電漿
309...活化物種
310...離子
400...系統/群集式工具
401...傳輸室
403...艙
404...前端環境
405...加載鎖定室
406...機械手
408A,408B...機械手
407,408,409,410...腔室
為讓本發明之上述特徵更明顯易懂,可配合參考實施例說明,其部分乃繪示如附圖式。須注意的是,雖然所附圖式揭露本發明特定實施例,但其並非用以限定本發明之精神與範圍,任何熟習此技藝者,當可作各種之更動與潤飾而得等效實施例。
第1圖,概要繪示根據本發明之一實施例的清潔腔室之剖面側視圖。
第2A圖,概要繪示根據本發明之另一實施例的清潔腔室之剖面側視圖。
第2B圖,概要繪示根據本發明之一實施例的清潔腔室之剖面側視圖。
第3圖,繪示根據本發明之一實施例的用於清潔半導體基板之方法的流程圖。
第4圖,概要繪示清潔腔室之一部分剖面側視圖。
第5圖,概要繪示根據本發明之一實施例的群集式工具之平面視圖。
為便於了解,圖式中相同的元件符號表示相同的元件。某一實施例採用的元件當不需特別詳述而可應用到其他實施例。
200...方法
212,214,216,220,222,224,226...步驟
Claims (9)
- 一種處理一半導體基板的方法,包含:將一基板置於一處理腔室中的一處理區域內;將設置於該處理腔室中的該基板之一表面暴露於一含氧氣體,以在該表面形成一第一含氧層;將該基板自該處理區域移除;於一腔室部件的一表面上沉積一集除層,該腔室部件係設置於該處理區域內;將該基板置回該處理區域內;將該第一含氧層暴露於一電漿,以移除該第一含氧層之至少一部分,並暴露出該基板的該表面之至少一部分;且將該基板的該表面暴露於一含氧氣體,以在該基板的該表面形成一第二含氧層。
- 如請求項1之方法,其中形成該第一含氧層、移除該第一含氧層之至少該部分及形成該第二含氧層之步驟皆於該處理腔室中進行。
- 如請求項1或2之方法,進一步包含:移除該第二含氧層之至少一部分,以暴露出該基板的 該表面;且沉積一磊晶層於該基板的經暴露表面之至少一部分上。
- 如請求項3之方法,其中形成該第一含氧層、移除該第一含氧層之至少該部分、形成該第二含氧層及移除該第二含氧層之至少該部分之步驟皆於該處理腔室中進行。
- 如請求項4之方法,進一步包含:在將該基板置於該處理區域前,於一腔室部件的一表面上沉積一集除層,該腔室部件設置於該處理腔室之該處理區域內。
- 如請求項5之方法,其中該集除層包含一材料,該材料係選自由矽及鍺所組成之群組。
- 如請求項1之方法,其中該含氧氣體包含雙原子氧(O2 )。
- 如請求項1之方法,其中該含氧氣體包含臭氧(O3 )。
- 如請求項1之方法,其中形成該第一含氧層或形成該第 二含氧層之步驟包含將該基板暴露於紫外光(UV)。
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US8309440B2 (en) | 2012-11-13 |
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WO2009014894A1 (en) | 2009-01-29 |
JP2010534935A (ja) | 2010-11-11 |
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KR20100041786A (ko) | 2010-04-22 |
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US20110263103A1 (en) | 2011-10-27 |
CN101765900B (zh) | 2012-04-04 |
JP5599437B2 (ja) | 2014-10-01 |
KR20110120359A (ko) | 2011-11-03 |
CN102569136B (zh) | 2015-08-19 |
TWI368267B (en) | 2012-07-11 |
TW200915402A (en) | 2009-04-01 |
KR101087925B1 (ko) | 2011-11-28 |
US8008166B2 (en) | 2011-08-30 |
KR101389801B1 (ko) | 2014-04-29 |
TW201207920A (en) | 2012-02-16 |
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