TWI423404B - 積體電路封裝體及其製造方法 - Google Patents

積體電路封裝體及其製造方法 Download PDF

Info

Publication number
TWI423404B
TWI423404B TW096122029A TW96122029A TWI423404B TW I423404 B TWI423404 B TW I423404B TW 096122029 A TW096122029 A TW 096122029A TW 96122029 A TW96122029 A TW 96122029A TW I423404 B TWI423404 B TW I423404B
Authority
TW
Taiwan
Prior art keywords
die
package
heat sink
thermal
thermal interconnect
Prior art date
Application number
TW096122029A
Other languages
English (en)
Other versions
TW200818427A (en
Inventor
Sam Ziqun Zhao
Rezaur Rahman Khan
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of TW200818427A publication Critical patent/TW200818427A/zh
Application granted granted Critical
Publication of TWI423404B publication Critical patent/TWI423404B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16113—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

積體電路封裝體及其製造方法
本發明涉及積體電路(IC)器件封裝技術，更具體地說，涉及IC半導體管芯熱點的冷卻、IC封裝體的散熱及IC封裝體中的熱互連技術。
電信號是由流經製作在半導體襯底上的大型積體電路(IC)中的導線和電晶體的電流來承載的。電流所承載的能量中有一部分在電流流經IC過程中以熱量的形式耗散掉。電子半導體IC所產生的熱量也稱為功耗、功率耗散(power dissipation)或熱散耗(heat dissipation)。IC中產生的熱量P為動態功率PD 和靜態功率PS 之和，即：P=PD +PS =ACV2 f+VIleak
其中A是門電路活躍因數(gate activity factor)，C是所有門電路(gate)的總電容負載，V是峰至峰電源電壓擺幅，f是頻率，Ileak 是漏電流。靜態功率PS =VIleak ，是漏電流Ileak 導致的靜態功率耗散。有關靜態功率在Kim等人編寫的於2003年12月發表於IEEE Computer36(12)第68-75頁上的Leakage Current：Moore’s Law Meet Static Power中進行了詳細的描述，本文引用了其中的全部內容。
動態功率PD =ACV2 f，是IC器件電容負載充電和放電過程中的動態功率損耗。因此動態功耗正比於工作頻率和工作電壓的平方。靜態功耗正比於工作電壓。半導體IC技術中電晶體門電路尺寸(gate size)的縮小降低了單個電晶體的工作電壓和功率耗散。然而，由於產業一直遵 循摩爾定律發展，未來技術中晶片功率密度預期將進一步上升。1965年，英代爾共同創始人高登．摩爾預言晶片中電晶體的數量將每兩年增加一倍。除了晶片中電晶體數量會增加以外，依照2004年國際半導體技術發展藍圖(ITRS藍圖)(http：//www.itrs.net/Common/2004Update/2004_00_Overview.pdf)，工作頻率也將每兩年提高一倍。電壓降低會加大在雜訊容限控制方面的難度，因此對於130nm及更短的柵極長度(gate lengths)而言，工作電壓再也無法像過去一樣降低的那樣迅速。因此，晶片的功率耗散將繼續上升。詳情參見ITRS藍圖表6。隨著製造過程中更多的採用65nm技術，以及45nm技術的商業化，功耗問題目前已成為半導體工業中的主要技術問題。
IC晶片的另一特徵在於半導體管芯溫度的非均勻分佈。在片上系統(system-on-chip,SOC)設計中，單塊晶片上集成的功能模組越來越多。較高的功率密度區會產生非均勻溫度分佈現象，在晶片上導致“熱點(hotspots)”的出現，熱點也稱為“熱區(hot blocks)”。熱點在晶片上產生的溫差可達5℃至30℃左右。在Shakouri和Zhang編寫的“On-Chip Solid-State Cooling For Integrated Circuits Using Thin-Film Microrefrigerators”IEEE Transactionon Componentsand Packaging Technologies Vol.28,No.1,March,2005,pp.65-69中對熱點進行了詳細的描述，本文也引用了其中的全部內容。
由於載流子遷移率與溫度成反比，因此時鐘速度通常必須根據晶片上的最熱點來進行設計。因此，熱設計是 基於這些晶片上的熱點溫度來進行的。同時，若由於管芯(die)上的片上溫度變化而無法在IC管芯上得到統一的載流子遷移率，則將會導致信號速度的變化，並使得電路時鐘控制變得複雜。
過去，散熱器(包括內嵌(drop-in)散熱器、散熱片和散熱管)被用於提高IC封裝體的熱性能。2003年4月22日授權的名稱為“Semiconductor Package Having An Exposed Heat Spreader”的美國專利No.6552428中對散熱器實例進行了詳細的描述，本文也引用了其中的全部內容。由Zhao和Avedisian編寫的“Enhancing Forced Air Convection Heat Transfer From An Array Of Parallel Plate Fins Using A Heat Pipe”Int.J.Heat Mass Transfer,Vol.40,No.1,pp.3135-3147(1997)中對散熱管實例進行了詳細的描述。
例如，圖1A展示了管芯朝上塑膠球柵陣列封裝體(PBGA)封裝體100，其上集成了內嵌散熱器104。在封裝體100中，IC管芯102通過管芯粘合材料106貼裝在襯底110上，並與引線(wirebond)114相連。封裝體100可通過焊球108連接到印刷線路板(PWB)(未示出)上。內嵌式散熱器104設置在襯底110上，用於排出管芯102的熱量。塑封材料112將封裝體100密封起來，其中包括管芯102、引線114、部分或全部內嵌散熱器104和襯底110的部分或全部上表層。內嵌散熱器104通常由銅或者熱傳導性優於塑封材料112的其他材料製成。銅的熱傳導值在390W/m＊℃左右，塑封材料的熱傳導值為0.8W/m＊℃左右。
如圖1A所示的熱性能增強方法的原理是將熱量從整個晶片或整個封裝體中移除。通過對整個晶片不加區分地進行冷卻，將半導體溫度維持在工作上限以下。相對於晶片的其他部位，這些方法通常不足以降低熱點的溫度，或者在降低熱點溫度方面根本不起作用，因此晶片的工作仍受到熱點的限制。
例如，圖1B展示了矽管芯102的剖視圖，並且特別展示了未使用外部散熱片的PBGA中矽管芯102上的溫度分佈情況。管芯102上的溫差為13.5℃。圖1C展示的是在封裝體中增加了內嵌散熱器和散熱片之後，圖1B中管芯102的情況。在露出的內嵌散熱器上面貼裝大尺寸(45mm×45mm×25mm)外部鋁質pin-fin散熱片後，溫差仍為13.0℃。無論是內嵌散熱器還是外部散熱片，在降低由熱點引起的片上溫差方面都是無效的。
在本領域中還有一種冷卻方法，這就是使用電能來排出IC晶片熱量的主動式片上冷卻方法。例如，一些人建議在矽片上刻出微型管道，然後泵入液體冷卻劑使其圍繞半導體管芯迴圈流動，以帶走殘餘的熱量。由Bush編寫的於2005年7月20日發表在Electronic News上的“Fluid Cooling Plugs Directonto CMOS”(http：//www.reed-electronics.com/electronicnews/article/CA626959？nid=2019&rid=550846255)對液體冷卻方法進行了詳細的介紹，本文也引用了其中的全部內容。還可參見由Singer編寫的於2005年7月20日發表在Electronic News上的“Chip Heat Removal with Microfluidic Backside Cooling”，本文也引用了其中的全部內容。
此外，還開發出了使用薄膜熱電冷卻器(TEC)來提供主動片上冷卻的其他主動冷卻方法。與使用TEC的片上冷卻有關的內容在由Snyder等人編寫的“Hot Spot Coolingusing Embedded Thermoelectric Coolers”(22ND IEEE SEMI-THERM,Symposium,pp.135-143(2006))中進行了詳細的描述，本文也引用了其中的全部內容。
這些主動冷卻方法要求使用外部的昂貴流體循環或微冷卻系統，並且會增加封裝體的整體功耗，然而該功耗正是要必須消除的。此外，還需要在IC封裝體中集成獨立的電源來驅動流體泵或TEC系統。這些部件非常昂貴，而且還會降低部件的可靠性。由於這些解決方案通常都很昂貴，因此在對成本敏感的應用如消費類電子器件中，其使用受到限制。
上面描述的這些冷卻方法不足以和/或難於實現商業化應用，或者成本過高。因此，需要一種低廉可靠的系統和方法，可以選擇性的排出半導體管芯上熱區或熱點的熱量。
本發明涉及改進型積體電路(IC)封裝的方法、裝置及系統。
本發明的一方面，IC器件封裝體包括帶有接觸焊盤的IC管芯，該接觸焊盤位於IC管芯表面的熱點處。熱互連構件貼裝於熱點處。本發明的一方面，封裝體密封在塑封材料中。本發明的另一方面，管芯和熱互連構件彼此之間存在電連接。
本發明的一方面，封裝體還包括散熱器。該散熱器可 熱連接至熱互連構件。本發明的另一方面，該散熱器還電連接至熱互連構件。本發明的一方面，散熱器完全密封在塑封材料中。另一方面，散熱器至少部分地密封在塑封材料中。本發明的一方面，散熱器上包括被塗敷區域，其位置與熱互連構件相對應。
本發明的一方面，製造IC封裝體的方法包括：將IC管芯貼裝到襯底上，採用焊線鍵合工藝將管芯和襯底之間電互連，將至少一個熱互連構件連接到管芯的至少一個接觸焊盤上，將封裝體密封在塑封材料或其他密封材料中。本發明的另一方面，熱互連構件(或多個熱互連構件)有一部分裸露。在一實施例中，塑封材料被移除一整層以使熱互連構件外露。在另一實施例中，塑封材料中挖有一凹腔以使熱互連構件外露。
本發明的一方面，製造IC封裝體的方法還包括：將散熱器與外露的熱互連構件相連。一方面，散熱器與熱互連構件相對應部位有一處或多處塗敷材料。
本發明的另一方面，對管芯進行分析，以確定因管芯工作所引起的管芯表面至少一個熱點的位置。一方面，該分析包括繪製管芯的功能模組圖來確定一個或多個熱點。另一方面，該分析包括在管芯工作期間對管芯進行熱分析以定位一個或多個熱點。
本發明的另一方面，IC封裝體包括具有相對的第一和第二表面的襯底、安裝在所述襯底第一表面的IC管芯、散熱器，及連接襯底第一表面與散熱器表面的熱互連構件。
根據本發明的一方面，提供一種積體電路(IC)封裝 體，包括：帶有接觸焊盤的IC管芯，其中所述接觸焊盤位於IC管芯表面的熱點處，在管芯工作期間所述熱點處的溫度高於管芯表面的其他部位的溫度；及連接於所述接觸焊盤的熱互連構件。
在本發明的IC封裝體中，所述熱互連構件使得在管芯工作期間所述熱點處的溫度能夠降低為其他部位的溫度。
在本發明的IC封裝體中，還包括：密封管芯和至少一部分熱互連構件的塑封材料。
在本發明的IC封裝體中，所述熱互連構件電連接於和熱連接於所述接觸焊盤。
在本發明的IC封裝體中，還包括：熱連接於所述熱互連構件的散熱器。
在本發明的IC封裝體中，所述散熱器電連接於所述熱互連構件。
在本發明的IC封裝體中，還包括：密封所述管芯、熱互連構件和散熱器其中一部分的塑封材料。
在本發明的IC封裝體中，還包括：密封所述管芯、熱互連構件和散熱器的塑封材料。
在本發明的IC封裝體中，所述散熱器上與熱互連構件相連接部分的區域塗敷有粘合材料。
在本發明的IC封裝體中，所述塗敷材料為焊料。
在本發明的IC封裝體中，所述塗敷材料為環氧材料。
在本發明的IC封裝體中，還包括貼裝在管芯表面至少一個附加(additional)接觸焊盤上的至少一個附加熱互連構件，所述至少一個附加接觸焊盤位於管芯表面至少 一個附加熱點上。
在本發明的IC封裝體中，還包括：熱連接於所述第一熱互連構件和至少一個附加熱互連構件的散熱器。
在本發明的IC封裝體中，所述塑封材料的表面形成凹腔。
在本發明的IC封裝體中，還包括：所述散熱器安裝在凹腔內。
在本發明的IC封裝體中，熱互連構件部分外露出塑封材料表面。
在本發明的IC封裝體中，熱互連構件的外露表面為平面並與塑封材料表面共在一平面內。
在本發明的IC封裝體中，所述熱互連構件為焊球。
在本發明的IC封裝體中，所述焊球頂部被截掉。
在本發明的IC封裝體中，所述熱互連構件包括金屬。
在本發明的IC封裝體中，所述金屬包括金、銅、鋁、銀、鎳、錫或金屬合金。
在本發明的IC封裝體中，所述熱互連構件包括導熱環氧材料。
在本發明的IC封裝體中，所述熱互連構件包括內核材料及包覆該內核的鍵合材料。
根據本發明的一方面，提供一種製造IC封裝體的方法，包括以下步驟：(a)將IC管芯貼裝到襯底上，所述IC管芯表面的熱點處設置有接觸焊盤，在管芯工作期間所述熱點處的輻射熱量高於管芯表面其他部位的輻射熱量；(b)在管芯和襯底之間連接至少一條焊線； (c)將熱互連構件與所述接觸焊盤相連；(d)將管芯、至少一條焊線和至少一部分熱互連構件密封在密封材料中。
在本發明所述的方法中，還包括以下步驟：(e)至少裸露出一個熱互連構件。
在本發明所述的方法中，所述步驟(e)包括移除一整層塑封材料。
在本發明所述的方法中，所述步驟(e)包括移除一層塑封材料中的部分區域。
在本發明所述的方法中，還包括(e)將散熱器連接到熱互連構件。
在本發明所述的方法中，先執行步驟(e)後執行步驟(d)。
在本發明所述的方法中，先執行步驟(d)後執行步驟(e)。
在本發明所述的方法中，先執行步驟(e)後執行步驟(c)。
在本發明所述的方法中，先執行步驟(c)後執行步驟(e)。
在本發明所述的方法中，所述散熱器有一塗敷區域，其中步驟(e)包括：將所述塗敷區域貼裝到熱互連構件的表面。
在本發明所述的方法中，所述步驟(e)包括：將至少一個附加熱互連構件連接于管芯表面上的至少一個附加(additional)接觸焊盤上，所述至少一個附加接觸焊盤位於管芯表面至少一個附加熱點上。
在本發明所述的方法中，還包括：(e)將散熱器連接於所述第一熱互連構件和至少一個附加熱互連構件。
在本發明所述的方法中，還包括：(e)在塑封材料表面形成凹腔。
在本發明所述的方法中，還包括：(f)將散熱器安裝到所述凹腔中。
在本發明所述的方法中，所述熱互連構件為焊球，其中步驟(c)還包括：將焊球安裝到接觸焊盤上。
在本發明所述的方法中，所述熱互連構件為焊球，其中步驟(c)還包括：截去焊球的頂部。
在本發明所述的方法中，還包括：(e)對管芯進行熱分析以確定管芯上的至少一個熱點。
根據本發明的一方面，提供一種IC封裝體，包括：具有相對的第一和第二表面的襯底；安裝在所述襯底第一表面的管芯；散熱器；及將所述襯底第一表面連接到所述散熱器表面的熱互連構件。
在本發明的IC封裝體中，所述熱互連構件為焊球。
在本發明的IC封裝體中，還包括至少一個附加熱互連構件，其將襯底的第一表面連接到散熱器的表面。
在本發明的IC封裝體中，所述IC管芯帶有接觸焊 盤，其中所述接觸焊盤位於IC管芯表面的熱點處，在管芯工作期間所述熱點處的溫度高於管芯表面的其他部位的溫度；還包括將所述接觸焊盤連接到所述散熱器表面的第二熱互連構件。
在本發明的IC封裝體中，所述熱互連構件貼裝在襯底第一表面的導電體上。
在本發明的IC封裝體中，所述熱互連構件包括金屬。
在本發明的IC封裝體中，所述金屬包括金、銅、鋁、銀、鎳、錫或金屬合金。
在本發明的IC封裝體中，所述熱互連構件包括導熱環氧材料。
在本發明的IC封裝體中，所述熱互連構件包括內核材料及包覆該內核的鍵合材料。
根據本發明的一方面，提供一種製造IC封裝體的方法，包括以下步驟：(a)將管芯貼裝到襯底上；(b)將熱互連構件連接到所述襯底；(c)將管芯和至少一部分熱互連構件密封在密封材料中；(d)將熱互連構件連接到散熱器。
在本發明的方法中，先執行步驟(b)後執行步驟(d)。
在本發明的方法中，先執行步驟(d)後執行步驟(b)。
在本發明的方法中，所述步驟(b)包括：將第二熱互連構件貼裝到IC管芯表面熱點處的接觸焊盤，在管芯工作期間所述熱點處的輻射熱量高於管芯表面其他部位的輻射熱量； 在本發明所述的方法中，所述熱互連構件為焊球，其中步驟(b)還包括：將焊球安裝到襯底上。
在本發明所述的方法中，所述步驟(b)還包括：將多個熱互連構件連接到襯底上，其中所述步驟(d)包括：將所述多個熱互連構件連接到所述散熱器。
在下面將要進行的對本發明的詳細描述中，上述和其他部件、優勢和特徵將變得更加明顯。應注意的是，發明內容和摘要部分可能使用一個或多個實施例，但並未列出發明人可能補充的有關本發明的全部示範性實施例。
本文描述了有關IC器件封裝技術的方法、系統和裝置。更具體地說，描述了有關(1)IC半導體管芯上的熱點冷卻、(2)IC封裝體散熱和(3)IC封裝體熱互連技術的方法、系統和裝置。
本說明書中提及的“一個實施例”、“實施例”、“示例性實施例”等等指的是所描述的實施例可能包括某特定特徵、結構或特點，但是並不是每一個實施例都必定包括該特定特徵、結構或特點。此外，這些短語不一定指的是同一個實施例。還有，當結合某一實施例描述某特定特徵、結構或特點時，無論是否明確說明，可以認為本領域的技術人員能夠將這些特定特徵、結構或特點結合到其他實施例中。
本說明書公開了結合有本發明特徵的一個或多個實 施例。所公開的實施例僅僅是對本發明的舉例，本發明的範圍不局限於所公開的實施例，而由本申請的權利要求來定義。
此外，需要理解的是，本文中所使用的與空間方位有關的描述(例如“上面”、“下面”、“左邊”、“右邊”，“向上”、“向下”、“頂部”、“底部”等)僅僅是出於舉例解釋的目的，本申請中所介紹的結構的實際實現可以具有各種不同的方位或方式。
本發明的實施例中，為半導體管芯表面所需的部位提供更強的散熱性能。傳統器件中是對整個IC管芯和或IC封裝體進行冷卻，從而將IC管芯的峰值溫度控制在正常工作的閾值範圍內。與其不同的是，在本發明的實施例中，是將一個或多個熱互連構件連接到IC管芯表面的一處或多處。熱互連構件將管芯熱點上的熱量帶走。熱互連構件提供了一條或多條熱轉移途徑，透過密封管芯的塑封材料將熱量從IC管芯散發到外界環境中。
在另一實施例中，熱互連構件與散熱器相連。當熱互連構件與集成在封裝體中的散熱器相連時，熱互連構件起到傳熱橋梁的作用，以透過填充在散熱器和管芯之間空隙中的塑封材料傳遞熱量。熱互連構件與管芯相接觸處位置是可選擇的，例如通過使用晶片上功率密度分佈圖和或根據IC晶片布圖。
在實施例中，可在所有類型的IC封裝體內實施一個或多個熱互連構件，無論帶散熱器或不帶散熱器。諸如可在塑膠球柵陣列(PBGA)封裝、精細間距球柵陣列(FBGA)封裝、矩柵陣列(LGA)、針柵陣列(PGA)、後塑封 塑膠導線架式封裝(如扁平封裝(QFP)和無引線扁平封裝(QFN)及微導線架式封裝(MLP))中都可實施。例如，本發明的實施例可在密封于塑封材料中的所有焊線式封裝體中實施，以便於晶片上的熱點冷卻，同時改進器件的整體散熱性能。
在實施例中，熱互連構件可以是導熱焊球、焊塊(solder bumps)、柱、或其他導熱結構。在一些實施例中，熱互連構件還可以是導電體。為進行示例說明，以下採用焊球作為熱互連結構的實施例，來說明本發明的原理。當然，本發明的實施例還可以採用其他的熱互連結構。熱互連構件可以由金屬製成，如金、銅、鋁、銀、鎳或錫；可以由金屬混合物/合金製成，如焊料、低共熔混合物(錫、鉛)、無鉛焊料；可以導熱環氧材料或其他粘合劑材料製成；或可由其他導熱材料製成。在一個實施例中，熱互連構件可由內核材料外部覆蓋一層鍵合材料而構成，該鍵合材料可以是焊料、金、銀、環氧材料，或能夠將熱互連構件與半導體管芯上的接觸焊盤(contact pads)機械鍵合到一起的其他粘合材料。在一個實施例中，熱互連構件可以預先堆放在半導體管芯表面預定的接觸焊盤上。在另一個實施例中，一個或多個熱互連構件還連接至散熱器。
將具有高導熱性的熱互連構件貼裝到管芯上某些區域(稱為點或“區”)的接觸焊盤上，可將熱點(也稱為“熱區”)所產生的熱量從IC管芯直接導向外界環境，或通過導熱散熱器(如果有)導向外界環境。在一個實施例中，一個或多個熱互連構件的佈置取決於特定應用中半導體管芯的 功率分佈圖。在另一個實施例中，如果由於應用不同而導致功率分佈圖不同，同種半導體管芯可以在不同位置設置熱互連構件。例如，對於不同的應用，當管芯上不同的功能模組從“上電(power-p)”模式轉換為“下電(power-down)”模式時，會出現這種熱點位置不同的情況，反之亦然。
在一實施例中，對管芯進行分析以確定管芯表面的至少一個熱點，這些熱點是因管芯工作產生的。在一個實施例中，所述分析包括繪出管芯的功能模組分佈圖以確定一個或多個熱點。在另一個實施例中，所述分析包括在管芯工作期間進行熱分析/測量(例如，如圖1B和1C所示)，以對熱點進行定位。作為分析結果，可以確定出管芯表面的一個或多個熱點。與熱點處相比，熱點以外的其他區域的溫度相對偏低，因而散熱需求相對較少。因此，根據本發明的實施例，一個或多個熱點上都這接(機械/熱連接)有相應的熱互連構件，以將熱量從熱點處帶走，同時從較冷點/區帶走的熱量較少(因為熱互連構件並未直接安裝在較冷點/區)。採用這種方式，能夠使管芯表面的熱分佈更加趨於一致(對熱點進行冷，使其溫度與冷點/區處接近)。
例如，某些管芯在管芯表面設有外部鍵合焊盤(bond pad)(例如，排列為一個或多個環)，以便能夠在管芯外部接入(accessible)內部I/O信號。焊線(wire bonds)的一端連接於週邊鍵合焊盤，另一端連接于封裝體的襯底或封裝體的其他結構上。在一些實施例中，接觸焊盤(contact pad)連接于管芯表面中部區域的熱點上，但在一些實施例 中，一個或多個接觸焊盤可設置在管芯表面的週邊區域。
圖2A-2B所示為管芯朝上的BGA封裝體200的實施例的剖視圖。圖2C是封裝體200的側面截面圖。封裝體200中，IC管芯102通過多條焊線114電連接於導電體(例如迹線(trace)、鍵合手指等)，如襯底110上表面的迹線210。襯底110上表面的導電體通過襯底110(例如通過一個或多個導電和/或非導電層)電耦合到襯底110下表面的焊球焊盤(solder ballpads)上。焊球108與焊球焊盤相連接，且與電路板(如印刷電路板(PBC)或印刷線路板，圖2A-2C中未示出)相連。
如圖2A所示，管芯102的上表面設有至少一個接觸焊盤202，其上連接有至少一個熱互連構件。在一些實施例中，管芯102可以具有任意數量的接觸焊盤202，每一個都與一個熱互連構件208相連。接觸焊盤202位於管芯102的預先確定的熱點(未示出)上。管芯102熱點處的溫度一般比管芯102其他部分的溫度高，儘管如此，接觸焊盤202也可設置在管芯102的非熱點處。塑封材料112密封住封裝體200。在圖2B-2C的實施例中，熱互連構件208被塑封材料112完全密封。
圖2D-2E示出了管芯朝上的BGAIC封裝體250實施例的透視圖。圖2F示出了封裝體250的截面圖。除了塑封材料112未將熱互連構件208的上表面252密封住之外，封裝體250與封裝體200相似。在一個實施例中，塑封材料112的上面一層被移除以使互連構件208的表面252外露。在該實施例中，互連構件208的頂部被切掉，以形成平坦外露的互連構件208表面252，並且表面 252與塑封材料112的上表面平齊。表面252也可稱為“熱接觸焊盤”。封裝體250的外露表面252可用於電連接(例如接地、電源或信號)到管芯102。有各種方法可將嵌在封裝體塑封材料內的球狀體焊料截去頂部(truncate)，包括下面將討論的圖5E中的方法。申請號為60/799,657，申請日為2006年5月12日、名稱為“Interconnect Structureand Formation for Package Stacking of Molded Plastic Area Array Package”的美國臨時專利申請中描述有焊球截去頂部並外露在塑封材料上表面的例子，此處全文引用其內容。
在圖2A-2E所示的實施例中沒加裝散熱器。與加裝散熱器(如以下所描述的)的封裝體相比，其熱性能有一定的差距。但是，即使在不加裝散熱器的情況下，對於特定的應用由於熱互連構件替代了塑封材料112使得結到管殼(junction-to-case)熱阻減小，因而熱性能的改進也是很顯著的。
例如，在一實施例中，熱互連構件208是焊球，由於一般IC封裝體焊球(無鉛和錫/鉛)的導熱係數介於50~60W/m＊℃，比一般塑封材料112的導熱係數(例如約為0.8W/m＊℃)高許多倍，因而結到管殼熱阻降低。此外，構成熱互連構件208的焊球貼裝到IC管芯102上，使導熱區從管芯102表面延伸至塑封材料112的上表面。對於具有小尺寸管芯102的封裝體而言，當焊球替代了管芯102上表面相對來說較大面積的塑封材料112時，從而為熱擴散提供了穿過封裝體250上表面的散熱通道，使得熱性能的改進尤其顯著。另外，當封裝體(如 200和250)的頂部安裝有外部散熱器，如散熱片或金屬板，封裝體的熱性能會進一步改進。有關實施例將在下一節描述。
在一些實施例中，熱互連有助於半導體管芯預選位置處的能量/熱量的擴散。在一個實施例中，IC管芯上至少貼裝有一個熱互連構件，該熱互連構件連接到內嵌或貼裝在封裝體中或上的至少一個散熱器。在一實施例中，散熱器密封在塑封材料中。散熱器可外露出封裝體的上表面，以將熱量擴散到周圍環境中，包括安裝散熱片。作為選擇，散熱器也可以完全密封在塑封式IC封裝體的塑封材料內。
在一些實施例中，為鎖定塑封材料(與封裝材料扣合)、擴散熱量、減小應力和或改進可靠性，散熱器可以設計成各種形狀，包括孔、槽或其他表面結構。散熱器可由金屬材料製成，諸如銅、銅合金、常用于導線架式封裝體的其他材料(C151、C194、EFTEC-64T、C7025等)、鋁、其他金屬或金屬/合金的組合物、和或導熱非金屬材料。散熱器可以是以柔性帶材如聚酰亞胺帶材為基底，在聚酰亞胺薄膜上碾壓一層或多層金屬箔。散熱器可以由導熱但不導電的材料製成，如導熱陶瓷，或散熱器也可以具有導電性。
在一個實施例中，集成散熱器的下表面和管芯上表面之間的距離小於焊線的線弧高度(loop-height)(即從焊線弧頂到IC管芯表面的距離)。在這一實施例中，散熱器的尺寸可能受到IC管芯上表面兩側焊線焊盤之間空間的限制。
在另一實施例中，散熱器下表面和管芯上表面之間的距離大於焊線的線弧高度。在這種情況下，散熱器的尺寸不受IC管芯表面兩側焊線焊盤之間距離的限制。即使在管芯表面的四個邊緣都有焊線互連的情況下，散熱器的尺寸也可以大於管芯的尺寸。較大的散熱器由於散熱面積大，可以提高熱點冷卻的效率。為利於熱連接，減小IC管芯和集成散熱器之間的間距，可採用面積小於管芯面積的底座，其向IC管芯上表面延伸。作為選擇，熱互連構件可以設置在散熱器的底部，該散熱器熱連接于IC管芯上貼裝的相應的熱互連構件。
在一個實施例中，集成散熱器完全密封在塑封材料中。在另一個實施例中，集成散熱器透過塑封材料頂部部分外露，與圖1A所示的內嵌式散熱器104相似。
在一個實施例中，熱互連構件具有導電性，一個或多個熱互連構件可以連接於地電位或IC管芯的電源，以便從散熱器上提供一條電流和片上電源的替代電路(to provide an alternative route for current or on-chip power delivery from the heat spreader)。這種配置的實施例在申請號為10/952,172、申請日為2004年9月29日、名稱為“Die Down Ball Grid Array Packages And Method for Making Same”的美國專利申請中進行了描述，此處全文引用。這種配置可以有效地縮短晶片上電源電流路徑的長度，從而降低IC管芯內的IR壓降。
在一實施例中，散熱器的尺寸小於封裝塑封體的尺寸，如圖3A-3C所示。作為選擇，散熱器的尺寸也可以與封裝塑封體尺寸完全相同，或大於封裝塑封體。有關 這方面的實施例在申請號為10/870,927、申請日為2004年6月21日、名稱為“Apparatus and Method for Thermal and Electromagnetic Interference(EMI)Shielding Enhancement in Die-Up Array Packages”的美國專利申請中進行了描述，此處全文引用。
以下幾節給出在不同IC封裝體中實施的本發明的幾個實施例。附圖及其描述只是以實施例的形式對本發明的原理進行示例說明，其目的並不是對本發明進行限制。以下所描述的許多實施例包括散熱器。但是，如圖2A-2F所示，本發明的某些實施例中不帶集成散熱器。
圖3A-3E示出了帶有集成散熱器302的塑封式塑膠精細間距球柵陣列(BGA)封裝體，其中散熱器至少部分地被塑封材料112覆蓋。在圖3A-3E所示的實施例中，各個封裝體的散熱器設置各不相同。
例如，圖3A所示的封裝體300帶有一個平板形散熱器302，其以部分嵌入的方式集成在封裝體300中。散熱器302具有外露(未被塑封材料112覆蓋)的平坦上表面304。在封裝體300中IC管芯102借助一條或多條焊線114電連接於襯底110。一個或多個熱互連構件208貼裝在管芯102的上表面。塑封材料112將管芯102、焊線114、襯底110上表面及熱互連構件208密封住。在一實施例中，塑封材料112可採用模塑工藝、單切技術(saws in gelation technique)或其他成型工藝在襯底110上成型。散熱器302的平坦下表面306與每一個熱互連構件208的頂部相連。在圖3A中，散熱器302被塑封材料112部分密封。散熱器302的下表面和外周邊與塑封材料112接 觸，而散熱器302的上表面304未被塑封材料覆蓋。散熱器302的上表面304與塑封材料112的上表面平齊。
在實施例中，散熱器302可部分或全部密封在塑封材料112中。此外，雖然圖3A所示的為平板形，在其他實施例中，散熱器302也可以是其他形狀，包括規則或不規則形狀、平板形或非平板形。
圖3B所示的封裝體350與封裝體300相似，只是散熱器302是以部分嵌入方式集成在封裝體300中，且散熱器302為非平板狀。在圖3B中，散熱器302類似於帽狀，其朝向管芯102的一面為一凹腔。散熱器302的下表面306與每個熱互連構件208的頂部相連。散熱器302上表面304的平坦部分308未被塑封材料112覆蓋，其餘部分被塑封材料112覆蓋。例如，散熱器302外沿的傾斜側壁部分310(其從散熱器302的平坦部分延伸到外部)被塑封材料112覆蓋。
圖3C所示的封裝體360帶有一個以非嵌入方式集成在封裝體360上的平板狀的散熱器302(與圖3A相似)。散熱器302的下表面306與每個熱互連構件208的頂部相連。散熱器302貼裝在塑封材料112平坦的上表面。這樣，散熱器302的下表面306與塑封材料112相接觸，而其餘部分未與塑封材料112相接觸。因而，在圖3C所示的實施例中，可以在塑封材料112完成加注後再將散熱器302貼裝到封裝體360中。
圖3D所示的封裝體370與封裝體360相似，但是散熱器302為非平板狀。散熱器302具有一平坦的中部區域312，其周圍連接有多條導線(lead)314，在將封裝體370 安裝到電路板上時，使用這些導線將散熱器302與電路板(圖3D中未示出)相連接。中部區域312的下表面306貼裝在熱互連構件上。散熱器302上的每一條導線314都從中部區域312在肩部朝向電路板向下彎曲。每條導線314的一端都有一足部372，其從散熱器302向外彎曲，便於其安裝到電路板上，如直接熱和/或電連接於電路板。
圖3E所示為封裝體380，其中熱互連構件208是被截去頂部的焊球，並有外露的表面252，與圖2F所示的設計相似。此外，散熱器302上對應于熱互連構件208的位置處設有焊盤382。焊盤382是在安裝到表面252之前，預先採用材料386堆積(deposit)的。預先堆積的焊盤382可以採用導熱材料386(諸如可將散熱器302機械連接到熱互連構件208的焊料或環氧材料)塗敷。在一個實施例中，塗敷材料386也具有導電性。在進行回流焊、固化(curing)或其他貼裝工藝期間，散熱器302被連接到熱互連構件208。另外，在一個實施例中，可以選擇在製造完成後，在散熱器302下方，散熱器302的下表面306和塑封材料112的上表面之間留一點兒空隙384。塗敷材料386使得散熱器302處於塑封材料112上方的一段距離處，以此來提供空隙382。
圖4A-4B示出了塑封塑膠球柵陣列(PBGA)封裝的實施例，其中具有至少一個連接于集成散熱器302的熱互連構件208。
圖4A所示為根據本發明實施例的封裝體400，其包含部分嵌入的散熱器302。在圖4A中，IC管芯102通過 焊線114電連接於襯底110。管芯102與散熱器302之間連接有一個或多個熱互連構件208。此外，熱互連構件208被截去頂部，與圖2F中相關部分的描述相似，散熱器302的下表面306貼裝在熱互連構件208的上表面252。塑封材料112採用模塑工藝成型，並密封住封裝體400的大部分，包括管芯102、焊線114、襯底110的部分上表面、散熱器302除平坦頂部402以外的部分。
在圖4A中，散熱器302為帽狀，有一個朝向管芯102的凹腔474，凹腔474包圍了熱互連構件208、管芯102及襯底110上表面的焊線114。帽狀散熱器302具有平坦的頂部，向外傾斜的側壁從平坦頂部向下延伸並包圍著凹腔474，外沿部分404圍繞著側壁的底部邊緣。散熱器302外沿部分404的下表面借助粘合材料406(諸如環氧、粘合劑、焊料或其他粘合劑)貼裝在襯底110的上表面。
散熱器302可以是規則或不規則形狀、平板狀或非平板狀。例如，圖4B所示的封裝體450與圖4A的封裝體400相似，除了散熱器302為平板狀之外。散熱器302的上表面未被塑封材料112密封。散熱器302的外邊緣被塑封材料112密封。散熱器302的下表面306嵌在塑封材料112中，並貼裝于熱互連構件208的上表面252。
本發明的實施例可在許多種IC封裝類型中實施。例如，圖5A-5C示出了在導線架式封裝體上集成有至少一個熱互連構件208和散熱器502的實施例。例如，圖5A所示的封裝體500中管芯102貼裝在導線架516的管芯焊盤504上。導線架516包括多條導線518和管芯焊盤504。管芯102借助一條或多條焊線514電連接于管芯焊 盤504和/或導線518。此外，借助一條或多條焊線514導線518可以電連接于管芯焊盤504。散熱器502為帽狀，具有一朝向管芯102的凹腔520。管芯102和散熱器502的凹腔520下表面522借助一個或多個熱互連構件208相連，該熱互連構件208可以是截去頂部的也可以是未截去頂部的。
封裝體500被密封在塑封材料112中，塑封材料112填充在散熱器502與管芯102之間的空隙中，包括凹腔520中。散熱器502的外沿部分524的下表面安裝在導線架516上。如圖5A所示，為改進機械連接，外沿部分524的下表面和導線架516可以設計成互鎖形式。
除散熱器502為平板狀因而未安裝到導線架516上之外，圖5B所示的封裝體550與圖5A的封裝體500相似。
除了散熱器502完全嵌在塑封材料112中之外，圖5C所示的封裝體560與圖5B的封裝體550相似。
需注意的是雖然圖5A-5C所示的全部為管芯朝上(即當安裝到電路板上時，管芯102的電路一側是背離電路板的)的設置，但這只是出由舉例說明的目的。本發明的實施例也可以應用到管芯朝下的導線架式封裝。
在另一實施例中，可在不加裝集成散熱器的情況下，在導線架式封裝中採用一個或多個熱互連構件208，與圖2A-2F所示BGA封裝中採用的方式相似。
微導線架封裝(MLP)或微導線架(MLF)1C封裝，其中集成有至少一個熱互連構件208和散熱器602。例如，圖6A所示的封裝體600中，管芯102貼裝在焊盤604上。管芯102借助一條或多條焊線614電連接到管芯焊盤604 和/或導線616上。散熱器602為帽狀，具有朝向管芯102的凹腔620。管芯102和散熱器602在凹腔620中的下表面622通過一個或多個熱互連構件208相連，這些熱互連構件208可以是截去頂部的也可以是未截去頂部的。
封裝體600被密封在塑封材料112中，塑封材料112填充在散熱器602與管芯102之間的空隙中，包括凹腔620中。散熱器602的外沿部分624的下表面安裝在導線架616上。如圖6A所示，為改進機械連接，外沿部分524的下表面和導線架616可以設計成互鎖形式。
除散熱器602為平板狀因而未安裝至導線616之外，圖6B所示的封裝體650與圖6A的封裝體600相似。
圖7A示出了本發明的製造工藝實施例的流程圖700。圖7B-7D示出了製造過程中各階段的BGA封裝體，以下結合圖7B-D對流程700進行描述。本領域的技術人員根據本發明的教導可知，流程700可用于製造其他封裝類型，可以按照其中的步驟進行，也可以更改其中的步驟。在流程700中安裝散熱器(步驟710)是可選步驟，可根據是否要加裝散熱器而決定是否進行該步驟。
底上。例如管芯可以是圖2A-2C所示的管芯102，可採用管芯粘合材料106將管芯貼裝到襯底上。管芯粘合材料106可以是任何類型的合適的粘合材料，諸如環氧和或薄膜粘合劑、或其他類型的粘合材料或貼裝機制。
在步驟702中，將熱互連構件安裝到管芯的上表面。例如，將一個或多個熱互連構件208安裝到管芯的接觸焊盤202上，如圖2A-2C所示。圖7B示出了步驟701和702之後的完成了部分裝配的封裝體750的示意圖。 在一個實施例中，當熱互連構件208為焊球時，採用傳統的將焊球安裝到GBA封裝體底部的焊球安裝工藝，將焊球安裝到管芯102上。
在步驟704中，將焊線連接到管芯和襯底之間。例如可以採用焊線鍵合工藝借助焊線114將管芯102電連接至襯底110。圖7C所示為步驟701-704之後的完成了部分裝配的封裝體760。
在步驟706，用塑封材料對封裝體進行密封。例如，塑封材料可以是塑封材料112。如圖2A-2C所示，塑封材料112將管芯102、焊線114、至少一個熱互連構件208及全部或部分襯底110密封住。圖7D所示為步驟701-706之後的完成了部分裝配的封裝體770。
在可選步驟708中，將塑封材料的頂層部分或全部移除。例如，在一實施例中，移除一層塑封材料，因而一個或多個熱互連構件208的頂部被截去(即熱互連構件208的頂部與塑封材料112的頂層中的一部分或整個頂層一起移除)。
圖7A所示的步驟708選擇性地包括步驟708a和708b之一。在可選步驟708a中，移除塑封材料的整個頂層，正如圖2F所示。圖7E示出了步驟708a實施方式的示例，其中採用打磨工具702打磨掉塑封材料的整個頂層，從而打磨掉熱互連構件208的一部分，並使熱互連構件208的表面252外露。
在可選步驟708b中，在塑封材料中形成凹腔。圖7F示出了步驟708b的實施方式的示例。如圖7F所示，採用到刨(routing)工具704在塑封材料512的頂層中部刳刨 出一凹腔706。在形成凹腔706的過程中，刳刨工具704刳刨掉凹腔706下方的部分熱互連構件208，以使位於熱互連構件208中部的表面252外露。
在一實施例中，在步驟708、708a和708b中也可以採用與上述方法不相同的其他的材料移除方法，以移除頂部塑封材料從而截去和/或外露一個或多個熱互連構件。其他表面加工方法諸如刻蝕或鐳射加工方法可用於移除塑封材料並使熱/電互連構件外露。
如上所述，步驟708(及其子步驟708a和708b)是可選的。在另一實施例中，不進行步驟708，塑封材料的頂層未被移除和/或不形成凹腔。
在可選步驟710，將散熱器安裝到封裝體上。例如，該散熱器可以是上述散熱器302、502、602或702。在一個不帶散熱器的封裝實施例中，不執行可選步驟710。當執行步驟710時，散熱器被連接至一個或多個外露的熱互連結構上，其中這些熱互連構件可以是截去頂部的，也可以是未截去頂部的。
需注意的是，流程700中步驟可以不按照圖7A中所示的順序進行。例如，步驟704可以在熱互連構件貼裝到管芯(步驟702)之前執行。
圖8A示出了將散熱器安裝到IC封裝體的工藝流程800。圖8B-8C中示出了製造過程中各階段的BGA封裝體的示意圖，以下結合圖8B-8C對流程800進行描述。本領域的技術人員根據本發明的教導可知，流程800可用于製造其他封裝類型，可以按照其中的步驟進行，也可以更改其中的步驟。
流程800開始於步驟802。在步驟802中，接納帶有一個或多個預先進行過塗敷的焊盤的散熱器。例如，散熱器為圖8B中所示的散熱器302。圖8B示出了完成了部分裝配的封裝體850和散熱器302。散熱器302帶有焊盤，其上塗有塗敷材料386的。塗敷材料386可以是導熱物質，例如焊料或環氧材料。
在步驟804中，將散熱器放置在封裝體上。例如，如圖8C所示，散熱器302被放置在完成了部分裝配的封裝體860上，從而塗敷材料386與熱互連構件252的表面相接觸。
在步驟806中，散熱器的底部與封裝體連接到一起。例如可採用回流焊或固化(curing)工藝將散熱器連接到封裝體上。回流焊或固化(curing)工藝使得散熱器302連接到完成了部分裝配的封裝體860上形成封裝體870，如圖8C所示。回流焊工藝適用于以塗敷的焊料作為塗敷材料386的實施例，而固化工藝適用于塗敷材料386為環氧材料的實施例。裝配後，已完成的封裝體在散熱器302與塑封材料112之間有一間隙384。
圖9A所示為本發明製造工藝實施例的流程900。圖9B-9D中示出了製造過程的各個階段中的BGA封裝體，流程900將結合圖9B-9D進行描述。本領域的技術人員根據本發明的教導可知，流程900可用于製造其他封裝類型，可以按照其中的步驟進行，也可以更改其中的步驟。
流程900開始於步驟902。在步驟902中，將管芯安裝到襯底上。例如管芯是圖3A所示的管芯102，其被安 裝到襯底110上。
在步驟904中，用焊線連接管芯和襯底。例如，如圖3A所示，可以採用焊線鍵合工藝借助焊線114將管芯102電連接至襯底110。
在步驟906中，將熱互連構件安裝到管芯的上表面。例如，將一個或多個熱互連構件208安裝到管芯的接觸焊盤202上。圖9B示出了步驟902、904、906之後的完成了部分裝配的封裝體920的示例。在一個實施例中，採用傳統的將焊球安裝到GBA封裝體底部的焊球安裝工藝，將熱互連構件208安裝到管芯102上。
在步驟908中，將散熱器安裝到熱互連構件上。例如，如圖3A所示，散熱器302被安裝在熱互連構件208上。在另一實施例中，散熱器302可以帶有預先進行過塗敷的焊盤，如圖3E所示。圖9C示出了步驟902-908後的完成了部分裝配的封裝體930的示例。
在步驟910中，將封裝體密封在塑封材料中。例如，如圖3A所示，塑封材料112覆蓋住管芯102、焊線114、至少一個熱互連構件及全部或部分襯底。圖9D示出了步驟902-910後的部分裝配的封裝體940的示例。
需注意的是，流程900中步驟可以不按照圖9A中所示的順序進行。例如，步驟906可以在步驟704之前執行。
到散熱器上。圖9E所示為本發明製造工藝實施例的流程950。圖9F-9H中示出了製造過程的各個階段中的BGA封裝體，流程950將結合圖9F-9H進行描述。本領域的技術人員根據本發明的教導可知，流程950可用于 製造其他封裝類型，可以按照其中的步驟進行，也可以更改其中的步驟。
流程950開始於步驟952。在步驟952中，將管芯安裝到襯底上。例如管芯是圖3A所示的管芯102，其被安裝到襯底110上。
在步驟954中，用焊線連接管芯和襯底。例如，如圖3A所示，可以採用焊線鍵合工藝借助焊線114將管芯102電連接至襯底110。
將一個或多個熱互連構件208安裝到散熱器302的下表面306，如圖9F所示。在一個實施例中，採用傳統的將焊球安裝到GBA封裝體底部的焊球安裝工藝，將熱互連構件208安裝到散熱器302上。在另一實施例中，散熱器302帶有預先進行過塗敷的焊盤(圖9F中未示出)。
在步驟958中，將熱互連構件安裝到管芯的上表面。例如，將熱互連構件208安裝到管芯102上。圖9G示出了步驟958之後的完成了部分裝配的封裝體980的示例。
在步驟960中，將封裝體密封在塑封材料中。例如，採用塑封材料112覆蓋住管芯102、焊線114、熱互連構件208及全部或部分襯底110。圖9H示出了步驟952-960後的完成了部分裝配的封裝體990的示例。
在一些實施例中，在積體電路封裝中，可使用熱互連構件將散熱器與襯底連接起來。例如，圖10A-10C是根據本發明實施例的BGA封裝體的示意圖，所述封裝體中帶有與封裝體襯底熱連接的散熱器。圖10A-10C的實施例僅是出於舉例的目的。在其他實施例中，其他類型的IC封裝體也可以採用熱互連構件將散熱器與襯底相連。 另外，當熱互連構件為焊球時，這些焊球可以載去項部也可以不截去頂部。其他材料，諸如銅、金、其他金屬和/或金屬合金，包括本文中其他部分提及的材料或其他已知材料，也可用作熱互連構件。
圖10A-10C所示的封裝體與圖3A所示的封裝體300大致相似，以下僅對一些不同之處進行描述。圖10A所示的封裝體1000具有多個熱互連構件208，其將散熱器302的下表面306連接至襯底110的上表面1002。在一個實施例中，熱互連構件208在襯底110與散熱器302之間提供一條熱傳導路徑，使得管芯102上產生的、並傳遞到襯底110的熱量能夠轉移到散熱器302上。
熱互連構件208可以在襯底110的非導電位置處和/或導電位置處連接到襯底110上表面1002。例如，熱互連構件208的下表面可以貼裝到襯底110的阻焊層或絕緣層的表面，其通常不具有導電性，且導熱性能相對較低。在另一例子中，熱互連構件208的下表面可以貼裝到襯底110的導電體1004(如迹線(trace)、鍵合手指、接觸焊盤、接地/電環(powerring)等)上，該導電體1004通常由金屬製成(例如金屬箔、塗敷層等)，諸如銅、鋁、金、錫、鎳、銀、其他金屬或金屬的組合物/合金。
在一個實施例中，熱互連構件208將襯底110的導電體1004連接到散熱器302，當熱互連構件208是導電體時，該熱互連構件208可以提供通向散熱器302的導電路徑。
如圖10A所示，散熱器302的面積小於塑封材料112上表面的面積，因而塑封材料112上表面的外周未被散 熱器302覆蓋。除了散熱器302的面積與塑封材料112的上表面的面積相同之外，圖10B所示的封裝體1010與圖10A的封裝體1000相似。
實施例中，可以使用任意數量的熱互連構件208將散熱器302連接到襯底110上，包括使用熱互連構件208的陣列。例如，在圖10A和10B中，一對熱互連構件208環圍繞著襯底110上表面的管芯102。需要時，可使用任意數量的這種熱互連構件208環。除了襯底110上表面的管芯102的周圍環繞著單一熱互連構件208環之外，圖10C所示的封裝體1020與圖10B的封裝體1010相似。
在一些實施例中，可以對流程700、900和950進行更改，使其包括形成/貼裝熱互連構件至散熱器和/或襯底的步驟，用於將散熱器連接於襯底。
要強調的是，雖然圖10A-10C所示的熱互連構件208連接於襯底和散熱器302之間，封裝體1000、1010、1020也可以包括將管芯102上表面連接到散熱器302的熱互連構件208。
本發明是通過一些實施例進行描述的，應當理解，其目的僅在於舉例說明，而沒有限制性。本領域的技術人員知悉，在不脫離本發明的精神和範圍情況下，在形式上和細節上還可做各種改變。因此，本發明的保護範圍不應當僅局限於以上描述的任一實施例，而應該依照權利要求及其等同來限定。
100‧‧‧管芯朝上塑膠球柵陣列封裝體(PBGA)封裝體
102‧‧‧IC管芯
104‧‧‧內嵌散熱器
106‧‧‧管芯粘合材料
108‧‧‧焊球
110‧‧‧襯底
112‧‧‧塑封材料
114‧‧‧引線(wirebond)
200‧‧‧管芯朝上的BGA封裝體
210‧‧‧跡線
202‧‧‧接觸焊盤
208‧‧‧熱互連構件
250‧‧‧管芯朝上的BGAIC封裝體
252‧‧‧上表面
300‧‧‧塑封式塑膠精細間距球柵陣列(BGA)封裝體
302‧‧‧集成散熱器
304‧‧‧平坦上表面
306‧‧‧下表面
308‧‧‧平坦部分
310‧‧‧傾斜側壁部分
312‧‧‧中部區域
314‧‧‧導線(lead)
350‧‧‧封裝體
360‧‧‧封裝體
370‧‧‧封裝體
372‧‧‧足部
380‧‧‧封裝體
382‧‧‧焊盤
384‧‧‧空隙
386‧‧‧塗敷材料
400‧‧‧封裝體
402‧‧‧平坦頂部
404‧‧‧外沿部分
406‧‧‧粘合材料
474‧‧‧凹腔
450‧‧‧封裝體
500‧‧‧封裝體
502‧‧‧散熱器
504‧‧‧管芯焊盤
514‧‧‧焊線
516‧‧‧導線架
518‧‧‧導線
520‧‧‧凹腔
522‧‧‧下表面
524‧‧‧外沿部分
550‧‧‧封裝體
560‧‧‧封裝體
600‧‧‧封裝體
602‧‧‧散熱器
604‧‧‧焊盤
614‧‧‧焊線
616‧‧‧導線
620‧‧‧凹腔
622‧‧‧下表面
624‧‧‧外沿部分
650‧‧‧封裝體
1000、1010、1020‧‧‧封裝體
1002‧‧‧上表面
1004‧‧‧導電體
圖1A所示為傳統IC封裝的示意圖；圖1B和圖1C所示為圖1A中傳統IC封裝採用傳統 冷卻方法後管芯溫度分佈的示意圖；圖2A和2B是根據本發明實施例的球柵陣列(BGA)封裝的剖視圖；圖2C是根據本發明實施例的BGA封裝的截面示意圖；圖2D是根據本發明實施例的球柵陣列(BGA)封裝的透視圖；圖2E是根據本發明實施例的球柵陣列(BGA)封裝的剖視圖；圖2F是根據本發明實施例的BGA封裝的截面示意圖；圖3A-圖3E是根據本發明實施例的帶有散熱器的密間距球柵陣列(FBGA)封裝的截面示意圖；圖4A-圖4B是根據本發明實施例的帶有散熱器的塑膠球柵陣列(PBGA)封裝的截面示意圖；圖5A-圖5C是根據本發明實施例的帶有散熱器的引線架式封裝的截面示意圖；圖6A-圖6B是根據本發明實施例的帶有散熱器的無引線扁平(QFN)封裝的示意圖；圖7A是根據本發明實施例的裝配IC封裝體的示例性步驟的流程圖；圖7B-圖7F是根據本發明實施例，在各個裝配階段的IC封裝體的截面圖，本實施例中，先密封後再安裝散熱器；圖8A是根據本發明實施例的裝配IC封裝體的示例性步驟的流程圖；圖8B-圖8C是根據本發明實施例，在IC封裝體上安 裝散熱器的截面圖；圖9A根據本發明實施例的裝配IC封裝體的示例性步驟的流程圖；圖9B-圖9D是根據本發明實施例，在各個裝配階段的IC封裝體的截面圖，本實施例中，先安裝散熱器後再密封；圖9E是根據本發明實施例的裝配IC封裝體的示例性步驟的流程圖；圖9F-圖9H是根據本發明實施例，在各個裝配階段的IC封裝體的截面圖，本實施例中，先安裝散熱器後再密封；圖10A-10C是根據本發明實施例，帶有熱連接到封裝體襯底的散熱器的BGA封裝體的截面圖。
102‧‧‧IC管芯
110‧‧‧襯底
112‧‧‧塑封材料
114‧‧‧引線(wirebond)
208‧‧‧熱互連構件
300‧‧‧塑封式塑膠精細間距球柵陣列(BGA)封裝體
302‧‧‧集成散熱器
304‧‧‧平坦上表面
306‧‧‧下表面

Claims (8)

  1. 一種積體電路(IC)封裝體，其特徵在於，包括：帶有接觸焊盤的IC管芯，其中所述接觸焊盤位於IC管芯表面的熱點處，在管芯工作期間所述熱點處的溫度高於管芯表面的其他部位的溫度；連接於所述接觸焊盤的熱互連構件；密封管芯和至少一部分熱互連構件的塑封材料，其中該塑封材料至少裸露出一個熱互連構件。
  2. 如申請專利範圍第1項所述的IC封裝體，其中，所述熱互連構件使得在管芯工作期間所述熱點處的溫度能夠降低為其他部位的溫度。
  3. 如申請專利範圍第1項所述的IC封裝體，其中，所述熱互連構件電連接於和熱連接於所述接觸焊盤。
  4. 一種製造IC封裝體的方法，其特徵在於，包括以下步驟：(a)將IC管芯貼裝到襯底上，所述IC管芯表面的熱點處設置有接觸焊盤，在管芯工作期間所述熱點處的輻射熱量高於管芯表面其他部位的輻射熱量；(b)在管芯和襯底之間連接至少一條焊線；(c)將熱互連構件與所述接觸焊盤相連；(d)將管芯、至少一條焊線和至少一部分熱互連構件密封在密封材料中；(e)所述塑封材料至少裸露出一個熱互連構件。
  5. 一種IC封裝體，其特徵在於，包括具有相對的第一和第二表面的襯底；安裝在所述襯底第一表面的管芯；散熱器；及連接所述管芯與所述散熱器表面的至少一個 裸露於塑封材料的熱互連構件。
  6. 如申請專利範圍第5項所述IC封裝體，其中，所述熱互連構件為焊球。
  7. 一種製造IC封裝體的方法，其特徵在於，包括以下步驟：(a)將管芯貼裝到襯底上；(b)將熱互連構件與所述管芯相連；(c)將管芯和至少一部分熱互連構件密封在密封材料中；(d)將塑封材料至少裸露出一個熱互連構件與散熱器相連。
  8. 如申請專利範圍第7項所述的方法，其中，先執行步驟(b)後執行步驟(d)。
TW096122029A 2006-06-20 2007-06-20 積體電路封裝體及其製造方法 TWI423404B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81487606P 2006-06-20 2006-06-20
US11/514,916 US9013035B2 (en) 2006-06-20 2006-09-05 Thermal improvement for hotspots on dies in integrated circuit packages

Publications (2)

Publication Number Publication Date
TW200818427A TW200818427A (en) 2008-04-16
TWI423404B true TWI423404B (zh) 2014-01-11

Family

ID=38564413

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096122029A TWI423404B (zh) 2006-06-20 2007-06-20 積體電路封裝體及其製造方法

Country Status (6)

Country Link
US (2) US9013035B2 (zh)
EP (1) EP1870933A2 (zh)
KR (1) KR100963207B1 (zh)
CN (1) CN101127334B (zh)
HK (1) HK1119482A1 (zh)
TW (1) TWI423404B (zh)

Families Citing this family (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI374525B (en) * 2004-05-11 2012-10-11 Taiwan Semiconductor Mfg Cut-out heat slug for integrated circuit device packaging
US7271479B2 (en) * 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
US8359739B2 (en) * 2007-06-27 2013-01-29 Rf Micro Devices, Inc. Process for manufacturing a module
US8053872B1 (en) 2007-06-25 2011-11-08 Rf Micro Devices, Inc. Integrated shield for a no-lead semiconductor device package
US8062930B1 (en) 2005-08-08 2011-11-22 Rf Micro Devices, Inc. Sub-module conformal electromagnetic interference shield
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US9299634B2 (en) * 2006-05-16 2016-03-29 Broadcom Corporation Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages
US20070273023A1 (en) * 2006-05-26 2007-11-29 Broadcom Corporation Integrated circuit package having exposed thermally conducting body
US7808087B2 (en) 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US8169067B2 (en) * 2006-10-20 2012-05-01 Broadcom Corporation Low profile ball grid array (BGA) package with exposed die and method of making same
US8183687B2 (en) 2007-02-16 2012-05-22 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
US8138024B2 (en) * 2008-02-26 2012-03-20 Stats Chippac Ltd. Package system for shielding semiconductor dies from electromagnetic interference
US8212279B2 (en) * 2008-03-25 2012-07-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader, signal post and cavity
US8148747B2 (en) * 2008-03-25 2012-04-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/cap heat spreader
US20100052005A1 (en) * 2008-03-25 2010-03-04 Lin Charles W C Semiconductor chip assembly with post/base heat spreader and conductive trace
US8232576B1 (en) 2008-03-25 2012-07-31 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and ceramic block in post
US8531024B2 (en) * 2008-03-25 2013-09-10 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and multilevel conductive trace
US7948076B2 (en) * 2008-03-25 2011-05-24 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and vertical signal routing
US8067784B2 (en) * 2008-03-25 2011-11-29 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and substrate
US20090284932A1 (en) * 2008-03-25 2009-11-19 Bridge Semiconductor Corporation Thermally Enhanced Package with Embedded Metal Slug and Patterned Circuitry
US8129742B2 (en) * 2008-03-25 2012-03-06 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and plated through-hole
US8310043B2 (en) * 2008-03-25 2012-11-13 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with ESD protection layer
US8324723B2 (en) * 2008-03-25 2012-12-04 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and dual-angle cavity in bump
US8288792B2 (en) * 2008-03-25 2012-10-16 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/post heat spreader
US8354688B2 (en) 2008-03-25 2013-01-15 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump
US8329510B2 (en) * 2008-03-25 2012-12-11 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a post/base heat spreader with an ESD protection layer
US8203167B2 (en) * 2008-03-25 2012-06-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and adhesive between base and terminal
US20110278638A1 (en) 2008-03-25 2011-11-17 Lin Charles W C Semiconductor chip assembly with post/dielectric/post heat spreader
US20100072511A1 (en) * 2008-03-25 2010-03-25 Lin Charles W C Semiconductor chip assembly with copper/aluminum post/base heat spreader
US8525214B2 (en) 2008-03-25 2013-09-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with thermal via
US8269336B2 (en) * 2008-03-25 2012-09-18 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and signal post
US8314438B2 (en) * 2008-03-25 2012-11-20 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and cavity in bump
US8415703B2 (en) * 2008-03-25 2013-04-09 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/flange heat spreader and cavity in flange
US8207553B2 (en) * 2008-03-25 2012-06-26 Bridge Semiconductor Corporation Semiconductor chip assembly with base heat spreader and cavity in base
US9018667B2 (en) * 2008-03-25 2015-04-28 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and dual adhesives
US20100181594A1 (en) * 2008-03-25 2010-07-22 Lin Charles W C Semiconductor chip assembly with post/base heat spreader and cavity over post
US8378372B2 (en) * 2008-03-25 2013-02-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and horizontal signal routing
US20110163348A1 (en) * 2008-03-25 2011-07-07 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and inverted cavity in bump
US8193556B2 (en) * 2008-03-25 2012-06-05 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and cavity in post
US20110156090A1 (en) 2008-03-25 2011-06-30 Lin Charles W C Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts
US8471376B1 (en) 2009-05-06 2013-06-25 Marvell International Ltd. Integrated circuit packaging configurations
US9355962B2 (en) * 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
US8324653B1 (en) 2009-08-06 2012-12-04 Bridge Semiconductor Corporation Semiconductor chip assembly with ceramic/metal substrate
US8633597B2 (en) * 2010-03-01 2014-01-21 Qualcomm Incorporated Thermal vias in an integrated circuit package with an embedded die
US9137934B2 (en) 2010-08-18 2015-09-15 Rf Micro Devices, Inc. Compartmentalized shielding of selected components
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
FR2977975A1 (fr) * 2011-07-13 2013-01-18 St Microelectronics Grenoble 2 Boitier electronique a via thermique et procede de fabrication
US20130082365A1 (en) 2011-10-03 2013-04-04 International Business Machines Corporation Interposer for ESD, EMI, and EMC
AU2013212087A1 (en) 2012-01-25 2014-08-07 Alphabet Energy, Inc. Modular thermoelectric units for heat recovery systems and methods thereof
JP2013243263A (ja) 2012-05-21 2013-12-05 Internatl Business Mach Corp <Ibm> ３次元積層パッケージにおける電力供給と放熱（冷却）との両立
US9257627B2 (en) 2012-07-23 2016-02-09 Alphabet Energy, Inc. Method and structure for thermoelectric unicouple assembly
US8796829B2 (en) 2012-09-21 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation through seal rings in 3DIC structure
US9490190B2 (en) 2012-09-21 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation through seal rings in 3DIC structure
US8963317B2 (en) * 2012-09-21 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation through seal rings in 3DIC structure
WO2014062559A2 (en) * 2012-10-15 2014-04-24 Alphabet Energy, Inc. Structures and methods for multi-leg package thermoelectric devices
US9807890B2 (en) * 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
CN103441108A (zh) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 一种芯片正装bga封装结构
CN103441106A (zh) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 一种芯片倒装bga封装结构
CN103441080A (zh) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 一种芯片正装bga封装方法
US9065017B2 (en) 2013-09-01 2015-06-23 Alphabet Energy, Inc. Thermoelectric devices having reduced thermal stress and contact resistance, and methods of forming and using the same
US9349709B2 (en) * 2013-12-04 2016-05-24 Infineon Technologies Ag Electronic component with sheet-like redistribution structure
US9368425B2 (en) * 2013-12-20 2016-06-14 Globalfoundries Inc. Embedded heat spreader with electrical properties
DE102014211524B4 (de) * 2014-06-17 2022-10-20 Robert Bosch Gmbh Elektronikmodul mit einer Vorrichtung zur Wärmeabführung von durch eine in einem Kunststoffgehäuse angeordnete Halbleitereinrichtung erzeugter Wärme und Verfahren zur Herstellung eines Elektronikmoduls
US9735084B2 (en) * 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9859200B2 (en) * 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
CN106416447A (zh) * 2015-01-22 2017-02-15 华为技术有限公司 一种小尺寸器件的散热装置和电路板散热系统
US9401315B1 (en) 2015-03-26 2016-07-26 Globalfoundries Inc. Thermal hot spot cooling for semiconductor devices
CN104851860B (zh) * 2015-04-30 2018-03-13 华为技术有限公司 一种集成电路管芯及制造方法
US9582621B2 (en) * 2015-06-24 2017-02-28 Globalfoundries Inc. Modeling localized temperature changes on an integrated circuit chip using thermal potential theory
JP2017112241A (ja) * 2015-12-17 2017-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US10083894B2 (en) 2015-12-17 2018-09-25 International Business Machines Corporation Integrated die paddle structures for bottom terminated components
US10199364B2 (en) 2016-05-19 2019-02-05 Sanmina Corporation Non-volatile dual in-line memory module (NVDIMM) multichip package
US20180090467A1 (en) * 2016-09-27 2018-03-29 Intel Corporation Package with thermal coupling
US10811334B2 (en) 2016-11-26 2020-10-20 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure in interconnect region
US10529641B2 (en) 2016-11-26 2020-01-07 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure over interconnect region
US11004680B2 (en) 2016-11-26 2021-05-11 Texas Instruments Incorporated Semiconductor device package thermal conduit
US10256188B2 (en) 2016-11-26 2019-04-09 Texas Instruments Incorporated Interconnect via with grown graphitic material
US10861763B2 (en) 2016-11-26 2020-12-08 Texas Instruments Incorporated Thermal routing trench by additive processing
US11676880B2 (en) 2016-11-26 2023-06-13 Texas Instruments Incorporated High thermal conductivity vias by additive processing
KR20180069636A (ko) 2016-12-15 2018-06-25 삼성전자주식회사 반도체 메모리 소자 및 이를 구비하는 칩 적층 패키지
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
CN107369662B (zh) * 2017-06-19 2020-11-24 北京嘉楠捷思信息技术有限公司 一种散热装置
US11011502B2 (en) * 2018-01-19 2021-05-18 Nepes Co., Ltd. Semiconductor package
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US10629512B2 (en) 2018-06-29 2020-04-21 Xilinx, Inc. Integrated circuit die with in-chip heat sink
US10622292B2 (en) * 2018-07-06 2020-04-14 Qualcomm Incorporated High density interconnects in an embedded trace substrate (ETS) comprising a core layer
US11398414B2 (en) * 2018-09-26 2022-07-26 Intel Corporation Sloped metal features for cooling hotspots in stacked-die packages
US10510713B1 (en) * 2018-10-28 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and method of manufacturing the same
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
US11423577B2 (en) 2020-07-08 2022-08-23 International Business Machines Corporation Printed circuit board assembly defect detection
US11515239B2 (en) * 2020-07-14 2022-11-29 Novatek Microelectronics Corp. Quad flat no-lead package structure
CN112151469A (zh) * 2020-09-21 2020-12-29 青岛歌尔微电子研究院有限公司 一种散热封装结构及其制备方法、以及电子器件
CN115708420A (zh) * 2021-06-18 2023-02-21 华为技术有限公司 芯片封装结构及其制备方法、封装系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030146520A1 (en) * 2002-01-07 2003-08-07 Jen-Kuang Fang Flip-chip package with a heat spreader
US20060091509A1 (en) * 2004-11-03 2006-05-04 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same

Family Cites Families (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247426A (en) * 1992-06-12 1993-09-21 Digital Equipment Corporation Semiconductor heat removal apparatus with non-uniform conductance
JPH07288298A (ja) * 1994-04-19 1995-10-31 Dainippon Printing Co Ltd 半導体チップ及びそれを用いた半導体パッケージ
KR100230189B1 (ko) * 1996-10-04 1999-11-15 마이클 디. 오브라이언 볼 그리드 어레이 반도체 패키지
US5856911A (en) * 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
US5786635A (en) * 1996-12-16 1998-07-28 International Business Machines Corporation Electronic package with compressible heatsink structure
US6395582B1 (en) * 1997-07-14 2002-05-28 Signetics Methods for forming ground vias in semiconductor packages
JPH11204679A (ja) * 1998-01-08 1999-07-30 Mitsubishi Electric Corp 半導体装置
US6337445B1 (en) * 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
TW418511B (en) * 1998-10-12 2001-01-11 Siliconware Precision Industries Co Ltd Packaged device of exposed heat sink
JP2000138262A (ja) * 1998-10-31 2000-05-16 Anam Semiconductor Inc チップスケ―ル半導体パッケ―ジ及びその製造方法
US6313521B1 (en) * 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
US6218730B1 (en) * 1999-01-06 2001-04-17 International Business Machines Corporation Apparatus for controlling thermal interface gap distance
US6265771B1 (en) * 1999-01-27 2001-07-24 International Business Machines Corporation Dual chip with heat sink
US6180426B1 (en) * 1999-03-01 2001-01-30 Mou-Shiung Lin High performance sub-system design and assembly
TW579555B (en) * 2000-03-13 2004-03-11 Ibm Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus
TW456013B (en) * 2000-07-04 2001-09-21 Advanced Semiconductor Eng Heat spreader substrate structure and the process thereof
US6525413B1 (en) * 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6523608B1 (en) * 2000-07-31 2003-02-25 Intel Corporation Thermal interface material on a mesh carrier
JP4529262B2 (ja) * 2000-09-14 2010-08-25 ソニー株式会社 高周波モジュール装置及びその製造方法
AU2002217987A1 (en) * 2000-12-01 2002-06-11 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US7161239B2 (en) * 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US20020079572A1 (en) * 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US6906414B2 (en) * 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
US7132744B2 (en) * 2000-12-22 2006-11-07 Broadcom Corporation Enhanced die-up ball grid array packages and method for making the same
US6853070B2 (en) * 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
US7259448B2 (en) * 2001-05-07 2007-08-21 Broadcom Corporation Die-up ball grid array package with a heat spreader and method for making the same
US6528892B2 (en) * 2001-06-05 2003-03-04 International Business Machines Corporation Land grid array stiffener use with flexible chip carriers
US6573592B2 (en) * 2001-08-21 2003-06-03 Micron Technology, Inc. Semiconductor die packages with standard ball grid array footprint and method for assembling the same
TW523887B (en) * 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
US6879039B2 (en) * 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US6712621B2 (en) * 2002-01-23 2004-03-30 High Connection Density, Inc. Thermally enhanced interposer and method
JP3908157B2 (ja) * 2002-01-24 2007-04-25 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
WO2003065451A1 (en) * 2002-01-31 2003-08-07 Thomson Licensing S.A. Flip chip die bond pads, die bond pad placement and routing optimization
US7245500B2 (en) * 2002-02-01 2007-07-17 Broadcom Corporation Ball grid array package with stepped stiffener layer
US6861750B2 (en) * 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
US7550845B2 (en) * 2002-02-01 2009-06-23 Broadcom Corporation Ball grid array package with separated stiffener layer
US6825108B2 (en) * 2002-02-01 2004-11-30 Broadcom Corporation Ball grid array package fabrication with IC die support structures
US6876553B2 (en) * 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
FR2837982B1 (fr) 2002-03-26 2005-02-18 Thales Sa Module de circuits integres et procede de fabrication correspondant
US20030202332A1 (en) * 2002-04-29 2003-10-30 Tommi Reinikainen Second level packaging interconnection method with improved thermal and reliability performance
TW582100B (en) * 2002-05-30 2004-04-01 Fujitsu Ltd Semiconductor device having a heat spreader exposed from a seal resin
US6848912B2 (en) * 2002-12-12 2005-02-01 Broadcom Corporation Via providing multiple electrically conductive paths through a circuit board
DE10260185B4 (de) * 2002-12-20 2007-04-12 Infineon Technologies Ag Halbleiterspeicher mit vertikalen Charge-trapping-Speicherzellen und Verfahren zu seiner Herstellung
US7245022B2 (en) * 2003-11-25 2007-07-17 International Business Machines Corporation Semiconductor module with improved interposer structure and method for forming the same
US20050127500A1 (en) 2003-12-10 2005-06-16 International Business Machines Corporation Local reduction of compliant thermally conductive material layer thickness on chips
KR100632459B1 (ko) 2004-01-28 2006-10-09 삼성전자주식회사 열방출형 반도체 패키지 및 그 제조방법
US7119432B2 (en) * 2004-04-07 2006-10-10 Lsi Logic Corporation Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
EP1741136A2 (fr) 2004-04-13 2007-01-10 SA Intexys Procede de fabrication de circuits electroniques et optoelectroniques
KR100604848B1 (ko) * 2004-04-30 2006-07-31 삼성전자주식회사 솔더 범프와 골드 범프의 접합을 갖는 시스템 인 패키지및 그 제조방법
US7482686B2 (en) * 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US7411281B2 (en) * 2004-06-21 2008-08-12 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US7432586B2 (en) * 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US7786591B2 (en) * 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US20060091542A1 (en) * 2004-11-03 2006-05-04 Broadcom Corporation Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same
KR100618881B1 (ko) 2005-01-05 2006-09-01 삼성전자주식회사 열방출 효율을 증대시킨 반도체 패키지 및 그 제조방법
US7355289B2 (en) * 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
US7566591B2 (en) * 2005-08-22 2009-07-28 Broadcom Corporation Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
US7582951B2 (en) * 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US20070200210A1 (en) * 2006-02-28 2007-08-30 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) * 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US9299634B2 (en) * 2006-05-16 2016-03-29 Broadcom Corporation Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages
US20070273023A1 (en) * 2006-05-26 2007-11-29 Broadcom Corporation Integrated circuit package having exposed thermally conducting body
US7808087B2 (en) * 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US8581381B2 (en) * 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030146520A1 (en) * 2002-01-07 2003-08-07 Jen-Kuang Fang Flip-chip package with a heat spreader
US20060091509A1 (en) * 2004-11-03 2006-05-04 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same

Also Published As

Publication number Publication date
US20150200149A1 (en) 2015-07-16
HK1119482A1 (en) 2009-03-06
US20070290322A1 (en) 2007-12-20
CN101127334B (zh) 2013-09-04
US9013035B2 (en) 2015-04-21
KR20070120917A (ko) 2007-12-26
EP1870933A2 (en) 2007-12-26
TW200818427A (en) 2008-04-16
KR100963207B1 (ko) 2010-06-16
CN101127334A (zh) 2008-02-20

Similar Documents

Publication Publication Date Title
TWI423404B (zh) 積體電路封裝體及其製造方法
EP1858076B1 (en) Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (ic) using integrated interposer for ic packages
US6404049B1 (en) Semiconductor device, manufacturing method thereof and mounting board
US7208819B2 (en) Power module package having improved heat dissipating capability
US5552635A (en) High thermal emissive semiconductor device package
US7772692B2 (en) Semiconductor device with cooling member
JPH0955455A (ja) 樹脂封止型半導体装置、リードフレーム及び樹脂封止型半導体装置の製造方法
US20060226521A1 (en) Semiconductor Package Having Integrated Metal Parts for Thermal Enhancement
US6700783B1 (en) Three-dimensional stacked heat spreader assembly for electronic package and method for assembling
TW201916279A (zh) 晶片封裝
JPH06232294A (ja) 半導体集積回路装置
JP2003258165A (ja) 半導体装置
TWI553799B (zh) 半導體封裝結構
JPH06125024A (ja) 半導体装置及びその冷却方法
TWI746391B (zh) 積體電路封裝系統
JP3058142B2 (ja) 半導体装置とその製造方法
JPH11163229A (ja) 半導体装置およびその製造方法
TWM348332U (en) Chip package structure
JPH04259245A (ja) 半導体集積回路装置
JPH07307421A (ja) Ｌｓｉチップ及びそのパッケージング構造

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees