TWM348332U - Chip package structure - Google Patents

Chip package structure Download PDF

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Publication number
TWM348332U
TWM348332U TW097211607U TW97211607U TWM348332U TW M348332 U TWM348332 U TW M348332U TW 097211607 U TW097211607 U TW 097211607U TW 97211607 U TW97211607 U TW 97211607U TW M348332 U TWM348332 U TW M348332U
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TW
Taiwan
Prior art keywords
wafer
package structure
substrate
heat dissipation
cap
Prior art date
Application number
TW097211607U
Other languages
Chinese (zh)
Inventor
Tsrong-Yi Wen
Original Assignee
Via Tech Inc
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Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW097211607U priority Critical patent/TWM348332U/en
Publication of TWM348332U publication Critical patent/TWM348332U/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A chip package structure including a substrate, a radiation cap, at least one chip and a molding compound is provided. The substrate having an upper surface and at least one outer-side wall includes a plurality of pads disposed on the upper surface. The radiation cap covering the upper surface and the outer-side wall of the substrate has a plurality of openings exposing the pads. The chip is disposed on the radiation cap and connects with the pads through a plurality of wires connecting the chip and the pads. The molding compound wraps the chip, the wires and the radiation cap.

Description

酼者科技的進步’晶# 110的運算速度大幅增加，而 曰j 110於運作中所產生的熱能亦隨之增加。然*，習知 板120與封裝膠體14〇的散熱能力並未隨之提升， 吏得封裝技術有了改良的空間。 M348332 八、新型說明： 【新型所屬之技術領域】 本創作是有關於一種晶片封裴結構，且特別是有關於 一種具有良好散熱效果的晶片封襄結構。 【先前技術】 在半導體產業中，積體電路（integratedCircuits，IC) 的生產，主要分為二個阳段.晶圓（Wafer)的製造、積體 電路（ic)的製作以及積體電路的封裝（Package)等。裸 晶片是經由晶圓製作、電路設計、光罩製作以及切割晶圓 等步驟而完成。 每—顆由晶圓切割所形成的裸晶片，在經由裸晶片上 之接點與外部訊號電性連接後，可再以封膠材料將裸晶片 ，覆。，其封裝之目的在於防止裸晶片受到濕氣、熱量、雜 =的衫響，並提供裸晶片與外部電路之間電性連接的媒 介，如此即完成積體電路的封裝步驟。 、 圖1繪示習知的晶片封裝結構的剖面示意圖。請參照 圖^，晶片封裝結構100的晶片110配置於基板12〇上’ 並藉由多條導線13G與基板12G連接。封裝膠體140配置 於基板120上並包覆晶片110與導線13〇。 【新型内容】 5 M348332 本創作的目的就是在提供一種具有良好散熱效果的晶 片封裝結構。 本創作提出一種晶片封裝結構包括一基板、一散熱 中目、至少一晶片與一封裝膠體。基板具有一頂面、至少一 外側面及多個配置於頂面上的接墊，而散熱帽覆蓋基板的 頂面與外侧面，並具有多個開口，其暴露出接墊。晶片配 置於散熱帽上，並經由多條導線與接墊電性連接，且封裝 膠體包覆晶片、導線與散熱帽。 基於上述，本創作可藉由散熱帽來增加晶片封裝吉構 的散熱路徑，進而提升“封裝結構的散熱效構 本創作更可藉由散熱帽來提南晶片封裝結構的結構強度。 ^為讓本創作之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 立圖2A繪示本創作一實施例之晶片封裝結構的剖面示 意圖，而圖2B繪示圖2A之散熱帽與基板的上視圖。圖3 繪示本創作另一實施例之晶片封裝結構的散熱帽與基板的 上視圖。圖4繪示圖2A之晶片封裝結構的其中一種變化 的剖面示意圖。 請參照圖2A’本創作的晶片封裝結構2〇〇包括一基板 21〇、一散熱帽220、一晶片230與一封襞膠體24〇。值得 注意的是，圖2A僅繪示一晶片230做為代表，但並非用 以限定本創作之晶片23〇的數量。舉例來說，本創作的晶 6 M348332 片封裝結構也可以具有-個以上的^，換言之，本創作 的晶片封裝結構也可以是多晶片封裝結構。 於本實施例巾，散熱帽22〇覆蓋部分基板21〇，而晶 片230配置於散熱帽220上，且封裂膠體24〇包覆晶片23〇 與散熱帽220。 基板210具有-頂面212、多個外側面214、一底面 216與多個配置頂面212上的接塾218，其中底面216相對The advancement of the technology of the latter, the operation speed of the crystal #110, has increased significantly, and the heat generated by the operation of the 曰j 110 has also increased. However, the heat dissipation capability of the conventional board 120 and the package colloid 14〇 has not been improved, and the packaging technology has improved space. M348332 VIII. New description: [New technical field] This creation is related to a wafer sealing structure, and in particular to a wafer sealing structure with good heat dissipation effect. [Prior Art] In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into two segments: the fabrication of wafers, the fabrication of integrated circuits (ic), and the packaging of integrated circuits. (Package) and so on. Bare wafers are completed through steps such as wafer fabrication, circuit design, mask fabrication, and wafer dicing. Each bare wafer formed by wafer dicing is electrically connected to an external signal via a contact on the bare wafer, and the bare wafer can be overcoated with a sealing material. The purpose of the package is to prevent the bare wafer from being exposed to moisture, heat, and the like, and to provide a medium for electrical connection between the bare chip and the external circuit, thus completing the packaging step of the integrated circuit. FIG. 1 is a cross-sectional view showing a conventional chip package structure. Referring to FIG. 2, the wafer 110 of the chip package structure 100 is disposed on the substrate 12' and connected to the substrate 12G by a plurality of wires 13G. The encapsulant 140 is disposed on the substrate 120 and covers the wafer 110 and the wires 13A. [New Content] 5 M348332 The purpose of this creation is to provide a wafer package structure with good heat dissipation. The present invention proposes a chip package structure comprising a substrate, a heat sink, at least one wafer and an encapsulant. The substrate has a top surface, at least one outer side surface and a plurality of pads disposed on the top surface, and the heat dissipation cap covers the top surface and the outer side surface of the substrate, and has a plurality of openings that expose the pads. The wafer is placed on the heat dissipating cap and electrically connected to the pads via a plurality of wires, and the encapsulant covers the wafer, the wires and the heat dissipating cap. Based on the above, the creation of the heat dissipation path of the chip package can be increased by the heat dissipation cap, thereby improving the heat dissipation effect of the package structure, and the heat dissipation cap can be used to increase the structural strength of the chip package structure. The above and other objects, features, and advantages of the present invention will become more apparent and understood. FIG. 2B is a top view of the heat dissipating cap and the substrate of FIG. 2A. FIG. 3 is a top view of the heat dissipating cap and the substrate of the chip package structure of another embodiment of the present invention. 2A' is a cross-sectional view showing a variation of the chip package structure of FIG. 2A. Referring to FIG. 2A', the chip package structure 2 of the present invention includes a substrate 21, a heat dissipation cap 220, a wafer 230, and a silicone body 24. It should be noted that FIG. 2A only shows a wafer 230 as a representative, but is not intended to limit the number of wafers 23 of the present invention. For example, the crystal 6 M348332 chip package of the present invention. The chip package structure of the present invention may also be a multi-chip package structure. In the embodiment, the heat dissipation cap 22 covers a portion of the substrate 21 , and the wafer 230 is disposed on the heat dissipation cap 220 . The sealing gel 24 covers the wafer 23 and the heat dissipation cap 220. The substrate 210 has a top surface 212, a plurality of outer side surfaces 214, a bottom surface 216 and a plurality of interfaces 218 on the top surface 212, wherein the bottom surface 216 relatively

於頂面212，且這些外側面214皆與頂面212及底面216 相連。 晶片封裝結構200可配置於—線路板3〇〇上，並與線 路板300連接。具體而言，晶片封裝結構2〇〇可具有多個 配置於基板210的底面216與線路板300之間的導電體 c，並可藉由這些導電體c與線路板3〇〇連接。導電體€ 例如是導電凸塊，而導電凸塊例如為錫球或是其他適合的 導電凸塊。於其他實施例中’導電體例如是針腳（pin)。 散熱帽220覆蓋基板210的頂面212與外侧面214， 以增加晶片封裝結樽2〇〇的散熱途徑，並可增加晶片封裝 結構200的結構強度。具體而言，散熱帽22〇可視情況所 需而覆蓋頂面212與一或多個外侧面214，且散熱帽220 例如是帽狀。散熱帽220的材質可為高導熱性的材料，例 如紹、銅及其合金、或是其他適合的金屬或合金。 此外，散熱帽220可具有一接近底面216的一端E， 且二導電體C可配置於端E與線路板300之間。而且，本 發明並不限定配置於端E與線路板300之間的導電體C的 7 M348332 數量，在其他實施例中，配置於端E與線路板300之間的 導電體C的數量可以是一個或是多個。導電體c例如是連 接散熱帽220與線路板300的接地墊（未繪示），以使散 熱帽220具有電磁屏蔽的功效。散熱帽220的材質例如是 導電材料。 此外，為便於配置在散熱帽220上的晶片230與接墊 218連接’散熱帽220可具有多個開口 OP1，且開口 〇P1 φ 暴露出接墊218。請同時參照圖2A與圖2B，在本實施例 中’接塾218可分為多個接墊組a，而每一接墊組A具有 至少二接墊218，且這些開口 ορι分別暴露出這些接墊組 A。此外’請參照圖3，在其他實施例中，多個開口 〇P2 可分別暴露出多個接墊218，也就是說，一個開口 〇P2僅 可暴露出一個接墊218。 另外，請參照圖4，於其他實施例中，散熱帽220可 區分為一頂部222、一側部224與一外緣部226。頂部222 覆盍頂面212，而侧部224連接頂部222並覆蓋外侧面 # 214。外緣部226與侧部224之接近底面216的端E相連， 且外緣部226朝向遠離基板21〇的方向延伸。外線部226 的一下表面22如實質上可與底面216齊平。此外，二導電 體c還可配置於外緣部226的下表面226a與線路板3〇〇 之間。而且，本發明並不限定配置於外緣部226的下表面 226a與線路板300之間的導電體c的數量，在其他實施例 中，配置於外緣部226的下表面226a與線路板300之間的 導電體C的數量可以是—個或是多個。 8 M348332 4再次參照圖2A，為使散熱帽22〇固定在基板21〇 上，可在政熱帽220與基板21〇之間配置一基板黏著層 250。於本實施例中’基板黏著層25〇可配置於散熱帽22〇 與基板210的頂面212之間，且基板黏著層25〇可呈有多 個與開口㈣連通關口 0 P 3以暴露出接墊2丨8。基板黏 著層250的材質包括樹脂、防焊材料或是其他適合的黏性 材料。 此外，為提升散熱帽22〇與基板21〇之間的導熱效 率，基板黏著層250的材質還可以是散熱膏、金屬或合金 等導熱性質較佳的材料。於本實施例中，當基板黏著層25〇 為金屬或合金（例如焊錫）時，基板黏著層25〇可配置於 散熱帽220之圍繞晶片230周邊的部分與基板21〇之間，' 以防止封裝膠體240溢流至散熱帽220之圍繞晶片23〇周 邊的部分與基板210之間。而且，由於基板黏著層25〇為 金屬或合金等導熱性良好的材質，因此，基板黏著層25〇 有利於散熱帽220與基板210之間的熱傳導。 晶片230配置於散熱帽220上。接墊218可配置於晶 片230周邊的基板21〇上，且晶片23〇可經由多條導線26〇 與接墊218電性連接，其中導線260連接晶片23〇與接墊 在本實施例中，為使晶片230固定在散熱帽22〇上， 還可在散熱帽220與晶片230之間配置一晶片黏著層 270且3曰片黏著層270的材質可為樹脂、散熱膏或其他具 有黏性與導熱性的材質。此外，封裝膠體24〇包覆晶片 M348332 230、導線260與散熱帽220’以保護晶片230與導線260。 圖5繪示本創作另一實施例之晶片封裝結構的剖面示 意圖。 請參照圖5 ’本實施例的晶片封裝結構3〇〇與前述實 施例的晶片封裝結構200 (請參照圖2A)相似，差異之處 僅在於晶片封裝結構300還包括一散熱蓋31〇。 月欠熱盖310配置於基板210的頂面212上並覆蓋晶片 230、導線260與封裝膠體240,以增加晶片封裝結構3〇〇 攀 的散熱途徑，並且可保護晶片230、導線260與封裝膠體 240。散熱蓋310的材質可為高導熱性的材料，例如鋁〔銅 及其合金、或是其他適合的金屬或合金。另外，在本實施 例中，散熱蓋310的材質也可為導電材料，如此一來，散 熱盖310還可具有電磁屏蔽的功效。 此外，散熱蓋310與散熱帽220導熱地連接，且本實 施例為使散熱蓋310固定在散熱帽22〇上，還可在散熱帽 2^0與散熱蓋310之間配置一散熱蓋黏著層32〇。散熱蓋黏 φ 者層的材質可為樹脂或是其他黏著性材料。此外，散 熱蓋黏著層320的材質還可以是金屬、合金或是其他導熱 性質良好的材質，以利於散熱帽220與散熱蓋310之間的 熱傳導。 • 另外，在本實施例中，封裝膠體240填充於散熱蓋31〇 與基板210所圍成的空間中。再者，於本實施例中，還可 在散熱蓋3H)與封裝膠體24〇之間配置一封裝膠體黏著層 330’以使散熱蓋310可固定在封裝膠體24〇上並與封裝膠 M348332 體240緊密接合。如此一來，散熱蓋31〇可快速地將晶片 230所產生的熱能由封裝膠體24〇傳遞至外界環境。 綜上所述，本創作可藉由散熱帽來增加晶片封裝結構 的散熱路徑，進而提升晶片封裝結構的散熱效率。^'夕°卜， 本創作更可藉由散熱帽來提高晶片封裝結構 同理，本創作還可藉由散熱蓋來更加提升晶片’圭= 散熱效率以及結構強度。另外，本創作之散熱帽與散熱蓋 還可具有電磁屏蔽的功效。 雖然本創作已以實施例揭露如上，然其並非用以限定 本創作，任何熟習此技藝者，在不脫離本創作之精神 圍内，當可作些許之更動與潤飾，因此本創作之保護範^ 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1 '纟會示習知的晶片封裝結構的剖面示意圖。 圖2A續'示本創作一貫施例之晶片封裝結構的剖面八 意圖。 α不 圖2Β繪示圖2Α之散熱帽與基板的上視圖。 圖3纷示本創作另一實施例之晶片封裝結構的散埶 與基板的上視圖。 '' 自 圖4繪示圖2Α之晶片封裝结構的其中一種變化的~ 面不意圖。 圖5繪示本創作另一實施例之晶片封装結構的剖 意圖。 τ 【主要元件符號說明】 11 M348332 100、200、300 :晶片封裝結構 110、230 :晶片 120、210 :基板 130、260 :導線 140、240 :封裝膠體 212 :頂面 214:外側面 216 :底面 218 :接墊 220 :散熱帽 222 :頂部 224 :側部 226 :外緣部 226a :下表面 250 :基板黏著層 270 :晶片黏著層 300 :線路板 310 :散熱蓋 320 :散熱蓋黏著層 330 :封裝膠體黏著層 A :接墊組 C :導電體 E :端 OP 卜 OP2、OP3 :開口 12The top surface 212 and the outer side surfaces 214 are connected to the top surface 212 and the bottom surface 216. The chip package structure 200 can be disposed on the circuit board 3A and connected to the circuit board 300. Specifically, the chip package structure 2 can have a plurality of conductors c disposed between the bottom surface 216 of the substrate 210 and the circuit board 300, and can be connected to the circuit board 3 by these conductors c. The electrical conductors are, for example, conductive bumps, and the conductive bumps are, for example, solder balls or other suitable conductive bumps. In other embodiments the conductor is, for example, a pin. The heat dissipation cap 220 covers the top surface 212 and the outer side surface 214 of the substrate 210 to increase the heat dissipation path of the chip package structure and increase the structural strength of the wafer package structure 200. In particular, the heat dissipating cap 22 covers the top surface 212 and one or more outer side surfaces 214 as desired, and the heat dissipating cap 220 is, for example, cap shaped. The heat sink cap 220 may be made of a material having high thermal conductivity, such as copper, copper and its alloys, or other suitable metals or alloys. In addition, the heat dissipation cap 220 may have an end E close to the bottom surface 216, and the two electrical conductors C may be disposed between the end E and the circuit board 300. Moreover, the present invention does not limit the number of 7 M 348 332 of the conductor C disposed between the terminal E and the circuit board 300. In other embodiments, the number of the conductors C disposed between the terminal E and the circuit board 300 may be One or more. The electric conductor c is, for example, a grounding pad (not shown) that connects the heat dissipating cap 220 and the circuit board 300, so that the heat dissipating cap 220 has electromagnetic shielding effect. The material of the heat dissipation cap 220 is, for example, a conductive material. In addition, in order to facilitate the connection of the wafer 230 disposed on the heat dissipation cap 220 to the pad 218, the heat dissipation cap 220 may have a plurality of openings OP1, and the opening 〇P1 φ exposes the pads 218. Referring to FIG. 2A and FIG. 2B simultaneously, in the embodiment, the interface 218 can be divided into a plurality of pad sets a, and each pad set A has at least two pads 218, and the openings ορι respectively expose these Pad set A. In addition, please refer to FIG. 3. In other embodiments, the plurality of openings 2P2 may respectively expose a plurality of pads 218, that is, one opening 2P2 may expose only one pad 218. In addition, referring to FIG. 4, in other embodiments, the heat dissipation cap 220 can be divided into a top portion 222, a side portion 224, and an outer edge portion 226. The top 222 covers the top surface 212 and the side portion 224 connects the top 222 and covers the outer side #214. The outer edge portion 226 is connected to the end E of the side portion 224 close to the bottom surface 216, and the outer edge portion 226 extends in a direction away from the substrate 21A. The lower surface 22 of the outer wire portion 226 can be substantially flush with the bottom surface 216 as such. Further, the two conductors c may be disposed between the lower surface 226a of the outer edge portion 226 and the wiring board 3''. Moreover, the present invention does not limit the number of the conductors c disposed between the lower surface 226a of the outer edge portion 226 and the circuit board 300. In other embodiments, the lower surface 226a of the outer edge portion 226 and the circuit board 300 are disposed. The number of conductors C between them may be one or more. 8 M348332 4 Referring again to FIG. 2A, in order to fix the heat dissipating cap 22 to the substrate 21A, a substrate adhesive layer 250 may be disposed between the thermal cap 220 and the substrate 21A. In the present embodiment, the substrate adhesion layer 25 〇 can be disposed between the heat dissipation cap 22 〇 and the top surface 212 of the substrate 210 , and the substrate adhesion layer 25 〇 can have a plurality of openings ( 4 ) communicating with the gate 0 P 3 to expose Pad 2丨8. The material of the substrate adhesive layer 250 includes a resin, a solder resist material or other suitable adhesive material. In addition, in order to improve the thermal conductivity between the heat dissipating cap 22 〇 and the substrate 21 ,, the material of the substrate adhesive layer 250 may be a material having better thermal conductivity such as a thermal grease, a metal or an alloy. In this embodiment, when the substrate adhesion layer 25 is made of a metal or an alloy (for example, solder), the substrate adhesion layer 25A can be disposed between the portion of the heat dissipation cap 220 surrounding the periphery of the wafer 230 and the substrate 21A, to prevent The encapsulant 240 overflows between the portion of the heat dissipation cap 220 surrounding the periphery of the wafer 23 and the substrate 210. Further, since the substrate adhesion layer 25 is made of a material having good thermal conductivity such as metal or alloy, the substrate adhesion layer 25 is advantageous for heat conduction between the heat dissipation cap 220 and the substrate 210. The wafer 230 is disposed on the heat dissipation cap 220. The pads 218 can be disposed on the substrate 21A around the wafer 230, and the wafers 23 can be electrically connected to the pads 218 via a plurality of wires 26, wherein the wires 260 are connected to the pads 23 and pads in the embodiment. In order to fix the wafer 230 on the heat dissipation cap 22, a die attach layer 270 may be disposed between the heat dissipation cap 220 and the wafer 230. The material of the adhesive layer 270 may be resin, thermal grease or other adhesive. Thermal conductivity material. In addition, the encapsulant 24 wraps the wafer M348332 230, the wires 260, and the heat sink cap 220' to protect the wafer 230 and the wires 260. FIG. 5 is a cross-sectional view showing a wafer package structure of another embodiment of the present invention. Referring to FIG. 5, the chip package structure 3 of the present embodiment is similar to the chip package structure 200 of the foregoing embodiment (please refer to FIG. 2A), except that the chip package structure 300 further includes a heat dissipation cover 31A. The aging heat cap 310 is disposed on the top surface 212 of the substrate 210 and covers the wafer 230, the wires 260 and the encapsulant 240 to increase the heat dissipation path of the chip package structure 3, and protect the wafer 230, the wires 260 and the encapsulant. 240. The material of the heat dissipation cover 310 may be a material having high thermal conductivity, such as aluminum [copper and its alloys, or other suitable metals or alloys. In addition, in the embodiment, the material of the heat dissipation cover 310 can also be a conductive material, so that the heat dissipation cover 310 can also have the function of electromagnetic shielding. In addition, the heat dissipating cover 310 is thermally connected to the heat dissipating cap 220 , and in this embodiment, the heat dissipating cover 310 is fixed on the heat dissipating cap 22 , and a heat dissipating cover adhesive layer may be disposed between the heat dissipating cap 2 0 0 and the heat dissipating cover 310 . 32〇. The heat sink cover is made of resin or other adhesive material. In addition, the heat-dissipating cover adhesive layer 320 may be made of metal, alloy or other material having good thermal conductivity to facilitate heat conduction between the heat-dissipating cap 220 and the heat-dissipating cover 310. In addition, in the present embodiment, the encapsulant 240 is filled in a space surrounded by the heat dissipation cover 31A and the substrate 210. Furthermore, in this embodiment, an encapsulation adhesive layer 330 ′ can be disposed between the heat dissipation cover 3H) and the encapsulant 24 以 to enable the heat dissipation cover 310 to be fixed on the encapsulant 24 并 and the M348332 body. 240 is tightly joined. In this way, the heat dissipating cover 31 can quickly transfer the heat generated by the wafer 230 from the encapsulant 24 to the external environment. In summary, the present invention can increase the heat dissipation path of the chip package structure by using a heat dissipation cap, thereby improving the heat dissipation efficiency of the chip package structure. ^ '夕°卜, this creation can also improve the chip package structure by using a heat-dissipating cap. This creation can also enhance the heat dissipation efficiency and structural strength of the wafer by the heat-dissipating cover. In addition, the heat sink and heat sink cover of this creation can also have electromagnetic shielding effect. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the creation of the present invention. Anyone skilled in the art can make some changes and refinements without departing from the spirit of the creation. ^ The person defined in the scope of the patent application is subject to change. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional wafer package structure. Figure 2A is a continuation of the cross-sectional view of the wafer package structure of the present invention. α 不 Figure 2Β is a top view of the heat sink cap and the substrate of Figure 2 . Figure 3 is a top plan view of the dilute and substrate of the wafer package structure of another embodiment of the present invention. '' From Fig. 4, one of the variations of the chip package structure of Fig. 2 is shown. Fig. 5 is a cross-sectional view showing a wafer package structure of another embodiment of the present invention. τ [Description of main component symbols] 11 M348332 100, 200, 300: chip package structure 110, 230: wafer 120, 210: substrate 130, 260: wires 140, 240: package colloid 212: top surface 214: outer side 216: bottom surface 218: pad 220: heat sink cap 222: top 224: side portion 226: outer edge portion 226a: lower surface 250: substrate adhesive layer 270: wafer adhesive layer 300: circuit board 310: heat dissipation cover 320: heat dissipation cover adhesive layer 330: Package adhesive layer A: pad set C: conductor E: end OP Bu OP2, OP3: opening 12

Claims (1)

M348332 九、申請專利範圍： h —種晶片封裝結構，包括： 基板’具有一頂面、至少一外側面及多個配置於該 頂面上的接整； —散熱帽’覆蓋該基板的該頂面與該外側面，並具有 多個開口’其暴露出該些接塾；M348332 IX. Patent application scope: h—a chip package structure, comprising: a substrate having a top surface, at least one outer side surface and a plurality of alignments disposed on the top surface; a heat dissipation cap covering the top of the substrate a face and the outer side, and having a plurality of openings 'which expose the joints; 至少一晶片，配置於該散熱帽上，並經由多條導線與 該些接墊電性連接；以及 一封裴膠體，包覆該晶片、該些導線與該散熱帽。 2·如申請專利範圍第1項所述之晶片封裴結構，更包 多個導電體 的底面上。 其分別配置於該基板的一相對 於該頂面 3. 如申請專利範圍第2項所述之晶片封裴紝 5亥散熱帽具有—接近該底面的一端，且至少— 其中 配置於該端上。 導電體At least one wafer is disposed on the heat dissipation cap and electrically connected to the pads via a plurality of wires; and a silicone body covering the wafer, the wires and the heat dissipation cap. 2. The wafer sealing structure according to item 1 of the patent application, further comprising a bottom surface of a plurality of electrical conductors. Each of the substrates is disposed on the substrate with respect to the top surface 3. The wafer package 5H heat-dissipating cap according to claim 2 has an end close to the bottom surface, and at least - configured on the end . Electrical conductor 4. 如申請專利範圍第2項所述之晶片封萝 該散熱帽包括： 又、、、0才冓’其中 一頂部’覆蓋該頂面； 一侧部，覆蓋該外側面，並連接該頂部；以 一外緣部，與該側部之接近該底面的一端及 外緣部朝向遠離該基板的方向延伸。 目連，且該 5. 如申請專利範圍第4項所述之晶片封 該外緣部的一下表面實質上與該底面齊平。、〜構’其中 13 M348332 6.如申請專利範圍第5項所述之晶片封裝結構，其中 至少一該些導電體配置於該外緣部的該下表面。 7·如申請專利範圍第1項所述之晶片封裝結構，更包 括： 一散熱蓋，配置於該基板的該頂面上，並覆蓋該晶 片、該些導線與該封裝膠體，其中該散熱蓋與該散熱帽導 _ 熱地連接。 - 8.如申請專利範圍第7項所述之晶片封裝結構，其中 該封裝膠體填充於該散熱蓋與該基板所圍成的空間中。 9. 如申凊專利範圍第7項所述之晶片封裝結構，更包 括： 一散熱蓋黏著層，配置於該散熱帽與該散熱蓋之間。 10. 如申請專利範圍第9項所述之晶片封裝結構，其 中該散熱蓋黏著層的材質包括樹脂、金屬或合金。 、 11. 如申請專利範圍第7項所述之晶片封裝結構，更 包括： φ 一封裝膠體黏著層，配置於該散熱蓋與該封裝膠體之 間。 12. 如申請專利範圍第7項所述之晶片封裝結構，其 中該散熱蓋的材質包括一導電材料。 • 13.如申請專利範圍第1項所述之晶片封裝結構，更 包括： 一基板黏著層’配置於該散熱帽與該基板之間。 14.如申凊專利範圍第ι3項所述之晶片封裝結構，其 14 M348332 中該基板黏著層的材質包括樹脂、散熱膏、金屬或合金。 15. 如申請專利範圍第14項所述之晶片封裝結構，其 中當該基板黏著層為金屬或合金時，該基板黏著層配置於 該散熱帽之圍繞該晶片周邊的部分與該基板之間。 16. 如申請專利範圍第1項所述之晶片封裝結構，更 包括： 一晶片黏著層，配置於該散熱帽與該晶片之間。 17. 如申請專利範圍第16項所述之晶片封裝結構，其 中該晶片黏著層的材質包括樹脂或散熱膏。 18. 如申請專利範圍第1項所述之晶片封裝結構，其 中該些開口分別暴露出該些接墊。 19. 如申請專利範圍第1項所述之晶片封裝結構，其 中該些接墊分為多個接墊組，且每一接墊組具有至少二接 墊，該些開口分別暴露出該些接墊組。 20. 如申請專利範圍第1項所述之晶片封裝結構，其 中該散熱帽的材質包括一導電材料。4. The wafer sealing device according to claim 2, wherein the heat dissipating cap comprises: a second, a top portion covering the top surface; a side portion covering the outer side surface and connecting the top portion And an outer edge portion, and one end and the outer edge portion of the side portion adjacent to the bottom surface extend in a direction away from the substrate. Mesh connection, and the lower surface of the outer edge portion of the wafer seal as described in claim 4 is substantially flush with the bottom surface. The chip package structure of claim 5, wherein at least one of the electrical conductors is disposed on the lower surface of the outer edge portion. The chip package structure of claim 1, further comprising: a heat dissipation cover disposed on the top surface of the substrate and covering the wafer, the wires and the encapsulant, wherein the heat dissipation cover It is thermally connected to the heat dissipation cap. 8. The wafer package structure of claim 7, wherein the encapsulant is filled in a space enclosed by the heat dissipation cover and the substrate. 9. The chip package structure of claim 7, further comprising: a heat dissipating cover adhesive layer disposed between the heat dissipating cap and the heat dissipating cover. 10. The wafer package structure of claim 9, wherein the heat dissipation cover adhesive layer comprises a resin, a metal or an alloy. 11. The chip package structure of claim 7, further comprising: φ a package adhesive layer disposed between the heat dissipation cover and the package body. 12. The chip package structure of claim 7, wherein the material of the heat dissipation cover comprises a conductive material. 13. The chip package structure of claim 1, further comprising: a substrate adhesive layer disposed between the heat dissipation cap and the substrate. 14. The wafer package structure of claim 1 , wherein the material of the substrate adhesion layer in 14 M348332 comprises a resin, a thermal grease, a metal or an alloy. 15. The wafer package structure of claim 14, wherein when the substrate adhesive layer is a metal or an alloy, the substrate adhesive layer is disposed between the portion of the heat dissipation cap surrounding the periphery of the wafer and the substrate. 16. The wafer package structure of claim 1, further comprising: a die attach layer disposed between the heat sink cap and the wafer. 17. The wafer package structure of claim 16, wherein the material of the die attach layer comprises a resin or a thermal grease. 18. The wafer package structure of claim 1, wherein the openings respectively expose the pads. 19. The chip package structure of claim 1, wherein the pads are divided into a plurality of pads, and each pad group has at least two pads, the openings respectively exposing the connections Mat set. 20. The chip package structure of claim 1, wherein the heat sink cap comprises a conductive material. 1515
TW097211607U 2008-06-30 2008-06-30 Chip package structure TWM348332U (en)

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