TWI404145B - 拉緊的絕緣層上覆矽層結構及其製備方法 - Google Patents

拉緊的絕緣層上覆矽層結構及其製備方法 Download PDF

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TWI404145B
TWI404145B TW094108847A TW94108847A TWI404145B TW I404145 B TWI404145 B TW I404145B TW 094108847 A TW094108847 A TW 094108847A TW 94108847 A TW94108847 A TW 94108847A TW I404145 B TWI404145 B TW I404145B
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Toshiharu Furukawa
Charles William Koburger Iii
James Albert Slinkman
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Description

拉緊的絕緣層上覆矽層結構及其製備方法
本發明係有關於一種半導體結構及元件和他們的製造方法，且更特定地係有關於特徵為具有較高載子移動性之絕緣層上覆矽層(silicon－on－insulators, SOI)結構、元件及積體電路，及其之製備方法。
絕緣層上覆矽層(silicon－on－insulators, SOI)結構係由一層覆蓋在二氧化矽絕緣層（亦即，埋設的氧化物(buried oxide)或簡稱「BOX」）上之薄的主動矽層所構成，該二氧化矽絕緣層又覆蓋在一支持性矽基材上。將SOI結構用於金氧半導體場效電晶體(MOSFET)技術及互補式金氧半導體(CMOS)積體電路的優點文獻中已多所記載。相較於習知大塊矽技術來說，該SOI結構的絕緣層使得場效電晶體(FET’s)可以較高速率運作且具有較佳的電子絕緣性及較低的電子損失率。其結果是可提高效能及降低耗電性。
在習知的MOSFET與CMOS技術中，形成在一SOI結構上的場效電晶體包括一形成在主動矽層中的通道。載子移動性是一項非常重要的參數，因其可直接影響該場效電晶體的輸出電流及切換效能(switching performance)。因此，提高效能的方式之一是藉由雙軸的或單軸的拉緊該主動矽層界已提高通道的遷移能力。可藉由引入壓縮的或拉伸的應力於該主動矽層來提供一淨應力。局部或整體式的拉緊該矽層平面上的晶格，會改變該矽層的電子帶結構。結果，可增加平面上的載子移動力10%至25%，因此可改善元件效能。
也可藉由引入一由晶格常數高於矽層之材料所製成的介層的方式，而在整個基材上的矽層中均勻的引入雙軸拉伸應力。舉例來說，可藉由在埋設的氧化物層與矽主動層之間，引入一薄層之分級矽鍺緩衝層及一放鬆的矽鍺層，而在一SOI結構上製造出一雙軸拉緊的主動矽層，該矽主動層係磊晶成長於該放鬆的矽鍺層上。該拉緊的應力會使基材平面上矽原子的距離增加，因而提高電子的遷移能力。可以一種層轉移方式來移除該矽鍺層。均勻的拉緊應力可提高n－通道型場效電晶體(NFET’s)的電子遷移能力，且p－通道型場效電晶體(PFET’s)的電洞遷移能力可藉由在與該PFET元件通道載子流動方向垂直的方向中引入一拉伸的應力而達成。
可藉由製程最佳化方式而於一矽層局部引入單軸壓縮應力。可藉由調控現存元件結構（例如帽蓋層、間隔物及淺溝渠隔離層）性質的方式來引入少量應力。可藉由只在PFET’s的源極與汲極區域沉積一分級的矽鍺層的方式來引入大量應力。局部引入矽鍺層具有可增加壓縮應力到該PFET通道的效應，因而可提高局部的電洞遷移力。
以矽鍺層來形成拉緊的矽層具有某些缺點。矽鍺層具有易使矽層出現缺陷的傾向，因而影響元件效能。在整體晶圓上沉積矽鍺層對單獨欲使NFET’s及PFET’s最佳化並不恰當。同時，矽鍺層的熱傳導性不佳，且某些摻雜物更易在整個矽鍺層上擴散，因而影響主動層中源極與汲極區域中摻雜物的擴散模式。另一項限制是使用矽鍺層會造成主動層整體厚度增加，而在目前元件設計上是希望將主動層厚度縮小的。
因此，需要一種可在一SOI結構的主動層中引入拉伸應力的方法，其係不需要使用一底下的、放鬆的矽鍺層；及具有由該方法製成之一拉緊的主動層的SOI結構、元件與積體電路。
依據本發明，藉由在該絕緣層上覆矽層基材的主動層上引入一拉伸應力而形成具有一拉緊的主動層之SO結構、元件及積體電路。該拉伸應力係在不引入一下層的矽鍺層的情況下來提供。為此，這類半導體結構大致包括一由半導體材料製成的主動層、一基材、及一介於該主動層與該基材之間的絕緣層。該絕緣層具有一較厚的區域以轉移拉伸的應力至該主動層，以有效地在覆蓋於該較厚區域之上的主動層之拉緊區域中誘發出拉緊應力。
依據本發明，局部提高埋設的氧化物層的厚度可局部地將拉伸的應力轉移至覆蓋於其上的主動層上。由一氧化物遮罩所界定出來的主動層的多個區域，可為該拉伸應力所拉緊。該拉緊的主動層的特徵在於具有較高的載子移動力，因而能改善形成於該拉緊的層中及其上之元件效能。該拉力可在不依賴複雜沉積技術下，隨著底下絕緣層被改變且不增加額外的層至該元件結構的情況下，被引入至該主動層中。特別是，在沒有矽鍺層蜘蛛多缺點的情況下拉緊該矽主動層。
首先參照第1圖，其顯示本發明一絕緣層上覆矽層(SOI)基板10。詳言之，該SOI基板10包括一矽（或其他適當半導體材料）主動層12，其係以一絕緣層16而與一處理晶圓14垂直分隔開來。該絕緣層16可電氣分隔該處理晶圓14與該主動層12。該SOI基材可以任何適當的技術製造，例如藉由晶圓接合或一氧離子佈植分離(seperation by implantation of oxygen, SIMOX)技術。在本發明所示實施例中，該由矽構成的主動層12一開始可摻雜一n－型摻雜物以使其成為n－型或摻雜一p－型摻雜物以使其成為p－型。該處理晶圓14可由任一適當的半導體材料形成，包括（但不限於）矽及多晶矽（聚矽）。該由介電材料構成的絕緣層16典型為二氧化矽，其厚度約在50奈米至約150奈米間，但並不限於此範圍。該主動層12可以薄至約10奈米或更薄，典型是在約20奈米至約150奈米的範圍內。第1圖中並未示出該處理晶圓14的厚度。
主動層12典型係覆以一由硬遮罩材料（例如一氮化物層）製成的帽蓋層22，以提供一可自我對準的上方氧化物阻障層及研磨終止層。為此，可於該主動層12之上覆以一同形的硬遮罩材料，其可以是10至150奈米的氮化矽(Si3 N4 )。一光敏性光阻層係覆蓋於該同形的硬遮罩層上，讓光購過一習知光罩來將其曝光，以於光阻上形成欲求島18的潛在圖樣，並將其顯影以將該潛在圖樣轉變成最終圖樣。可使用諸如非異向性蝕刻法(例如，反應性離子蝕刻)之類的蝕刻製程來移除最終圖樣中未被遮罩區域上的帽蓋層22。在完成該蝕刻製程後，即可將該光阻層向該SOI基材上剝除。
依據習知設計來選擇每一島18的線寬，在特定實施例中，該線寬為約15奈米至約125奈米間。在相鄰島18間的絕緣層16和溝渠20可提供橫向的絕緣。
在此，「垂直的」、「水平的」等名詞係舉例性質，用以作為一參考，並非用以限定於該特定方向。在此所謂「水平的」係定義成一與習知平面或SOI基材10表面平行的平面，無論其原來方向為何。「垂直的」一詞在此定義為垂直於上述界定之「水平的」方向之方向。諸如「在...之上或上方(on or above)」、「在...之下或下方(below or beneath or under)」「側(side)(如側壁)」、「較高(higher)」、「較低(lower)」等名詞均係相對於該水平的平面來界定。須知在不悖離本發明範疇下，可使用各種其他方式來建立參考方向。
參照第2及2A圖，其中相同元件符號係代表出現在第1圖及後續製程中相同的結構，由氧化遮罩材料建構成的條紋26係用以定義出可於其中發生氧化反應的視窗28。每一視窗28（在此示出一視窗28）可將相鄰的條紋26分隔開來。為製造出條紋26，在第1圖結構上沉積出一層氧化遮罩材料。條紋26覆蓋住該帽蓋層22上表面及連同該島18、在視窗28旁邊或側面之區域中的絕緣層16。方向性蝕刻製程可創造出視窗28並留下一由氧化遮罩材料構成的間隔物30覆蓋住該主動層12之每一垂直的側壁。由方向性蝕刻製程所創造出的視窗28也應停止在該氧化遮罩材料之下的薄蝕刻終止層上，使不致過度蝕刻該帽蓋層22。
參照第3圖，其中相同元件符號係代表出現在第2圖及後續製程中相同的結構，以適當製程將SOI基材10之水平平面中一區域以及主動層12局部區域32之下的區域變厚。絕緣層16中變厚的區域大致與主動層12區域垂直。絕緣層16變厚的步驟係由一可逐步消耗與該絕緣層16共同延伸之主動層12下方平面表面33和/或處理晶圓14一上方平面表面35的製程開始，以形成具有較高體積之新組成的材料，或藉由其他可擴展或增加絕緣層16之有效厚度的機制來進行。區域32大致來說是主動層12中的平面上區域，其係在SOI基材平面中與視窗28水平對齊。
絕緣層16厚度增加的程度可視所欲形成在主動層12中之半導體元件的欲求效能及任何擴產時之設計或實行上的困難度而定。在本發明特定實施例中，兩相鄰條紋26間的間距約為1微米。
在本發明一例示的實施例中，以一熱氧化製程來增加該SOI基材10中絕緣層16的局部厚度，在該SOI基材中一光罩24係由諸如氮化矽之類的不會氧化的材料製成，該光罩24係作為一種氧化遮罩。該氧化製程會將該SOI基板10暴露在一乾式或濕式之充滿氧氣且加熱的環境下，例如，一種氧化爐或快速熱退火製程室。選擇氧化條件以提供絕緣層16僅於主動層12下方區域32處出現專一性的膨脹，並避免整個SOI基板10上之絕緣層16均一地變厚。在一特定實施例中，在800℃至950℃下進行的濕式氧化係持續進行一段足以提高區域32下絕緣層厚度約1奈米至10奈米厚度的時間。在本發明其他實施例中，兩相鄰條紋26的間距約0.2微米，氧化物厚度可提高下層區域32約4.5奈米並賦予區域32約0.1%的拉力。絕緣層厚度16所增加的厚度多寡是由整個變厚區域中的最大厚度來決定，因區域32下的厚度變化並非整體均一性的提高，雖然本發明也不限於此範圍。
主動層12的氧化係藉由從該加熱環境中的氧化氣體源傳送氧化物種氣體穿過視窗28而產生，因可形成絕緣層16的材料會吸附該等氣體之故。覆蓋於島18上的帽蓋層22及光罩24之條紋26，與覆蓋在該島18之垂直側壁上的間隔物30可遮蔽主動層12使不會直接接觸到往內傳送流動的氧化物種氣體，典型是氧氣或水（其係來自富含氧氣的環境），使得主動層12的側壁與上表面幾乎不會受到氧化製程的影響。
再次參照第3圖及依據該例式的實施例，氧化物種氣體會從每一視窗28擴散穿過絕緣層16以與主動層12下方表面33的矽發生化學反應。潛在性的，如果構成處理晶圓14的材料很容易氧化的話，該擴散的物種可與處理晶圓14上方表面35的材料發生化學反應。相較於光罩24之條紋26下方區域32以外的部分，對主動層12區域32部分來說，其氧化物種擴散至主動層12下方表面33的路徑，比光罩24之條紋26下方區域32以外的部分其其氧化物種擴散至主動層12下方表面33的路徑來得短。此外，對處理晶圓14區域32部分來說，其氧化物種擴散至處理晶圓14上方表面35的路徑，比光罩24之條紋26下方及處理晶圓14區域32以外的部分其氧化物種擴散至處理晶圓14上方表面35的路徑來得短。因此，在區域32下方之絕緣層16有效厚度係潛在地較其他部分來得高，該絕緣層16可與主動層12的氧化部分具有相同組成，也與處理晶圓14具有相同組成。已知，所形成二氧化矽的厚度約等於所消耗掉矽層厚度的2.27倍。垂直對比於光罩24之條紋26所覆蓋之鄰近區域而言，局部擴展該絕緣層16會升高覆蓋在該絕緣層16較厚區域之主動層12之區域32的高度。
擴展絕緣層16會升高每一島18區域32中主動層12之材料的應力，其會在區域32中誘發出一淨量之拉緊力。此淨量之局部拉緊力，典型在每一百分比的十分之一至十分之二範圍內，可影響該主動層12拉緊區域32中載子的電性。如果該主動層12是矽，該拉緊應力會提高區域32中的載子移動力約百分之二十甚至更高。因此，後續在每一島18中所製造的元件之元件效能將會改善，如果該元件通道係位在該拉緊的區域32中。可調整氧化的重來影響引入至該拉緊區域32中的拉緊力程度。此外，視窗32的寬度也對該引入至拉緊區域32中的拉緊力程度有所影響。
參照第4圖，其中相同元件符號係代表出現在第3圖及後續製程中相同的結構，以對該主動層12及絕緣層16材料具專一性的蝕刻製程將光罩24（第3圖）從該SOI基材10上剝除下來。如果光罩24及帽蓋層22是由相同材料構成，帽蓋層22的厚度必須大於光罩24的厚度，使得兩條紋26間之帽蓋層22無法被完全剝除。之前位在光罩24下之島18的區域是藉由主動層12周圍區域連接固定至絕緣層16上，使得拉緊的區域32不會被放鬆或是其放鬆度將受到限制。結果，該拉緊的區域32將因區域32下適當位置處之絕緣層16厚度增加而處於永遠拉緊的狀況下。如果預期會出現某種程度的放鬆，可增加區域32一開始的拉力以補償該放鬆。
參照第5、6A及6B圖，其中相同元件符號係代表出現在第4圖及後續製程中相同的結構，於該拉緊的區域32中具有通道區域之島18之中或其上形成半導體元件，其可改善元件中載子的移動力使得元件表現出較高的效能。所示MOSFET元件並非用以限定本發明範疇，習知技藝人士應能了解其他類型的半導體元件（例如，記憶體胞、其他類型的電晶體等）也能由所述拉緊區域中受惠。
特別參照第5圖，一類型的半導體元件34a可以是金氧半導體場效電晶體(MOSFET’s)，每一者都具有源極/汲極區域36、38及位於一通道42上方之一靜電－耦合閘極電極40，該通道42係被定義在該主動層12中介於該源極/汲極區域36、38之間。一薄閘極介電層44可將閘極電極40與該通道42彼此電氣絕緣。用來形成該閘極電極40的材料可以是，例如，多晶矽、鎢或其他欲求的材料，且該源極/汲極區域36、38及其延伸可以適當摻雜物進行離子佈植。可在該閘極電極42的垂直側壁上加入一諸如氮化矽之類的材料製成的側壁間隔物37、39。該間隔物37、39與該閘極電極42一起作為一可自我對準的遮罩，用於該源極/汲極區域36、38之深摻雜部分的佈植。隔離區域43提供主動層12中相鄰島間的電氣隔離。該隔離區域43係以一適當的介電材料加以充填，例如以化學氣相沉積法同形沉積之二氧化矽層，其被以一化學機械研磨(CMP)法或任何適當的平坦化技術加以平坦化成一平面。帽蓋層22係作為該平坦化操作的一研磨終止層且可在平坦化操作之後加以移除。
在源極/汲極區域36、38間流動的載子以和通道42中的電阻變化成比例的方式穿過通道42，該電阻變化係與施加到閘極電極40上的電位成比例變化。元件34a係製作成可使每一通道42與一拉緊區域32彼此重疊。在本發明特定實施例中，元件34a是一種n－通道型場效電晶體(NFET’s)且任一積體電路中的p－通道型場效電晶體(PFET’s)係形成在缺乏該拉緊區域32的SOI基材10上。該場效電晶體係以習知技藝人士熟知的製程來製作。
參找第6A及6B圖，另一類型的半導體元件34b可以是可自我對準的雙閘極鰭式場效電晶體(finFET)，其每一者均具有一以薄的垂直層修飾之通道46及一閘極電極48其界定出包覆在該通道區域46兩側之兩個單獨的閘極部分48a、48b（第5C圖）。該閘極電極48係位於源極/汲極區域50、52之間且覆蓋住該通道46。閘極電極48係以一閘極介電層47與該閘極電極48彼此成電氣隔絕。提供間隔物54、56以將該閘極電極48夾在中間。元件34b係製作成可使每一通道46與一拉緊區域32彼此重疊，本發明也涵蓋帽蓋層22的全部或部份可留在完成的元件結構的主動層12中。該finFET係可以習知技藝人士熟知的製程來製作。
參照第7圖，其中相同元件符號係代表出現在第2圖及後續製程中相同的結構，在覆以光罩24並進行圖案化製程之前，先於帽蓋層22上覆以一墊層58。該墊層58在可蝕刻光罩24及去除光罩24的製程中係作為一種蝕刻終止層材料。該墊層58可有效的防止這些個別的蝕刻製程將兩相鄰條紋26間的帽蓋層22變薄。一種適合作為墊層58的材料是二氧化矽，如果該帽蓋層22是氮化矽，其厚度約為2奈米至10奈米。帽蓋層被過度削薄將降低其作為研磨終止層與氧化遮罩的功效。
本發明已藉由各種實施例相係揭示如上，所述實施例僅供闡述發明目的之用，非用以限制本發明範疇。
10‧‧‧SOI基材
12‧‧‧主動層
14‧‧‧處理晶圓
16‧‧‧絕緣層
18‧‧‧島
20‧‧‧溝渠
22‧‧‧帽蓋層
24‧‧‧光罩
26‧‧‧條紋
28‧‧‧視窗
32‧‧‧主動層12下方區域
33‧‧‧下方平面表面
34‧‧‧上方平面表面
34a、34b．．．半導體元件
36．．．源極
38．．．汲極
37、39．．．側壁間隔物
40、48．．．閘極電極
42、46．．．通道
43．．．隔離區域
44．．．閘極介電層
47．．．閘極介電層
48a、48b．．．閘極部分
58．．．墊層
第1圖為本發明一基材部分截面的示意圖。
第2圖為類似第1圖之基材在後續製程階段下的圖示。
第2A圖為沿著第2圖之線2A-2A所看到的截面示意圖。
第3圖為類似第2圖之基材在後續製程階段下的圖示。
第4圖為類似第3圖之基材在後續製程階段下的圖示。
第5圖為類似第4圖之基材經過一系列後續製程階段下的圖示。
第6A圖為依據本發明另一實施例，類似第5圖之基材經過一系列後續製程階段下的圖示。
第6B圖為類似第6A圖之基材的示意圖。
第7圖為依據本發明另一實施例，類似第2圖之基材的示意圖。
12‧‧‧主動層
14‧‧‧處理晶圓
16‧‧‧絕緣層
18‧‧‧島
32‧‧‧主動層下方區域
34a‧‧‧半導體元件
36‧‧‧源極
38‧‧‧汲極
37、39‧‧‧側壁間隔物
40‧‧‧閘極電極
42‧‧‧通道
43‧‧‧隔離區域
44‧‧‧閘極介電層

Claims (34)

  1. 一種半導體結構，其至少包含：一由半導體材料製成的島，該島包括複數個側壁與一拉緊的區域；一處理晶圓；以及一絕緣層，其係位於該島與該處理晶圓之間，該絕緣層含有一變厚的區域位在該拉緊的區域之下，該絕緣層將該半導體材料製成的該島與該處理晶圓電氣隔絕，且該變厚的區域可將拉伸應力轉移至該拉緊的區域。
  2. 如申請專利範圍第1項所述之半導體結構，其中該絕緣層是一埋設的氧化物層且該島是矽。
  3. 如申請專利範圍第1項所述之半導體結構，更包含：一源極，其係界定在該島中；一汲極，其係界定在該島中；及一通道，其係界定在介於該源極與該汲極間之該島的部分中，至少一部份該通道是位在該島之該拉緊的區域中。
  4. 如申請專利範圍第3項所述之半導體結構，更包含：一閘極電極，其係與界定該通道之該島的該部分彼此電氣隔絕。
  5. 如申請專利範圍第4項所述之半導體結構，其中該拉緊的區域可分隔該閘極電極。
  6. 如申請專利範圍第4項所述之半導體結構，其中該閘極電極大致覆蓋在該通道上。
  7. 如申請專利範圍第1項所述之半導體結構，更包含：一半導體元件，其係由該島製成。
  8. 如申請專利範圍第1項所述之半導體結構，其中該島是矽且該絕緣層變厚的區域是由該島氧化後所形成的。
  9. 如申請專利範圍第1項所述之半導體結構，其中該絕緣層是二氧化矽。
  10. 如申請專利範圍第9項所述之半導體結構，其中該處理晶圓是矽且該變厚的區域是由該處理晶圓氧化後所形成的。
  11. 如申請專利範圍第1項所述之半導體結構，其中該拉伸應力係能有效提高該拉緊的區域中之載子的移動力。
  12. 如申請專利範圍第1項所述之半導體結構，其中該 變厚區域的所增加的厚度是介於約5奈米至約10奈米間。
  13. 如申請專利範圍第1項所述之半導體結構，其中該絕緣層變厚的區域之厚度係遠大於夾住該變厚的區域兩邊之絕緣層周圍區域的厚度。
  14. 如申請專利範圍第1項所述之半導體結構，更包含：夾住該拉緊的區域之第一和第二固定物，該第一和第二固定物可有效的限制該島中該拉緊的區域使其不放鬆。
  15. 如申請專利範圍第14項所述之半導體結構，其中該第一和第二固定物包含可夾住該拉緊的區域兩邊之該島的相鄰區域。
  16. 一種製造使用一絕緣層上覆矽(SOI)基板的一拉緊的半導體結構的方法，該絕緣層上覆矽(SOI)基板具有由一半導體材料所組成的一主動層、一處理晶圓以及介於該主動層與該處理晶圓之間的一絕緣層，該方法包含：在主動層與該絕緣層之間的一介面處，以一熱氧化製程將該主動層的一區域中的該半導體材料專一性的氧化，使得該絕緣層的一區域的厚度會增加，該絕緣層的該區域會誘使該主動層的該區域出現拉伸應力，因而局部拉緊該主動層的該區域。
  17. 如申請專利範圍第16項所述之方法，其中該半導體材料是矽且將一帽蓋層設置在該主動層的該區域的一上表面上，使得該區域介於該帽蓋層與該絕緣層之間，且該專一性氧化該主動層的該區域中的該半導體材料的步驟包含：在該主動層的該區域中，讓該主動層的該半導體材料與一從周圍環境擴散穿過該帽蓋層的氧化物種氣體反應，以形成該絕緣層的該區域。
  18. 如申請專利範圍第17項所述之方法，其中將該主動層的該半導體材料與該氧化物種氣體反應的步驟包含：以一氧化遮罩覆蓋該帽蓋層；圖案化該氧化遮罩，用以在該氧化遮罩中界定複數個視窗，該視窗延伸至該帽蓋層；以及以該氧化遮罩阻隔該氧化物種氣體擴散穿過該帽蓋層至該視窗外。
  19. 如申請專利範圍第18項所述之方法，其中該氧化遮罩係由氮化矽所組成。
  20. 如申請專利範圍第16項所述之方法，更包含：在該主動層中形成一源極與一汲極，該源極與該汲極可 夾住一通道，至少一部份該通道係界定在該主動層的該區域中。
  21. 如申請專利範圍第20項所述之方法，更包含：形成一閘極電極，其藉由一閘極介電層與該主動層電氣隔絕，且該閘極電極覆蓋住該通道。
  22. 如申請專利範圍第21項所述之方法，其中該主動層的該區域可分隔該閘極電極，以界定複數個閘極部分。
  23. 如申請專利範圍第16項所述之方法，更包含：在該處理晶圓與該絕緣層之間且位於該主動層的該區域下的一介面處，專一性的氧化該處理晶圓之一區域，使得該絕緣層的該區域的厚度會增加。
  24. 如申請專利範圍第23項所述之方法，其中該絕緣層是由二氧化矽所組成且該基材是由矽所組成。
  25. 如申請專利範圍第16項所述之方法，其中該絕緣層是由二氧化矽所組成且該主動層是由矽所組成。
  26. 一種製造使用一絕緣層上覆矽(SOI)基板的一拉緊的半導體結構的方法，該絕緣層上覆矽(SOI)基板具有一主 動層、一處理晶圓以及介於該主動層與該處理晶圓之間的一絕緣層，該方法包含：在該主動層的一區域下的一位置處之位在該主動層與該絕緣層之間的一介面處，以一專一性熱氧化製程將該絕緣層的一區域變厚，以誘使該主動層的該區域出現拉伸應力，並因而局部拉緊該主動層的該區域。
  27. 如申請專利範圍第26項所述之方法，其中該主動層是由一半導體材料所組成，且使該絕緣層的該區域變厚的步驟更包含：在該區域中以該專一性熱氧化製程將該主動層的該半導體材料專一性氧化，使能局部提高該絕緣層的該區域的厚度。
  28. 如申請專利範圍第27項所述之方法，其中該半導體材料是矽且該主動層係由一帽蓋層所覆蓋，且使該絕緣層的該區域變厚的步驟包含：在該區域中讓該主動層的該半導體材料與一從周圍環境擴散穿過該帽蓋層至該主動層的該區域之氧化物種氣體反應，以形成該絕緣層的該區域。
  29. 如申請專利範圍第28項所述之方法，其中該讓主動層反應的步驟包含： 以一氧化遮罩覆蓋該帽蓋層；圖案化該氧化遮罩，用以在該氧化遮罩中界定複數個視窗，該視窗延伸至該帽蓋層；以及以該氧化遮罩阻隔該氧化物種氣體擴散穿過該帽蓋層至該視窗外。
  30. 如申請專利範圍第29項所述之方法，其中該氧化遮罩是由氮化矽所組成。
  31. 如申請專利範圍第26項所述之方法，更包含：在該主動層中形成一源極與一汲極，該源極與該汲極可夾住一通道，至少一部份該通道係界定在該主動層的該區域中。
  32. 如申請專利範圍第31項所述之方法，更包含：形成一閘極電極，其藉由一閘極介電層與該主動層電氣隔絕，且該閘極電極覆蓋住該通道。
  33. 如申請專利範圍第31項所述之方法，其中該主動層的該區域可分隔該閘極電極，以界定複數個閘極部分。
  34. 如申請專利範圍第26項所述之方法，更包含：在該處理晶圓與該絕緣層之間且位於該主動層的該區 域下的一介面處，以該專一性熱氧化製程專一性氧化該處理晶圓之一區域，使得該該絕緣層的該區域的厚度會增加。
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