CN1914722B - 制作应变绝缘体上硅结构的方法及用此方法形成的绝缘体上硅结构 - Google Patents

制作应变绝缘体上硅结构的方法及用此方法形成的绝缘体上硅结构 Download PDF

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CN1914722B
CN1914722B CN2005800031333A CN200580003133A CN1914722B CN 1914722 B CN1914722 B CN 1914722B CN 2005800031333 A CN2005800031333 A CN 2005800031333A CN 200580003133 A CN200580003133 A CN 200580003133A CN 1914722 B CN1914722 B CN 1914722B
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active layer
insulating barrier
silicon
semiconductor structure
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古川俊治
查尔斯·W.·考伯格三世
詹姆斯·A.·斯林科曼
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GlobalFoundries Inc
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Abstract

一种绝缘体上硅(SOI)器件和结构，在硅有源层中具有局部应变区域，通过增大隔开硅有源层和衬底的掩埋绝缘层的下方区域的厚度而形成。从绝缘层的下方加厚区域传递到上方应变区域的应力增大了有源层的这些受限区域中的载流子迁移率。形成在该硅有源层中和上的器件可受益于隔开的应变区域中的增大的载流子迁移率。

Description

制作应变绝缘体上硅结构的方法及用此方法形成的绝缘体上硅结构
技术领域
本发明一般涉及半导体结构和器件及其制作方法，更具体地，涉及制作方法以及绝缘体上硅(SOI)结构、器件和集成电路，它们的特征在于提高了的载流子迁移率。
背景技术
绝缘体上硅(SOI)结构由叠加在二氧化硅绝缘层(即掩埋氧化物，或“BOX”)上的薄的有源硅层构成，二氧化硅绝缘层本身也叠加在支撑硅衬底上。用于金属-氧化物-半导体场效应晶体管(MOSFET)技术和互补金属-氧化物-半导体(CMOS)集成电路的SOI结构的优点已经得到很好的证明。SOI结构的绝缘层使得场效应晶体管(FET)能够以高得多的速度工作，并且与传统的体硅技术相比电绝缘性能更好、电学损耗更小。结果是性能的提高和功耗的减小。
在传统MOSFET和CMOS技术中，制作在SOI结构上的场效应晶体管包括形成在有源硅层中的沟道。载流子迁移率是一个重要的参数，因为它直接影响到场效应晶体管的输出电流和开关性能。因此，提高器件性能的一个方法是通过使有源硅层发生双轴或单轴应变而提高沟道迁移率。净应变可通过在硅有源层中引入压应力或在硅有源层中引入张应力来提供。使硅层平面中的晶格发生局部或全局应变改变了硅层的电子能带结构。结果，面内载流子迁移率可提高十至二十五个百分比，提高了器件性能。
也可通过引入由晶格常数大于硅的晶格常数的材料形成的插入层对整个衬底上的硅层均匀地引入双轴张应变。例如，可以通过在掩埋氧化层和硅有源层之间引入渐变硅锗缓冲层和弛豫硅锗层的薄的组合层而在SOI结构中引入双轴应变有源硅层，硅有源层外延沉积在弛豫硅锗层上。张应变增大了衬底平面中的硅的原子间距，这增大了电子迁移率。层转移方法可用于去除硅锗层。均匀张应变的存在提高了n沟道场效应晶体管NFET的器件沟道中的电子迁移率，并对于垂直于PFET器件沟道中的载流子流的方向引入的张应变来说，提高了p沟道场效应晶体管(PFET)中的空穴迁移率。
单轴压应变可以通过工艺优化而局部地引入到硅层中。少量的应力可以通过操纵已有器件结构——例如盖帽层、间隔层和浅沟绝缘——的特性来引入。更大量的应力可通过例如仅在PFET的源和漏区中沉积一层渐变硅锗层来引入。局部引入硅锗层可以对PFET沟道增加压应变，这在局部增大了空穴迁移率。
使用硅锗层来形成应变硅具有一些缺点。硅锗层会在硅中引入缺陷，影响器件产率。在整个晶片上沉积全局性硅锗层对于分别优化NFET和PFET来说是不合适的。硅锗层还具有差的导热性，某些掺杂剂在硅锗层中扩散得更快，这会影响形成在有源层中的源和漏区中的扩散掺杂轮廓。另一个实际限制就是硅锗层促使增大了有源区的总厚度，而在现代器件设计中，有源区的厚度是要比例减薄的。
因此，需要一种在SOI结构的有源层中引入张应变而无需使用下层弛豫硅锗层的方法，还需要由该方法制作的具有应变有源层的SOI结构、器件和集成电路。
发明内容
根据本发明的原理，通过在绝缘体上硅衬底的有源层中引入张应变形成了具有应变有源层的SOI结构、器件和集成电路。无需引入下层硅锗层就给出了张应变。为此，这样的半导体结构通常包括半导体材料有源层、衬底以及置于有源层和衬底之间的绝缘层。绝缘层具有加厚区域，将张应力传到有源层上，有效地将应变引入到加厚区域之上的有源层的应变区域中。
根据本发明的原理，局部增大掩埋绝缘层的厚度将张应力局部转移到上层有源层中。张应力使氧化掩模所确定的有源层区域中发生应变。应变有源层的特征在于更大的载流子迁移率，从而提高了形成在应变有源层中和其上的器件的器件性能。无需依赖于复杂的膜沉积技术就可以将应变引入到有源层中，这是因为没有在器件结构中加入任何附加层就改变了下层绝缘层。特别地，可以使硅有源层应变，避免硅锗层的缺点。
附图说明
在此引入并构成本说明书的一部分的附图示出本发明的实施方案，并与上面给出的本发明的一般描述和下面给出的实施方案的详细描述一起用于解释本发明的原理。
图1为衬底的一部分的部分截面概略透视图。
图2为后续制造阶段类似于图1的视图。
图2A为沿图2的2A-2A线的剖视图。
图3为后续制造阶段类似于图2的视图。
图4为后续制造阶段类似于图3的视图。
图5为一系列后续制造阶段之后类似于图4的视图。
图6A为根据本发明替代实施方案的一系列后续制造阶段之后类似于图5的视图。
图6B为类似于图6A的视图。
图7为根据本发明替代实施方案的类似于图2的视图。
具体实施方式
参见图1，绝缘体上硅(SOI)衬底10包括硅有源层12，或另一合适的半导体材料，绝缘层16将其与处理晶片14垂直分隔开。绝缘层16使有源层12与处理晶片14电绝缘。SOI衬底10可以用任何标准技术来制作，例如晶片键合，或者氧注入分离(SIMOX)技术。在本发明所示出的实施方案中，可以一开始就用n型掺杂剂掺杂构成有源层12的硅使其变为n型，或用p型掺杂剂掺杂使其变为p型。处理晶片可由任何合适的半导体材料形成，包括但不局限于：硅和多晶态硅(多晶硅)。构成绝缘层16的介电材料通常为二氧化硅，厚度在大约五十(50)纳米至大约150纳米之间，但也并非如此限制。有源层12可以薄至大约十(10)纳米或更薄，通常在大约二十(20)纳米至大约150纳米之间。处理晶片14的厚度在图1中并没有按比例示出。
有源层12上通常盖有硬掩模材料(例如衬垫氮化物)的盖帽层22，以提供自对准上氧化物阻挡层和抛光停止层。为此，在有源层12上加上一层硬掩模材料的共形空白层，它可以是10至150纳米的氮化硅(Si3N4)。在共形空白层上涂上辐射敏感光刻胶层，用通过传统光刻版投射的辐射来曝光，在光刻胶层中形成潜在的具有预期的岛18的投射图像图案，并显影以将潜在图像图案转变成最终图像图案。腐蚀工艺(例如各向异性腐蚀工艺(反应离子腐蚀))除去盖帽层22中最终图像图案未覆盖的区域中的硬掩模材料。在腐蚀工艺完成之后从SOI衬底10上剥离光刻胶层。
根据传统设计技术选择每个岛18的线宽，在某些实施方案中，它处于大约15nm至大约125nm的范围内。绝缘层16以及相邻岛18之间的沟槽20提供了侧向电绝缘。
这里对像“竖直”、“水平”等这样的词语的引用只是作为建立参考框架的例子，而不是作为限制。用于此处的词语“水平”定义为平行于SOI衬底10的传统平面或表面的平面，而不考虑取向。词语“竖直”指的是垂直于如上定义的水平的方向。像“上”、“上方”、“下方”、“侧”(例如“侧壁”)、“更高”、“更低”、“之上”、“之下”和“下”都是相对于水平平面来定义。应当理解，只要不偏离本发明的精神和范围，还可以采用各种其它参考框架。
参见图2和2A，其中相似的附图标记指的是图1中相似的并处于随后制造阶段的特征，制作氧化掩模材料条26以确定窗口28，通过该窗口将会发生氧化。窗口28中的每一个隔开相邻的条26，图中只示出了一个窗口28。为了制作条26，在图1的结构上沉积氧化掩模材料空白层，并用标准光刻工艺和腐蚀工艺来构图。条26位于盖帽层22和绝缘层16上表面上与岛18、限制或侧翼窗口28一起的区域中，并覆盖这些区域。形成窗口28的定向腐蚀工艺留下氧化掩模材料隔离层30，覆盖有源层12的垂直侧壁中的每一个。形成窗口28的定向腐蚀工艺还应当停止在氧化掩模材料下方的薄腐蚀停止层材料上，以避免腐蚀盖帽层22。
参见图3，其中相似的附图标记指的是图2中相似的并处于随后制造阶段的特征，用合适的工艺在SOI衬底10的水平平面和有源层12的下方局部区域32中的区域上充分加厚绝缘层16。绝缘层16加厚的区域通常与有源层12的区域垂直重合。绝缘层16的加厚可来源于大量消耗与绝缘层16有相同延伸范围的有源层12的平坦下表面33和/或处理晶片14的平坦上表面35的材料以形成体积增大的具有新组分的材料的工艺，或者可以通过任何其它能够扩大或增加绝缘层16的有效厚度的机制来进行。区域32通常是有源层12的面内区域，在SOI衬底10的平面中与窗口28水平对齐。
绝缘层16的厚度增加的程度可以根据要形成在有源层12中的半导体器件所需的性能以及膨胀上的任何设计或物理限制而改变。
在本发明的示例性实施方案中，使用热氧化工艺来局部加厚SOI衬底12的绝缘层16，其中掩模24由不可氧化的材料(例如氮化硅)形成，用作氧化掩模。氧化工艺需要将SOI衬底10暴露在，例如氧化炉或快速热退火腔中的干燥或潮湿的充满氧气的加热环境中。选择氧化条件以使得绝缘层16只有在有源层12的区域32下方的区域中发生选择膨胀，并避免SOI衬底12上的均匀加厚绝缘层16。在某一特定实施方案中，在800℃至950℃下进行湿法氧化，氧化时间应足以使得区域32下方的区域上绝缘层的厚度增加1纳米至10纳米。在本发明的一个实施方案中，区域32下方氧化物厚度大约4.5纳米的增加在区域32中产生了大约百分之0.1的应变。绝缘层16的厚度增加由加厚区域上最大的厚度增加来确定，因为即使在区域32之下，厚度增加也是不均匀的，尽管本发明并非如此限制。
有源层12的氧化由来自加热环境中的氧化气体的气态氧化物质由于被形成绝缘层16的材料吸收而经过窗口28的输送引起。覆盖岛18的盖帽层22和掩模24的条26以及遮蔽岛18的竖直侧壁的间隔层30阻挡了来自充满氧气的环境中的气态氧化物质(通常为O2或H2O)直接进入有源层12，从而有源层12的侧壁和上表面基本不受氧化工艺的影响。
继续参见图3并根据示例性实施方案，气态氧化物质从每个窗口28扩散穿过绝缘层16以和有源层12下表面33中的硅发生化学反应。潜在地，如果构成处理晶片14的材料容易氧化的话，扩散物质可能会与处理晶片14的上表面35中的材料发生发应。对于有源层12在区域32中的部分来说，氧化物质进入有源层12的下表面33的扩散路径比处于区域32之外、掩模24的条26下方的区域中的要短。另外，且如果有的话，对于处理晶片14在区域32中的区域来说，氧化物质进入处理晶片14的上表面35的扩散路径比处理晶片14处于区域32外位于掩模24的条26下方的区域中的要短。因而，绝缘层16的有效厚度增加在区域32下方更大，绝缘层16可具有与有源层12的氧化部分相同且潜在地与处理晶片14的氧化部分相同的组分。正如已知的，所形成的二氧化硅的厚度等于所消耗的硅的厚度的大约2.27倍。绝缘层16的局部膨胀相对于被掩模24的条26覆盖的相邻区域竖直提升了覆盖在绝缘层16的加厚区域上的有源层12的区域32。
绝缘层16的膨胀压迫每个岛18的区域32中的有源层12的材料，这在区域32中引入净应变量。这一净局部应变量(它通常在一个百分比的十分之一到十分之二的范围内)调整了有源层12的应变区域32中的载流子的电学特性。如果有源层12是硅，则应变使得区域32中的载流子迁移率增大了差不多百分之二十或更大。因而，如果例如器件沟道位于应变区域32中的话随后制作在每个岛18中的器件性能将得到提高。可以调节氧化的量以影响引入到应变区域32中的应变程度。另外，窗口28的宽度对引入到区域32中的应变也有影响。
参见图4，其中相似的附图标记指的是图3中相似的并处于随后制造阶段的特征，用对有源层12和绝缘层16的材料具有选择性的腐蚀工艺将掩模24(图3)从SOI衬底10上剥离。如果掩模24和盖帽层22由相同材料形成，则盖帽层22的厚度必须大于掩模24的厚度从而条26之间盖帽层22不会被完全去除。先前位于掩模24之下的岛18的区域基本由有源层12的侧面区域在绝缘层16上的附着来锚定下来，从而防止或限制了应变区域32的弛豫。结果，应变区域32被绝缘层16在区域32下方的合适位置中的增加的厚度或膨胀永久压迫。如果预计会有一些弛豫，那么可以增大区域32中的初始应变以补偿弛豫。
参见图5、6A和6B，其中相似的附图标记指的是图4中相似的并处于随后制造阶段的特征，半导体器件形成在岛18之中和之上，岛18有沟道区域位于应变区域32中，这增大了器件中的载流子迁移率，从而器件性能得到提高。这里所示的MOSFET器件并不是限制性的，正如本领域技术人员所知的，其它类型的半导体器件(例如存储单元、其它类型的晶体管等)也可受益于此处所描述的应变区域。
特别地，参见图5，某一类型的半导体器件34a可以是金属-氧化物-半导体场效应晶体管(MOSFET)，每个都具有源/漏区域36、38和位于确定在源/漏区域36、38之间的有源层12中的沟道42上方的静电耦合栅电极40。薄的栅电介质44将栅电极42与沟道42电绝缘。用于形成栅电极42的材料可以是例如多晶硅、钨，或任何其它希望的材料，而源/漏区域36、38和它们的扩展部分可以通过注入合适的掺杂剂物质来形成。正如技术中所众所周知的，可以在栅电极42的竖直侧壁上再加上一种材料(例如氮化硅)的侧壁间隔层37、39。间隔层37、39和栅电极42一起用作源/漏区域36、38的深掺杂部分的注入的自对准掩模。隔离区域43提供有源层12的相邻岛18之间的电隔离。隔离区域43填入合适的介电材料，例如化学气相沉积(CVD)所共形沉积的二氧化硅，并由化学机械抛光(CMP)工艺或任何其它合适的平面化技术来抛平并平面化。盖帽层22用作平面化工作的抛光停止层，并在平面化工作之后去除。
载流子在源/漏区域36、38之间通过沟道42流动，正比于沟道42中的电阻率变化，后者正比于施加在栅电极40上的电压。器件34a被制作成每个沟道42都与其中一个应变区域32相重合。在本发明的某些实施方案中，器件3a4为n沟道场效应晶体管(NFET)而任何出现在集成电路中的p沟道场效应晶体管(PFET)都形成在SOI衬底的没有应变区域32的区域中。场效应晶体管用本领域技术人员所熟知的传统制作工艺来形成。
特别地，参见图6A和6B，另一种类型的半导体器件34b可以是自对准双栅鳍式场效应晶体管(finFET)，每个都具有薄的垂直层(鳍(fin))，提供沟道46和确定两个独立的位于沟道区域46侧面的栅部分48a、48b的栅电极48(图5C)。栅电极48位于源/漏区域50、52之间并覆在沟道46之上。栅电极48通过栅电介质47与栅电极48电绝缘。间隔层54、56位于栅电极48的侧面。器件34b制作成使得沟道46与应变区域32重合。本发明预期全部或部分盖帽层22可以留在完成的器件结构中的有源层12上。finFET由本领域技术人员所熟知的传统制作工艺来形成。
参见图7，其中相似的附图标记指的是图2中相似的特征，在使用掩模24并构图之前，可以在盖帽层22上加一垫层58。垫层58是任何用作构图掩模24的腐蚀和去除掩模24的腐蚀过程中的腐蚀停止层。垫层58有效地防止了这些腐蚀工艺对条26之间的盖帽层22的减薄。一种合适的用作垫层58的材料是二氧化硅，如果盖帽层22是氮化硅的话，厚度在大约2纳米至大约10纳米。盖帽层22的过度减薄会降低其作为抛光停止层和氧化掩模的有效性。
虽然通过描述各种实施方案示出了本发明并且对这些实施方案都进行了相当详细的描述，但是并不是要将所附权利要求的范围约束在或以任何方式局限在这样的细节上。对本领域技术人员来说，将能很容易看到另外的优点和调整。这样，本发明在其更广的方面中并不局限于所示和描述的特定细节代表性装置和方法以及示意性实施例。因此，只要不偏离申请人的一般发明性思想，就可以与这些细节有所不同。

Claims (34)

1.一种半导体结构，包含：半导体材料有源层，所述有源层包括应变区域和沟道区域，其中所述沟道区域至少部分位于所述应变区域中；绝缘体上硅SOI衬底；置于所述有源层和所述SOI衬底之间的绝缘层，所述绝缘层包含位于所述应变区域下方的加厚区域，其中所述加厚区域位于所述沟道区域之下，所述加厚区域将张应力传递到所述应变区域。
2.根据权利要求1的半导体结构，其中所述绝缘层为掩埋氧化物层，而所述有源层为硅。
3.根据权利要求1的半导体结构，进一步包含：被限定在所述有源层中的源；被限定在所述有源层中的漏，其中所述沟道区域被限定在所述有源层的位于所述源和所述漏之间的部分中。
4.根据权利要求3的半导体结构，进一步包含：与所述有源层限定所述沟道区域的所述部分电绝缘的栅电极。
5.根据权利要求4的半导体结构，其中所述应变区域分开所述栅电极。
6.根据权利要求4的半导体结构，其中所述栅电极基本上覆盖所述沟道区域。
7.根据权利要求1的半导体结构，进一步包含：用所述有源层制作的半导体器件。
8.根据权利要求1的半导体结构，其中所述有源层为硅，而所述绝缘层的所述加厚区域通过所述有源层的氧化来形成。
9.根据权利要求1的半导体结构，其中所述绝缘层为二氧化硅。
10.根据权利要求9的半导体结构，其中所述加厚区域由所述SOI衬底的氧化来形成。
11.根据权利要求1的半导体结构，其中所述张应力对于提高所述应变区域中的载流子迁移率是有效的。
12.根据权利要求1的半导体结构，其中所述加厚区域的厚度增加5纳米至10纳米的增量。
13.根据权利要求1的半导体结构，其中所述绝缘层的所述加厚区域的厚度大于所述绝缘层位于所述加厚区域侧面的环绕区域的厚度。
14.根据权利要求1的半导体结构，进一步包含：第一和第二锚定片，位于所述应变区域侧面，所述第一和第二锚定片用于限制所述有源层的所述应变区域的弛豫。
15.根据权利要求14的半导体结构，其中所述第一和第二锚定片包含所述有源区位于所述应变区域侧面的相邻区域。
16.一种在绝缘体上硅SOI衬底上制作应变半导体结构的方法，包含：在有源层和下方绝缘层之间的位置处局部地选择氧化有源层，在该位置处上增大绝缘层的厚度以形成加厚区域，加厚区域在有源层中引入张应力以在加厚区域上的有源层中形成应变区域，其中所述应变区域包括至少部分沟道区域，并且所述加厚区域位于所述沟道区域之下。
17.根据权利要求16的方法，其中有源层为硅，而选择氧化绝缘层包含：使有源层与从周围环境扩散到绝缘层中的气态氧化物质发生反应以形成绝缘层的加厚区域。
18.根据权利要求17的方法，其中选择氧化绝缘层包含：用氧化掩模覆盖绝缘层和有源层；在氧化掩模中形成窗口，使得气态氧化物质能够传送到绝缘层中以便随后的向加厚区域的扩散。
19.根据权利要求18的方法，其中覆盖绝缘层和有源层包含：形成氮化硅的构图层。
20.根据权利要求16的方法，进一步包含：在有源层中形成源和漏，源和漏位于至少部分被限定于有源层的应变区域中的沟道区域的侧面。
21.根据权利要求20的方法，进一步包含：形成栅电极，与有源层电绝缘并覆盖所述沟道区域。
22.根据权利要求21的方法，其中应变区域分开栅电极。
23.根据权利要求16的方法，进一步包含：选择氧化支持绝缘层的SOI衬底位于应变区域下方的位置处的部分，在该位置处上增大绝缘层的厚度以形成加厚区域。
24.根据权利要求23的方法，其中绝缘层包含二氧化硅。
25.根据权利要求16的方法，其中绝缘层包含二氧化硅，而有源层包含硅。
26.一种在绝缘体上硅SOI衬底上制作应变半导体结构的方法，包含：在位于有源层的应变区域下方的位置处加厚绝缘层的加厚区域，使得在有源层中引入张应力，并由此在有源层中形成应变区域，其中所述应变区域包括至少部分沟道区域，并且所述加厚区域位于所述沟道区域之下。
27.根据权利要求26的方法，其中加厚加厚区域进一步包含：在有源层和绝缘层之间的介面处选择氧化有源层，在该介面处增大绝缘层的厚度以形成加厚区域。
28.根据权利要求27的方法，其中有源层为硅，且加厚加厚区域包含：使有源层与来自周围环境在绝缘层中扩散至应变区域下方用于形成绝缘层的加厚区域的位置的气态氧化物质发生发应。
29.根据权利要求28的方法，其中与有源层反应包含：用氧化掩模覆盖绝缘层和有源层；在氧化掩模中形成窗口，使得气态氧化物质能够传送到绝缘层中以便随后的扩散。
30.根据权利要求29的方法，其中覆盖绝缘层和有源层包含：形成氮化硅的构图层。
31.根据权利要求26的方法，进一步包含：在有源层中形成源和漏，源和漏位于至少部分被限定于有源层的应变区域中的沟道区域的侧面。
32.根据权利要求31的方法，进一步包含：形成与有源层电绝缘并覆盖沟道区域的栅电极。
33.根据权利要求32的方法，其中应变区域分开栅电极。
34.根据权利要求26的方法，进一步包含：在位于应变区域下方的位置处选择地氧化支持绝缘层的SOI衬底，使得该位置处上增大绝缘层的厚度以形成加厚区域。
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