TWI389285B - 半導體裝置及使用其之半導體模組 - Google Patents

半導體裝置及使用其之半導體模組 Download PDF

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Publication number
TWI389285B
TWI389285B TW097105624A TW97105624A TWI389285B TW I389285 B TWI389285 B TW I389285B TW 097105624 A TW097105624 A TW 097105624A TW 97105624 A TW97105624 A TW 97105624A TW I389285 B TWI389285 B TW I389285B
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Taiwan
Prior art keywords
circuit board
semiconductor element
semiconductor
main surface
electrode pad
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TW097105624A
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English (en)
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TW200901427A (en
Inventor
Ryoji Matsushima
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Toshiba Kk
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Publication of TW200901427A publication Critical patent/TW200901427A/zh
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Publication of TWI389285B publication Critical patent/TWI389285B/zh

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Description

半導體裝置及使用其之半導體模組
本發明係關於半導體裝置及使用其之半導體模組。本申請案係基於2007年2月20日所申請之日本申請案特願2007-038862號之優先權之權利。因此，主張其優先權之權利。於此，將前述日本申請案全部內容作為參照文獻併入本文中。為實現半導體裝置之小型化及高密度安裝化，在一個封裝體內積層複數之半導體元件後密封之堆疊型多晶片封裝已實用化。堆疊型多晶片封裝中，複數之半導體元件於具有外部連接端子之電路基板或導線架等電路基材上依次積層。複數之半導體元件與電路基材之連接上應用打線接合時，為使可與金屬線連接，半導體元件以面朝上之狀態積層。
先前之堆疊型多晶片封裝中，連接於最上部之半導體元件的金屬線，必然配置為通過超出複數之半導體元件之積層厚度的部分。將具有此種積層構造與金屬線配線形狀之複數之半導體元件用樹脂密封時，其密封樹脂之厚度須為對最上部之半導體元件之金屬線配線形狀之厚度。如此，先前之堆疊型多晶片封裝中，對最上部之半導體元件之金屬線配線形狀成為使封裝體厚度變厚之主要原因。
於日本特開2001-036000號公報中，記載有使2個半導體元件各自之墊形成面彼此相對配置之半導體封裝。然而，此處於半導體元件之結合墊形成面上形成絕緣膜，進而於絕緣膜表面形成金屬配線，此等金屬配線間藉由焊球連接。因此，半導體封裝體本身之厚度不能夠充分變薄。並且，安裝板與半導體封裝體之連接係於2個半導體元件間之間隙配置接合引線而實施。此點亦有加厚半導體封裝體厚度之傾向。
本發明態樣之半導體裝置具有：電路基板，係具備具有第1連接墊之第1主面、具有第2連接墊且與上述第1主面成相反側之第2主面、以貫通上述第1連接墊附近之方式設置之第1開口部、及以貫通上述第2連接墊附近之方式設置之第2開口部；第1半導體元件，係搭載於上述電路基板之上述第1主面上，且具有露出於上述第2開口部內之第1電極墊；第2半導體元件，係搭載於上述電路基板之上述第2主面上，且具有露出於上述第1開口部內之第2電極墊；第1連接構件，係經由上述第1開口部配置成電性連接上述第1連接墊與上述第2電極墊；第2連接構件，係經由上述第2開口部配置成電性連接上述第2連接墊與上述第1電極墊；及密封部，係將上述第1及第2半導體元件與上述第1及第2連接構件和上述電路基板之一部分一同密封。
本發明之其他態樣之半導體裝置具有：電路基板，係具備具有第1連接墊之第1主面、具有第2連接墊且與上述第1主面成相反側之第2主面、以貫通上述第1連接墊附近之方式設置之第1開口部、及以貫通上述第2連接墊附近之方式設置之第2開口部；第1元件群，係具備具有電極墊之複數之半導體元件，且上述複數之半導體元件以使上述電極墊露出於上述第2開口部內之方式，以階梯狀積層於上述電路基板之上述第1主面上；第2元件群，係具備具有電極墊之複數之半導體元件，且上述複數之半導體元件以使上述電極墊露出於上述第1開口部內之方式，以階梯狀積層於上述電路基板之上述第2主面上；第1連接構件，係經由上述第1開口部配置成電性連接上述第1連接墊與構成上述第2元件群之上述複數之半導體元件之上述電極墊；第2連接構件，係經由上述第2開口部配置成電性連接上述第2連接墊與構成上述第1元件群之上述複數之半導體元件之上述電極墊；及密封部，係將上述第1及第2元件群與上述第1及第2連接構件和上述電路基板之一部分一同密封。
本發明之態樣之半導體模組，係具備複數之本發明之態樣之半導體裝置，且上述複數之半導體裝置係積層。
以下，對用於實施本發明之形態一面參照圖式進行說明。圖1、圖2以及圖3係顯示本發明之實施形態之半導體裝置構成之圖，圖1係其剖面圖，圖2係平面圖，圖3係背面圖。此等圖所示之半導體裝置1具有可以進行兩面安裝之電路基板2。電路基板2係於例如樹脂基板、陶瓷基板、玻璃基板等絕緣基板或半導體基板之內部或表面設有配線網(未圖示)之基板。作為電路基板2之代表例，可列舉使用玻璃-環氧樹脂或BT樹脂(雙馬來醯亞胺‧三氮烯樹脂)的印刷配線基板。
電路基板2具有成為第1元件搭載面之第1主面(A面)2a、成為第1主面2a相反側之第2元件搭載面之第2主面(B面)2b。第1主面2a之中央部附近作為元件搭載區域。同樣，第2主面2b之中央部附近作為元件搭載區域。如此，電路基板2可以於表裏兩面搭載半導體元件，具有半導體元件之兩面安裝所對應之配線網。
進而，於電路基板2之第1及第2主面2a、2b分別設有外部連接用之陸區3、4。此等陸區3、4形成於除了由後述密封部之密封區域外之外側區域，分別沿電路基板2之相對兩邊(外形邊)排列。於第2主面2b側之陸區4上設有焊料凸塊等外部連接端子5。另外，於沒有將半導體裝置1多段積層而模組化之情形下，未必需要第1主面2a側之陸區3。
於電路基板2之第1主面2a設有至少一部分經由配線網與陸區3、4電性連接之第1連接墊6。第1連接墊6設於第1主面2a之元件搭載區域與電路基板2之相對2個外形邊中之一邊(第1外形邊)之間。第1連接墊6，以與電路基板2之第1外形邊平行之方式大致成直線狀排列。如後述，第1連接墊6在對第2半導體元件等進行打線結合時作為連接部發揮機能。
於電路基板2之第2主面2b設有至少一部分經由配線網與陸區3、4電性連接之第2連接墊7。第2連接墊7設於第2主面2b之元件搭載區域與電路基板2之相對2個外形邊中之另一邊(第2外形邊)之間。第2連接墊7，以與電路基板2之第2外形邊平行之方式大致成直線狀排列。如後述，第2連接墊7在對第1半導體元件等進行打線結合時作為連接部發揮機能。
電路基板2具有貫通第1連接墊6附近的第1開口部8、貫通第2連接墊7附近的第2開口部9。第1開口部8設於電路基板2之第1外形邊與第1連接墊6之形成區域之間，具有沿第1連接墊6之排列方向之長形狀。第2開口部9設於電路基板2之第2外形邊與第2連接墊7之形成區域之間，具有沿第2連接墊7之排列方向之長形狀。如後述，此等開口部8、9成為將電路基板2與半導體元件電性連接之連接構件的配置區域。
於電路基板2之第1主面2a經由第1接合材層11接合第1半導體元件10。第1半導體元件10具有與包含電晶體之積體電路的形成面配置於同一面上之第1電極墊12。第1電極墊12沿第1半導體元件10之一邊大致排成一列。即，第1半導體元件10具有單側墊構造。並且，第1半導體元件10，以具有第1電極墊12之電極形成面與第1主面(上面)2a相對之方式，以面朝下之狀態搭載於電路基板2之第1主面2a上。
第1半導體元件10配置成沿第1電極墊12之形成區域之邊(墊排列邊)成為第2開口部9側。並且，第1半導體元件10配置成第1電極墊12露出於第2開口部9內。藉此，可防止相對第1主面(上面)2a以面朝下狀態配置之第1半導體元件10的電極墊12被電路基板2遮蓋。露出於第2開口部9內之第1電極墊12，在使第1半導體元件10之電極形成面與第1主面(上面)2a相對之後可以進行打線接合等。
於電路基板2之第2主面2b，經由第2接合材層14接合第2半導體元件13。第2半導體元件13具有與包含電晶體之積體電路的形成面配置於同一面上之第2電極墊15。第2電極墊15沿第2半導體元件13之一邊大致排成一列。第2半導體元件13亦與第1半導體元件10相同，具有單側墊構造。並且，第2半導體元件13，以具有第2電極墊15之電極形成面與第2主面(下面)2b相對之方式，以面朝上之狀態搭載於電路基板2之第2主面2b上。
第2半導體元件13配置成沿第2電極墊15之形成區域之邊(墊排列邊)成為第1開口部8側。並且，第2半導體元件13配置成第2電極墊15露出於第1開口部8內。藉此，可防止相對第2主面(下面)2b以面朝上狀態配置之第2半導體元件13的電極墊15被電路基板2遮蓋。露出於第1開口部8內之第2電極墊15，在使第2半導體元件13之電極形成面與第2主面(下面)2b相對之後可以進行打線接合等。
如此，第1半導體元件10與第2半導體元件13各別之電極形成面經由電路基板2相對，且分別之墊排列邊之配置以相反方向(相對於電路基板2之面方向成相反側)配置。再者，使第1電極墊12露出於第2開口部9內，且使第2電極墊15露出於第2開口部9相反側之第1開口部8內。藉此，不會增加密封厚度至經由電路基板2積層之第1及第2半導體元件10、13之厚度以上，可以將電極墊12、15與電路基板2連接。
再者，於第1半導體元件10上經由第3接合材層18接合具有單側排列構造之第3電極墊16之第3半導體元件17。第3半導體元件17以面朝下狀態積層於第1半導體元件10上，使其電極形成面與第1半導體元件10之電極形成面之相反側的面(背面(圖中為上面))相對。此等半導體元件10、17以一致方向積層，使電極墊12、16彼此接近。第3半導體元件17與第1半導體元件10於中心位置上錯開後成階梯狀積層，使第3電極墊16露出。第3電極墊16與第1電極墊12相同，露出於第2開口部9內。
第1半導體元件10與第3半導體元件17構成搭載於電路基板2之第1主面2a上之第1元件群。構成第1元件群之半導體元件數不限於2個，亦可為3個或3個以上。第1元件群由複數之半導體元件構成。然而，電路基板2之第1主面2a上搭載之半導體元件數亦可為1個。圖1所示之半導體裝置1亦可具有於電路基板2之第1主面2a僅搭載第1半導體元件10之構成。
第2半導體元件13上(立體上為下側)，經由第4接合材層21接合具有單側排列構造之第4電極墊19之第4半導體元件20。第4半導體元件20以面朝上狀態積層於第2半導體元件13上，使其電極形成面與第2半導體元件13之電極形成面之相反側的面(背面(圖中為下面))相對。此等半導體元件13、20以一致方向積層，使電極墊15、19彼此接近。第4半導體元件20與第3半導體元件13於中心位置上錯開後成階梯狀積層，使第4電極墊19露出。第4電極墊19與第2電極墊15相同，露出於第1開口部8內。
第2半導體元件13與第4半導體元件20構成搭載於電路基板2之第2主面2b上之第2元件群。構成第2元件群之半導體元件數不限於2個，亦可為3個或3個以上。第2元件群由複數之半導體元件構成。然而，電路基板2之第2主面2b上搭載之半導體元件數亦可為1個。圖1所示之半導體裝置1亦可具有於電路基板2之第2主面2b僅搭載第2半導體元件13之構成。
於第1半導體元件10上積層第3半導體元件17之3層積層構造、甚至於第2半導體元件13上積層第4半導體元件20之4層積層構造，其密封厚度與經由電路基板2積層之複數的半導體元件(第1至第3半導體元件10、13、17，或第1至第4半導體元件10、13、17、20)之厚度相同。之後，可將複數之半導體元件之電極墊與電路基板2連接。第1至第4半導體元件10、13、17、20適用如NAND型快閃記憶體等記憶體元件，但不限於此。
第1開口部8係提供設於電路基板2之第1主面2a上之第1連接墊6與第2及第4半導體元件13、20之電極墊15、19之連接空間。第1開口部8配置有第1連接構件。第1連接墊6與第2半導體元件13之電極墊15，經由以第1開口部8為中介配置之第1金屬線(Au線等)22電性連接。第2電極墊15藉由利用第1開口部8，經由第1金屬線22與搭載有第2半導體元件13之電路基板2之第2主面2b相反側的第1主面2a上設置之第1連接墊6電性連接。
第4半導體元件20之電極墊19亦經由以第1開口部8為中介配置之第1金屬線22與第1連接墊6電性連接。在第2電極墊15與第4電極墊19之電性特性或信號特性相同之情形，能夠將第4電極墊19與第2電極墊15與第1連接墊6藉由第1金屬線22依次連接。此情形之金屬線22可分別實施打線接合步驟進行連接，亦可用1根金屬線22依次連接第4電極墊19與第2電極墊15與第1連接墊6。
第2開口部9係提供設於電路基板2之第2主面2b上之第2連接墊7與第1及第3半導體元件10、17之電極墊12、16之連接空間。第2開口部9配置有第2連接構件。第2連接墊7與第1半導體元件10之電極墊12，經由以第2開口部9為中介配置之第2金屬線(Au線等)23電性連接。第1電極墊12藉由利用第2開口部9，經由第2金屬線23與搭載有第1半導體元件10之電路基板2之第1主面2a相反側的第2主面2b上設置之第2連接墊7電性連接。
第3半導體元件17之電極墊16亦經由以第2開口部9為中介配置之第2金屬線23與第2連接墊7電性連接。在第1電極墊12與第3電極墊16之電性特性或信號特性相同之情形，能夠將第3電極墊16與第1電極墊12與第2連接墊7藉由第2金屬線23依次連接。此情形之金屬線23可分別實施打線接合步驟進行連接，亦可用1根金屬線23依次連接第3電極墊16與第1電極墊12與第2連接墊7。
圖1及圖2所示之半導體裝置1，作為將電路基板2之連接墊6、7與半導體元件10、13、17、20之電極墊12、15、16、19電性連接之連接構件，具有金屬線(接合引線)22、23。連接構件不限於金屬線。連接構件亦可為金屬配線層等。即，連接墊6、7與電極墊12、15、16、19之電性連接不限於打線接合，使用金屬配線層之連接構造等亦適用。
第1至第4半導體元件10、13、17、20與第1及第2金屬線22、23及電路基板2之一部分一同用環氧樹脂等密封樹脂24密封。密封樹脂24形成於除電路基板2之端子形成區域以外之區域，使陸區3、4及外部連接端子5露出。藉此構成半導體裝置1。密封樹脂24形成為使電路基板2之第1主面2a側之第3半導體元件17之背面露出，且形成為使第2主面2b側之第4半導體元件20之背面露出。第3及第4半導體元件13、20之背面未必必須露出，亦可由密封樹脂24覆蓋。
如上述，由於第1及第2金屬線22、23分別配置於開口部8、9內，故密封樹脂24之厚度可等同於經由電路基板2積層之半導體元件10、13、17、20之厚度。因此，將積層之半導體元件10、13、17、20與電路基板2藉由打線接合等進行電性連接後，可減小密封樹脂24之厚度。藉由使第3及第4半導體元件13、20之背面(構成第1及第2元件群之半導體元件中分別位於最上層之半導體元件之背面)露出，密封樹脂24之厚度為最小。
由於密封樹脂24之厚度不受金屬線形狀之影響，故能夠根據電路基板2之厚度與複數之半導體元件之厚度的合計厚度進行設定。因此，可以實現具有複數之半導體元件10、13、17、20之半導體裝置1的小型及薄型化。將第3及第4半導體元件13、20之背面用密封樹脂24覆蓋之情形，只要將密封樹脂24之厚度設定於能夠覆蓋第3及第4半導體元件13、20之範圍內即可，故可抑制密封樹脂24之厚度增加。因此，可以實現半導體裝置1之薄型化。
此實施形態之半導體裝置1例如可以按照以下描述進行製作。關於半導體裝置1之製造步驟，參照圖4至圖10進行說明。首先，如圖4所示，準備具有陸區3(4)與第1及第2開口部8、9之電路基板2。在此，電路基板2作為具有複數之裝置形成區域的基板板體(電路基板板體)31供給於半導體裝置1之製造步驟。圖4顯示電路基板2之第1主面2a。
基板板體31具有複數之相當於1個電路基板2(以及使用其之半導體裝置1)的裝置形成區域32。在此，使用於長向連續複數個三連構造之裝置形成區域32之基板板體31。圖4中省略其圖示，但於電路基板2之表裏兩面分別形成有連接墊6、7。
其次，如圖5及圖6所示，實施半導體元件之安裝步驟及連接步驟。圖5及圖6係放大顯示基板板體31中之1個電路基板2(裝置形成區域32)。根據此等圖示對半導體元件之搭載步驟及連接步驟進行說明。再者，實際之步驟係對基板板體31之複數的電路基板2(裝置形成區域32)依次實施半導體元件之搭載步驟及連接步驟。
首先，如圖5A所示，於電路基板2(裝置形成區域32)之第1主面2a之中央附近形成接合材層11。其次，如圖5B所示，於電路基板2之第1主面2a上經由接合材層11搭載第1半導體元件10。之後，如圖5C所示，於第1半導體元件10上積層第3半導體元件17。使第1及第3半導體元件10、17之方向一致，錯開中心位置後成階梯狀積層。另外，第1及第3半導體元件10、17以覆蓋第2開口部9之方式配置。
其次，如圖6A所示，於電路基板2(裝置形成區域32)之第2主面2b之中央附近形成接合材層14。其次，如圖6B所示，於電路基板2之第2主面2b上經由接合材層14搭載第2半導體元件13。之後，如圖6C所示，於第2半導體元件13上積層第4半導體元件20。使第2及第4半導體元件13、20之方向一致，錯開中心位置後成階梯狀積層。另外，第2及第4半導體元件13、20以覆蓋第1開口部8之方式配置。
其後，如圖7A所示，對搭載於電路基板2之第2主面2b之第2及第4半導體元件13、20，從電路基板2之第1主面2a側經由第1開口部8實施打線接合步驟。即，將設於電路基板2之第1主面2a之第1連接墊6、搭載於電路基板2之第2主面2b之第2及第4半導體元件13、20之電極墊15、19藉由Au線等構成之第1金屬線(接合引線)22進行電性連接。
其後，如圖7B所示將電路基板2翻面，對搭載於第1主面2a之第1及第3半導體元件10、17，從電路基板2之第2主面2b側經由第2開口部9實施打線接合步驟。即，將設於電路基板2之第2主面2b之第2連接墊7、搭載於電路基板2之第1主面2a之第1及第3半導體元件10、17之電極墊12、16藉由Au線等構成之第2金屬線(接合引線)23進行電性連接。
圖8顯示藉由實施圖5A至圖5C、圖6A至圖6C、以及圖7A至圖7B所示之各步驟，於基板板體31之裝置形成區域32(電路基板2)分別搭載複數之半導體元件(10、13、17、20)之狀態。圖8中，搭載於各裝置形成區域32之半導體元件(10、13、17、20)分別經由金屬線(22、23)與電路基板2電性連接。
其後，如圖9所示，將密封樹脂24例如進行射出成形，使電路基板2之表裏兩面2a、2b一同進行樹脂成形。在此，將三連構造之裝置形成區域32之表裏兩面一同射出成形。從半導體裝置1之厚度的觀點出發，密封樹脂24宜以使最外層之半導體元件17、20之背面露出之方式形成。然而，在提高半導體裝置1之可靠性時，將最外層之半導體元件17、20之背面用密封樹脂24覆蓋亦為有效。
其後，如圖10所示，於設於電路基板2之第2主面(背面)2b側之陸區4上接合焊球作為外部連接端子5。然後，將業已實施半導體元件10、13、17、20之搭載步驟、藉由金屬線22、23之連接步驟、藉由密封樹脂24之密封步驟、外部連接端子5之形成步驟之基板板體31沿各裝置形成區域32切斷，藉此製作單片化之半導體裝置1。
上述實施形態之半導體裝置1可作為半導體封裝體直接使用。此情形下，電路基板2之厚度為100μm、各半導體元件10、13、17、20之厚度為60μm、各接合材層11、14、18、21之厚度為10μm時，密封樹脂24之厚度可為相當於各構成要素之積層厚之380μm。即使考慮外部連接端子5之安裝高度(例如320μm)，亦能夠使半導體裝置1之全高為例如500μm左右。
半導體裝置1除作為個別半導體封裝體使用之外，還作為多層積層之半導體模組使用。圖11顯示複數之半導體裝置1積層之構造(POP構造)的半導體模組41。圖11顯示將4個半導體裝置1積層之狀態。複數之半導體裝置1間的電性連接，藉由依次連接設於電路基板2之第1主面2a側之陸區3與形成於第2主面2b側之外部連接端子5而實施。即，將位於下層側之半導體裝置1之陸區3與位於上層側之半導體裝置1之外部連接端子5依次連接。
圖12及圖13係顯示於安裝板42之表裏兩面分別以4連狀態安裝4層構造之半導體模組41之半導體模組43。即，安裝板42之表面安裝有4個將半導體裝置1以4層積層構成之半導體模組41。安裝板42之背面亦裝有4個相同之半導體模組41。因此，安裝板42上裝有8個半導體模組41，半導體裝置1之合計數為32個。如此，半導體模組可以具有將半導體裝置1以多層‧複數安裝之構造。
半導體模組41、43能夠根據半導體裝置1之薄型化及連接高度之降低進行薄型化。圖11所示之半導體模組41，在將密封樹脂24之厚度為380μm、全高為500μm之半導體裝置1以4層積層之情形，其高度(模組高)可以為1.7mm左右。半導體模組41、43不限於將搭載有NAND型快閃記憶體之半導體裝置1以複數積層之構造。半導體模組可以適用將搭載有邏輯元件之半導體裝置與搭載有NAND型快閃記憶體之半導體裝置積層之構造、進而將搭載有DRAM之半導體裝置積層之構造等各種形態。
另外，本發明不限於上述實施形態，亦適用於電路基板之兩面分別搭載半導體元件且將電路基板與半導體元件連接之各種構造之半導體裝置。本發明中亦包括此等半導體裝置。本發明之實施形態可在本發明之技術思想範圍內進行擴充或更改，其擴充、更改之實施形態亦包含於本發明之技術範圍內。
1．．．半導體裝置
2．．．電路基板
2a．．．第1主面
2b．．．第2主面
3．．．陸區
4．．．陸區
5．．．外部連接端子
6．．．第1連接墊
7．．．第2連接墊
8．．．第1開口部
9．．．第2開口部
10．．．第1半導體元件
11．．．第1接合材層
12．．．第1電極墊
13．．．第2半導體元件
14．．．第2接合材層
15．．．第2電極墊
16．．．第3電極墊
17．．．第3半導體元件
18．．．第3接合材層
19．．．第4電極墊
20．．．第4半導體元件
21．．．第4接合材層
22．．．第1金屬線
23．．．第2金屬線
24．．．密封樹脂
31．．．基板板體
32．．．裝置形成區域
41．．．半導體模組
42．．．安裝板
43．．．半導體模組
圖1係顯示實施形態之半導體裝置構成之剖面圖。
圖2係圖1所示之半導體裝置之平面圖。
圖3係圖1所示之半導體裝置之背面圖。
圖4係顯示用於半導體裝置之製造步驟之基板板體之平面圖。
圖5A至圖5C係放大顯示半導體裝置之製造步驟中將半導體元件搭載於電路基板之第1主面上之階段之圖。
圖6A至圖6C係放大顯示半導體裝置之製造步驟中將半導體元件搭載於電路基板之第2主面上之階段之圖。
圖7A及圖7B係放大顯示半導體裝置之製造步驟中之打線接合階段之圖。
圖8係顯示半導體裝置之製造步驟中將半導體元件安裝於基板板體之裝置形成區域後之狀態的平面圖。
圖9係顯示半導體裝置之製造步驟中將基板板體之裝置形成區域樹脂密封後之狀態的平面圖。
圖10係顯示半導體裝置之製造步驟中於基板板體之裝置形成區域形成外部連接端子之狀態的平面圖。
圖11係顯示實施形態之半導體模組之剖面圖。
圖12係顯示將圖11所示之半導體模組複數安裝於安裝板之表裏兩面之模組構造的平面圖。
圖13係圖12所示之模組構造之剖面圖。
1．．．半導體裝置
2．．．電路基板
2a．．．第1主面
2b．．．第2主面
3．．．陸區
4．．．陸區
5．．．外部連接端子
6．．．第1連接墊
7．．．第2連接墊
8．．．第1開口部
9．．．第2開口部
10．．．第1半導體元件
11．．．第1接合材層
12．．．第1電極墊
13．．．第2半導體元件
14．．．第2接合材層
15．．．第2電極墊
16．．．第3電極墊
17．．．第3半導體元件
18．．．第3接合材層
19．．．第4電極墊
20．．．第4半導體元件
21．．．第4接合材層
22．．．第1金屬線
23．．．第2金屬線
24．．．密封樹脂

Claims (20)

  1. 一種半導體裝置，其具備：電路基板，係具備具有第1連接墊之第1主面、及具有第2連接墊且與上述第1主面成相反側之第2主面；第1半導體元件，係具有第1電路形成面及設置於上述第1電路形成面上之第1電極墊，上述第1半導體元件係以使上述第1電路形成面面對上述電路基板之上述第1主面之方式，搭載於上述電路基板之上述第1主面上；第2半導體元件，係具第1電路形成面及設置於上述第1電路形成面上之第2電極墊，上述第2半導體元件係以使上述第2電路形成面面對上述電路基板之上述第2主面之方式，搭載於上述電路基板之上述第2主面上；第1金屬線，係電性連接上述電路基板之上述第1連接墊與上述第2半導體元件之上述第2電極墊；第2金屬線，係電性連接上述電路基板之上述第2連接墊與上述第1半導體元件之上述第1電極墊；及密封部，係將上述第1及第2半導體元件與上述第1及第2金屬線一同密封。
  2. 如請求項1之半導體裝置，其中上述電路基板具有形成於上述第2主面之除由上述密封部之密封區域以外之區域的外部連接端子。
  3. 如請求項1之半導體裝置，其中上述第1連接墊設於上述電路基板之第1外形邊與上述電路基板之上述第1主面之上述第1半導體元件搭載區域之間，上述第2連接墊設於 與上述第1外形邊相對之上述電路基板之第2外形邊與上述電路基板之上述第2主面之上述第2半導體元件搭載區域之間。
  4. 如請求項1之半導體裝置，其係進而具備第3半導體元件，其具有第3電路形成面及設置於上述第3電路形成面上之第3電極墊；上述第3半導體元件係以使上述第3電路形成面面對上述電路基板之上述第1主面之方式，積層於在上述第1電路形成面相反側之上述第1半導體元件之第1背面，且上述第3半導體元件之上述第3電極墊與上述電路基板之上述第2連接墊電性連接。
  5. 如請求項4之半導體裝置，其中上述第2連接墊、上述第1電極墊以及上述第3電極墊藉由上述第2金屬線依次電性連接。
  6. 如請求項1之半導體裝置，其係進而具備第4半導體元件，其具有第4電路形成面及設置於上述第4電路形成面上之第4電極墊；上述第4半導體元件係以使上述第4電路形成面面對上述電路基板之上述第2主面之方式，積層於在上述第2電路形成面相反側之上述第2半導體元件之第2背面，且上述第4半導體元件之上述第4電極墊與上述電路基板之上述第1連接墊電性連接。
  7. 如請求項6之半導體裝置，其中上述第1連接墊、上述第2電極墊以及上述第4電極墊藉由上述第1金屬線依次電性連接。
  8. 如請求項1之半導體裝置，其中上述電路基板具備以貫 通上述電路基板之方式設置於接近上述第1連接墊之位置之第1開口部、及以貫通上述電路基板之方式設置於接近上述第2連接墊之位置之第2開口部；上述第1半導體元件之上述第1電極墊係露出於上述第2開口部內，上述第2半導體元件之上述第2電極墊係露出於上述第1開口部內；上述第1金屬線係經由上述第1開口部而配置，上述第2金屬線係經由上述第2開口部而配置。
  9. 如請求項2之半導體裝置，其中上述電路基板具備配線網，其電性連接上述外部連接端子及上述第1及第2連接墊。
  10. 一種半導體裝置，其具備：電路基板，係具備具有第1連接墊之第1主面、及具有第2連接墊且與上述第1主面成相反側之第2主面；第1元件群，係具備具有第1電路形成面及設置於上述第1電路形成面上之第1電極墊之複數之第1半導體元件，且上述第1半導體元件以使上述第1電路形成面面對上述電路基板之上述第1主面之方式，以階梯狀積層於上述電路基板之上述第1主面上；第2元件群，係具備具有第2電路形成面及設置於上述第2電路形成面上之第2電極墊之複數之第2半導體元件，且上述複數之第2半導體元件以使上述第2電路形成面面對上述電路基板之上述第2主面之方式，以階梯狀積層於上述電路基板之上述第2主面上；第1金屬線，係電性連接上述電路基板之上述第1連接 墊與構成上述第2元件群之上述第2半導體元件之上述第2電極墊；第2金屬線，係電性連接上述電路基板之上述第2連接墊與構成上述第1元件群之上述第1半導體元件之上述第1電極墊；及密封部，係將上述第1及第2元件群與上述第1及第2金屬線一同密封。
  11. 如請求項10之半導體裝置，其中上述電路基板具有形成於上述第2主面之除由上述密封部之密封區域以外之區域的外部連接端子。
  12. 如請求項10之半導體裝置，其中上述密封部係形成為使構成第1及第2元件群之上述複數之半導體元件中分別位於最上層之上述半導體元件之背面露出。
  13. 如請求項10之半導體裝置，其中上述電路基板具備以貫通上述電路基板之方式設置於接近上述第1連接墊之位置之第1開口部、及以貫通上述電路基板之方式設置於接近上述第2連接墊之位置之第2開口部；上述第1半導體元件之上述第1電極墊係露出於上述第2開口部內，上述第2半導體元件之上述第2電極墊係露出於上述第1開口部內；上述第1金屬線係經由上述第1開口部而配置，上述第2金屬線係經由上述第2開口部而配置。
  14. 如請求項11之半導體裝置，其中上述電路基板具備配線網，其電性連接上述外部連接端子及上述第1及第2連接墊。
  15. 一種半導體模組，其特徵為具備：第1及第2裝置，各具備具有以下構件之半導體裝置：電路基板，係具備具有第1連接墊之第1主面、及具有第2連接墊且與上述第1主面成相反側之第2主面；第1半導體元件，係具有第1電路形成面及設置於上述第1電路形成面上之第1電極墊，上述第1半導體元件係以使上述第1電路形成面面對上述電路基板之上述第1主面之方式，搭載於上述電路基板之上述第1主面上；第2半導體元件，係具第1電路形成面及設置於上述第1電路形成面上之第2電極墊，上述第2半導體元件係以使上述第2電路形成面面對上述電路基板之上述第2主面之方式，搭載於上述電路基板之上述第2主面上；第1金屬線，係電性連接上述電路基板之上述第1連接墊與上述第2半導體元件之上述第2電極墊；第2金屬線，係電性連接上述電路基板之上述第2連接墊與上述第1半導體元件之上述第1電極墊；及密封部，係將上述第1及第2半導體元件與上述第1及第2金屬線一同密封；且上述第2裝置係堆疊於上述第1裝置上。
  16. 如請求項15之半導體模組，其中形成上述第1裝置之上述半導體裝置之上述電路基板及形成上述第2裝置之上述半導體裝置之上述電路基板，具有形成於上述第1主面之除由上述密封部之密封區域以外之區域的第1陸區、形成於上述第2主面之除藉由上述密封部之密封區域以外之區域 的第2陸區、及設於上述第2陸區上之外部連接端子，上述第1裝置之上述第1陸區與上述第2裝置之上述外部連接端子電性連接。
  17. 如請求項15之半導體模組，其中上述半導體裝置具備第3半導體元件，其具有第3電路形成面及設置於上述第3電路形成面上之第3電極墊；上述第3半導體元件以使上述第3電路形成面面對上述電路基板之上述第1主面之方式，與上述第1半導體元件積層，且上述第3半導體元件之上述第3電極墊與上述電路基板之上述第2連接墊電性連接。
  18. 如請求項17之半導體模組，其中上述第2連接墊、上述第1電極墊以及上述第3電極墊藉由上述第2金屬線依次電性連接。
  19. 如請求項15之半導體模組，其中上述半導體裝置具備第4半導體元件，其具有第4電路形成面及設置於上述第4電路形成面上之第4電極墊；上述第4半導體元件以使上述第4電路形成面面對上述電路基板之上述第2主面之方式，與上述第2半導體元件積層，且上述第4半導體元件之上述第4電極墊與上述電路基板之上述第1連接墊電性連接。
  20. 如請求項19之半導體模組，其中上述第1連接墊、上述第2電極墊以及上述第4電極墊藉由上述第1金屬線依次電性連接。
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US20080197472A1 (en) 2008-08-21
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