CN101257013B - 半导体装置和采用其的半导体模块 - Google Patents

半导体装置和采用其的半导体模块 Download PDF

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CN101257013B
CN101257013B CN2008100920287A CN200810092028A CN101257013B CN 101257013 B CN101257013 B CN 101257013B CN 2008100920287 A CN2008100920287 A CN 2008100920287A CN 200810092028 A CN200810092028 A CN 200810092028A CN 101257013 B CN101257013 B CN 101257013B
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circuit substrate
semiconductor element
electrode pad
semiconductor
type surface
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CN101257013A (zh
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松岛良二
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Abstract

本发明提供了半导体装置和采用其的半导体模块，半导体装置包括：包括具有第1连接焊盘的第1主表面、具有第2连接焊盘的第2主表面、以贯通第1连接焊盘的附近的方式设置的第1开口部、和以贯通第2连接焊盘的附近的方式设置的第2开口部的电路基板。在电路基板的第1主表面上以面向下的状态装载第1半导体元件。第1电极焊盘在第2开口部内露出，通过第2开口部与第2连接焊盘连接。在电路基板的第2主表面上以面向上的状态装载第2半导体元件。第2电极焊盘在第1开口部内露出，通过第1开口部与第1连接焊盘连接。

Description

半导体装置和采用其的半导体模块
相关申请的交叉参考
本申请以于2007年2月20日申请的日本申请、特愿2007-038862号的优先权权益为基础。从而要求其优先权权益。在此引入所述日本申请的全部内容作为参考文献。
技术领域
本发明涉及半导体装置和采用该半导体装置的半导体模块。
背景技术
为了实现半导体装置的小型化和高密度安装化，在一个封装内层叠多个半导体元件进行密封的叠层型多芯片封装已经实用化了。在叠层型多芯片封装中，在具有外部连接端子的电路基板、引线框架等的电路基材上顺序层叠多个半导体元件。在多个半导体元件和电路基材的连接中适用引线接合时，为了使半导体元件能够与金属引线连接，在面朝上的状态下层叠半导体元件。
在现有的层叠型多芯片封装中，必然要将与最上部的半导体元件连接的金属引线配置为通过超过多个半导体元件的层叠厚度的部分。用树脂密封具有这样的叠层结构和引线布线形状的多个半导体元件时，需要使密封树脂的厚度仅按引线布线向最上部的半导体元件的形状的量加厚。这样，在现有的叠层型多芯片封装中，引线布线对于最上部的半导体元件的形状成为使封装厚度加厚的原因。
在特开2001-036000号公报中，记载了配置2个半导体元件以使各自的焊盘形成面彼此相对的半导体封装。但是，其中在半导体元件的接合焊盘形成面上形成绝缘层，还在绝缘层的表面上形成金属布线，用焊料球在这些金属布线之间连接。因此，不能使半导体封装本身的厚度足够薄。而且，安装板和半导体封装的连接通过在2个半导体元件之间的间隙中配置接合引线来实施。这一点也使半导体封装的厚度有变厚的倾向。
发明内容
根据本发明的一个方面的半导体装置包括：电路基板，其包括具有第1连接焊盘的第1主表面、具有第2连接焊盘并在所述第1主表面相反侧的第2主表面、以贯通所述第1连接焊盘的附近的方式设置的第1开口部、和以贯通所述第2连接焊盘的附近的方式设置的第2开口部；第1半导体元件，其装载在所述电路基板的所述第1主表面上，具有在所述第2开口部内露出的第1电极焊盘；第2半导体元件，其装载在所述电路基板的所述第2主表面上，具有在所述第1开口部内露出的第2电极焊盘；第1连接部件，其以电连接所述第1连接焊盘和所述第2电极焊盘的方式，通过所述第1开口部配置；第2连接部件，其以电连接所述第2连接焊盘和所述第1电极焊盘的方式，通过所述第2开口部配置；以及密封部，其与所述第1及第2连接部件和所述电路基板的一部分一起密封所述第1和第2半导体元件。
根据本发明的另一方面的半导体装置包括：电路基板，其包括具有第1连接焊盘的第1主表面、具有第2连接焊盘并在所述第1主表面相反侧的第2主表面、以贯通所述第1连接焊盘的附近的方式设置的第1开口部、和以贯通所述第2连接焊盘的附近的方式设置的第2开口部；第1元件组，其包括具有电极焊盘的多个半导体元件，所述多个半导体元件以所述电极焊盘在所述第2开口部内露出的方式，阶梯状地层叠在所述电路基板的所述第1主表面上；第2元件组，其包括具有电极焊盘的多个半导体元件，所述多个半导体元件以所述电极焊盘在所述第1开口部内露出的方式，阶梯状地层叠在所述电路基板的所述第2主表面上；第1连接部件，其以电连接所述第1连接焊盘和构成所述第2元件组的所述多个半导体元件的所述电极焊盘的方式，通过所述第1开口部配置；第2连接部件，其以电连接所述第2连接焊盘和构成所述第1元件组的所述多个半导体元件的所述电极焊盘的方式，通过所述第2开口部配置；以及密封部，其与所述第1及第2连接部件和所述电路基板的一部分一起密封所述第1和第2元件组。
根据本发明的另一个方面的半导体模块包括多个根据本发明的一个方面的半导体装置，层叠所述多个半导体装置。
附图说明
图1是示出根据实施方式的半导体装置的结构的剖面图。
图2是图1中示出的半导体装置的平面图。
图3是图1中示出的半导体装置的背面图。
图4是示出在半导体装置的制造工序中采用的基板面板的平面图。
图5A到图5C是放大示出在半导体装置的制造工序中在电路基板的第1主表面上装载半导体元件的阶段的图。
图6A到图6C是放大示出在半导体装置的制造工序中在电路基板的第2主表面上装载半导体元件的阶段的图。
图7A和图7B是放大示出在半导体装置的制造工序中引线接合阶段的图。
图8是示出在半导体装置的制造工序中在基板面板的装置形成区域中安装半导体元件的状态的平面图。
图9是示出在半导体装置的制造工序中对基板面板的装置形成区域进行树脂密封的状态的平面图。
图10是示出在半导体装置的制造工序中在基板面板的装置形成区域中形成外部连接端子的状态的平面图。
图11是示出根据实施方式的半导体模块的剖面图。
图12是示出在安装板的表面和背面两面上多联安装了图11中示出的半导体模块的模块结构的平面图。
图13是图12中示出的模块结构的剖面图。
具体实施方式
下面，参照附图说明实施本发明的方式。图1、图2和图3是示出根据本发明实施方式的半导体装置结构的图。图1是其剖面图、图2是平面图，图3是背面图。在这些图中示出的半导体装置1包括可以两面安装的电路基板2。电路基板2是在例如树脂基板、陶瓷基板、玻璃基板等的绝缘基板、半导体基板等的内部、表面等上设置了布线网(未图示)的电路基板。作为电路基板2的代表例，可列举使用了玻璃环氧树脂、BT树脂(马来酰亚胺·三嗪树脂)等的印刷布线基板。
电路基板2包括作为第1元件装载面的第1主表面(A面)2a、在第1主表面2a相反侧的作为第2元件装载面的第2主表面(B表面)2b。第1主表面2a的中央部附近是元件装载区域。同样地，第2主表面2b的中央部附近是元件装载区域。这样，电路基板2的表面和背面两面都可以装载半导体元件，具有与半导体元件的两面安装相对应的布线网。
而且，在电路基板2的第1和第2主表面2a、2b上分别设置外部连接用连接盘(land)3、4。这些连接盘3、4形成在除了通过后述的密封部进行密封的区域之外的外侧区域上。分别沿电路基板2相对的两边(外形边)设置。在第2主表面2b一侧的连接盘4上设置焊料凸起等外部连接端子5。此外，多级层叠半导体装置1而没有模块化时，也可以不需要第1主表面2a一侧的连接盘3。
在电路基板2的第1主表面2a上设置至少一部分通过布线网与连接盘3、4电连接的第1连接焊盘6。第1连接焊盘6设置在第1主表面2a的元件装载区域与电路基板2相对的两个外形边中的一个边(第1外形边)之间。基本成直线状地排列第1连接焊盘6，以使其与电路基板2的第1外形边平行。第1连接焊盘6如后所述，在对第2半导体元件等进行引线接合时起连接部的作用。
在电路基板2的第2主表面2b上设置至少一部分通过布线网与连接盘3、4电连接的第2连接焊盘7。第2连接焊盘7设置在第2主表面2b的元件装载区域与电路基板2相对的两个外形边中的另一个边(第2外形边)之间。基本成直线状地排列第2连接焊盘7，以使其与电路基板2的第2外形边平行。第2连接焊盘7如后所述，在对第1半导体元件等进行引线接合时起连接部的作用。
电路基板2具有贯通第1连接焊盘6附近的第1开口部8和贯通第2连接焊盘7附近的第2开口部9。第1开口部8设置在电路基板2的第1外形边与第1连接焊盘6的形成区域之间，具有沿第1连接焊盘6的排列方向的长形。第2开口部9设置在电路基板2的第2外形边与第2连接焊盘7的形成区域之间，具有沿第2连接焊盘7的排列方向的长形。这些开口部8、9如后所述，作为电连接电路基板2和半导体元件的连接部件的设置区域。
在电路基板2的第1主表面2a上通过第1粘结材料层11粘结第1半导体元件10。第1半导体元件10具有设置在与含晶体管的集成电路的形成面相同面上的第1电极焊盘12。第1电极焊盘12沿第1半导体元件10的一边基本成一列排列。即，第1半导体元件10具有单侧焊盘结构。而且，第1半导体元件10，以具有第1电极焊盘12的电极形成面与第1主表面(上表面)2a相对的方式，以面向下的状态装载在电路基板2的第1主表面2a上。
将第1半导体元件10设置为沿第1电极焊盘12的形成区域的边(焊盘排列边)在第2开口部9一侧。而且，将第1半导体元件10设置为第1电极焊盘12在第2开口部9内露出。由此，防止相对于第1主表面(上表面)2a以面向下状态设置的第1半导体元件10的电极焊盘12被电路基板2所覆盖。在第2开口部9内露出的第1电极焊盘12使第1半导体元件10的电极形成面与第1主表面(上表面)2a相对之后，可以进行引线接合等。
在电路基板2的第2主表面2b上通过第2粘结材料层14粘结第2半导体元件13。第2半导体元件13具有设置在与含晶体管的集成电路的形成面相同面上的第2电极焊盘15。第2电极焊盘15沿第2半导体元件13的一边基本成一列排列。第2半导体元件13与第1半导体元件10同样也具有单侧焊盘结构。而且，第2半导体元件13，以具有第2电极焊盘15的电极形成面与第2主表面(上表面)2b相对的方式，以面向上的状态装载在电路基板2的第2主表面2b上。
将第2半导体元件13设置为沿第2电极焊盘15的形成区域的边(焊盘排列边)在第1开口部8一侧。而且，将第2半导体元件13设置为第2电极焊盘15在第1开口部8内露出。由此，防止相对于第2主表面(下表面)2b以面向上状态设置的第2半导体元件13的电极焊盘15被电路基板2所覆盖。在第1开口部8内露出的第2电极焊盘15使第2半导体元件13的电极形成面与第2主表面(下表面)2b相对之后，可以进行引线接合等。
这样，将第1半导体元件10和第2半导体元件13设置为各自的电极形成面通过电路基板2相对，并且各自的焊盘排列边的设置成相反的方向(相对于电路基板2的表面方向相反侧)。而且，使第1电极焊盘12在第2开口部9内露出，并且使第2电极焊盘15在第2开口部9相反侧的第1开口部8内露出。由此，不用使密封厚度增加到通过电路基板2层叠的第1和第2半导体元件10、13的厚度以上，就可以连接电极焊盘12、15和电路基板2。
而且，在第1半导体元件10上通过第3粘结材料层18粘结具有单侧排列结构的第3电极焊盘16的第3半导体元件17。第3半导体元件17，以其电极形成面与第1半导体元件10的电极形成面相反侧的面(背面(图中是上面))相对的方式，以面向下的状态在第1半导体元件10上层叠。这些半导体元件10、17，以电极焊盘12、16彼此接近的方式，方向一致地层叠。第3半导体元件17，以第3电极焊盘16露出的方式，与第1半导体元件10中心位置错开阶梯状地层叠。第3电极焊盘16与第1电极焊盘12相同，在第2开口部9内露出。
第1半导体元件10和第3半导体元件17构成装载在电路基板2的第1主表面2a上的第1元件组。构成第1元件组的半导体元件的数量不限于2个，也可以是3个或3个以上。第1元件组由多个半导体元件构成。但是，装载在电路基板2的第1主表面2a上的半导体元件的数量可以是1个。图1中示出的半导体装置1可以具有在电路基板2的第1主表面2a上仅装载第1半导体元件10的结构。
在第2半导体元件13上(立体看，在下侧)通过第4粘结材料层21粘结具有单侧排列结构的第4电极焊盘19的第4半导体元件20。第4半导体元件20，以其电极形成面与第2半导体元件13的电极形成面相反侧的面(背面(图中是下面))相对的方式，以面向上的状态在第2半导体元件13上层叠。这些半导体元件13、20，以电极焊盘15、19彼此接近的方式，方向一致地层叠。第4半导体元件20，以第4电极焊盘19露出的方式，与第2半导体元件13中心位置错开阶梯状地层叠。第4电极焊盘19与第2电极焊盘15相同，在第1开口部8内露出。
第2半导体元件13和第4半导体元件20构成装载在电路基板2的第2主表面2b上的第2元件组。构成第2元件组的半导体元件的数量不限于2个，也可以是3个或3个以上。第2元件组由多个半导体元件构成。但是，装载在电路基板2的第2主表面2b上的半导体元件的数量可以是1个。图1中示出的半导体装置1可以具有在电路基板2的第2主表面2b上仅装载第2半导体元件13的结构。
在第1半导体元件10上层叠第3半导体元件17的3层叠层结构、还在第2半导体元件13上层叠第4半导体元件20的4层叠层结构中，密封层厚度与通过电路基板2层叠的多个半导体元件(第1到第3半导体元件10、13、17，或者第1到第4半导体元件10、13、17、20)的厚度相同。而且，能够连接多个半导体元件的电极焊盘和电路基板2。对于第1到第4半导体元件10、13、17、20，例如适用如NAND型闪存的存储器元件，但是不限于此。
第1开口部8提供在电路基板2的第1主表面2a上设置的第1连接焊盘6与第2和第4半导体元件13、20的电极焊盘15、19的连接空间。在第1开口部8中设置第1连接部件。第1连接焊盘6与第2半导体元件13的电极焊盘15通过经由第1开口部8设置的第1金属引线(Au引线等)22电连接。第2电极焊盘15，通过利用第1开口部8，与在装载有第2半导体元件13的电路基板2的第2主表面2b相反侧的第1主表面2a上设置的第1连接焊盘6通过第1金属引线22电连接。
第4半导体元件20的电极焊盘19也通过经由第1开口部8设置的第1金属引线22与第1连接焊盘6电连接。在第2电极焊盘15和第4电极焊盘19的电特性、信号特性等相等的情形下，可以通过第1金属引线22顺序连接第4电极焊盘19、第2电极焊盘15和第1连接焊盘6。该情形下的金属引线22可以通过分别实施引线接合工序进行连接，也可以通过1根金属引线22顺序连接第4电极焊盘19、第2电极焊盘15和第1连接焊盘6。
第2开口部9提供在电路基板2的第2主表面2b上设置的第2连接焊盘7与第1和第3半导体元件10、17的电极焊盘12、16的连接空间。在第2开口部9中设置第2连接部件。第2连接焊盘7与第1半导体元件10的电极焊盘12通过经由第2开口部9设置的第2金属引线(Au引线等)23电连接。第1电极焊盘12，通过利用第2开口部9，与在装载有第1半导体元件10的电路基板2的第1主表面2a相反侧的第2主表面2b上设置的第2连接焊盘7通过第2金属引线23电连接。
第3半导体元件17的电极焊盘16也通过经由第2开口部9设置的第2金属引线23与第2连接焊盘7电连接。在第1电极焊盘12和第3电极焊盘16的电特性、信号特性等相等的情形下，可以通过第2金属引线23顺序连接第3电极焊盘16、第1电极焊盘12和第2连接焊盘7。该情形下的金属引线23可以通过分别实施引线接合工序进行连接，也可以通过1根金属引线23顺序连接第3电极焊盘16、第1电极焊盘12和第2连接焊盘7。
图1和图2中示出的半导体装置1具有作为电连接电路基板2的连接焊盘6、7和半导体元件10、13、17、20的电极焊盘12、15、16、19的连接部的金属引线(接合引线)22、23。连接部件不限于金属引线。连接部件也可以是金属布线层等。即，连接焊盘6、7和电极焊盘12、15、16、19的电连接不限于引线接合，可以适用采用金属布线层的连接结构等。
第1到第4半导体元件10、13、17、20与第1和第2金属引线22、23、电路基板2等的一部分共同由环氧树脂等的密封树脂24密封。密封树脂24，以连接盘3、4、外部连接端子5等露出的方式，在除了电路基板2的端子形成区域之外的区域上形成。由此构成半导体装置1。将密封树脂24形成为在电路基板2的第1主表面2a一侧露出第3半导体元件17的背面，在第2主表面2b一侧露出第4半导体元件20的背面。第3和第4半导体元件13、20的背面也不必必须露出，也可以由密封树脂24覆盖。
如上所述，因为第1和第2金属引线22、23分别设置在开口部8、9内，所以能够使密封树脂24的厚度与通过电路基板2层叠的半导体元件10、13、17、20的厚度相同。从而，在通过引线接合等电连接层叠的半导体元件10、13、17、20和电路基板2之后，能够使密封树脂24的厚度减薄。通过使第3和第4半导体元件13、20的背面(构成第1和第2元件组的半导体元件中，分别位于最上级的半导体元件的背面)露出，使密封树脂24的厚度成为最小。
因为密封树脂24的厚度不受引线形状的影响，因此可以根据电路基板2的厚度和多个半导体元件的厚度的总厚度设定。从而，可以实现包括多个半导体元件10、13、17、20的半导体装置1的小型·薄型化。在由密封树脂24覆盖第3和第4半导体元件13、20的背面的情形下，因为可以将密封树脂24的厚度设定在可以覆盖第3和第4半导体元件13、20的范围内，因此能够抑制密封树脂24的厚度的增加。从而，可以实现半导体装置1的薄型化。
本实施方式的半导体装置1例如如下所述来制作。参照图4到图10说明半导体装置1的制作工序。首先，如图4所示，准备具有连接盘3(4)以及第1和第2开口部8、9的电路基板2。其中，电路基板2，在半导体装置1的制作工序中，作为具有多个装置形成区域的基板面板(电路基板面板)31提供。图4示出了电路基板2的第1主表面2a。
基板面板31具有多个与1个电路基板2(和采用其的半导体装置1)相当的装置形成区域32。其中，采用在纵向上连接多个三联结构的装置形成区域32的基板面板31。虽然在图4中省略了图示，但是在电路基板2的表面和背面两面上分别形成连接焊盘6、7。
接下来，如图5和图6所示，进行半导体元件的安装工序和连接工序。图5和图6放大示出了基板面板31中的1个电路基板2(装置形成区域32)。根据这些图说明半导体元件的装载工序和连接工序。此外，实际的工序是对于基板面板31的多个电路基板2(装置形成区域32)顺序进行半导体元件的安装工序和连接工序。
首先，如图5A所示，在电路基板2(装置形成区域32)的第1主表面2a的中央附近形成粘结材料层11。接下来，如图5B所示，在电路基板2的第1主表面2a上通过粘结材料层11装载第1半导体元件10。接下来，如图5C所示，在第1半导体元件10上层叠第3半导体元件17。第1和第3半导体元件10、17的方向一致，中心位置错开阶梯状地层叠。而且，将第1和第3半导体元件10、17设置为覆盖第2开口部9。
接下来，如图6A所示，在电路基板2(装置形成区域32)的第2主表面2b的中央附近形成粘结材料层14。接下来，如图6B所示，在电路基板2的第2主表面2b上通过粘结材料层14装载第2半导体元件13。接下来，如图6C所示，在第2半导体元件13上层叠第4半导体元件20。第2和第4半导体元件13、20的方向一致，中心位置错开阶梯状地层叠。而且，将第2和第4半导体元件13、20设置为覆盖第1开口部8。
接下来，如图7A所示，对在电路基板2的第2主表面2b上装载的第2和第4半导体元件13、20，从电路基板2的第1主表面2a一侧通过第1开口部8进行引线接合工序。即，通过包括Au引线等的第1金属引线(接合引线)22电连接在电路基板2的第1主表面2a上设置的第1连接焊盘6和在电路基板2的第2主表面2b上装载的第2和第4半导体元件13、20的电极焊盘15、19。
接下来，如图7B所示，倒置电路基板2，对在第1主表面2a上装载的第1和第3半导体元件10、17，从电路基板2的第2主表面2b一侧通过第2开口部9进行引线接合工序。即，通过包括Au引线等的第2金属引线(接合引线)23电连接在电路基板2的第2主表面2b上设置的第2连接焊盘7和在电路基板2的第1主表面2a上装载的第1和第3半导体元件10、17的电极焊盘12、16。
在图8中示出通过进行图5A到图5C、图6A到图6C和图7A到图7B中示出的各工序，在基板面板31的装置形成区域32(电路基板2)上分别装载多个半导体元件(10、13、17、20)的状态。在图8中，分别通过金属引线(22、23)电连接在各装置形成区域32上装载的半导体元件(10、13、17、20)和电路基板2。
接下来，如图9所示，以将电路基板2的表面和背里两面2a、2b包括起来进行树脂模制的方式，例如注射模制密封树脂24。其中，将三联结构的装置形成区域32的表面和背面两面包括起来进行注射模制。从半导体装置1的厚度的观点出发，优选将密封树脂24形成为使最外层的半导体元件17、20的背面露出。但是，在提高半导体装置1的可靠性方面，用密封树脂24覆盖最外层的半导体元件17、20的背面也是有效的。
然后，如图10所示，在电路基板2的第2主表面(背面)2b一侧设置的连接盘4上接合作为外部连接端子5的焊料球。然后，沿着各装置形成区域32切断进行了半导体元件10、13、17、20的装载工序、用金属引线22、23进行连接的工序、用密封树脂24进行密封的工序、外部连接端子5的形成工序的基板面板31，制作单个化的半导体装置1。
上述实施方式的半导体装置1能够直接作为半导体封装使用。该情形下，电路基板2的厚度为100μm，各半导体元件10、13、17、20的厚度为60μm，各粘结材料层11、14、18、21的厚度为10μm时，密封树脂24的厚度可以为与各构成要素的叠层厚度相当的380μm。即使考虑外部连接端子5的装配高度(例如320μm)，半导体装置1的总高度也可以为例如500μm左右。
半导体装置1除了单个地作为半导体封装使用外，还可以进行多级层叠作为半导体模块使用。图11示出了层叠多个半导体装置1的结构(POP结构)的半导体模块41。图11示出了层叠4个半导体装置1的状态。通过顺序连接在电路基板2的第1主表面2a一侧设置的连接盘3和在第2主表面2b一侧形成的外部连接端子5来进行多个半导体装置1之间的电连接。即，顺序连接位于下级侧的半导体装置1的连接盘3和位于上级侧的半导体装置1的外部连接端子5。
图12和图13示出了在安装板42的表面和背面两面上分别以4联状态安装4级结构的半导体模块41的半导体模块43。即，在安装板42的表面上安装4个4级层叠半导体装置1构成的半导体模块41。在安装板42的背面上也安装4个同样的半导体模块41。从而在安装板42上安装8个半导体模块41，半导体装置1的总数为32个。这样，半导体模块可以具有多级·多联安装半导体装置1的结构。
半导体模块41、43可以基于半导体装置1的薄型化、连接高度的降低等而薄型化。在图11中示出的半导体模块41中，在层叠4级密封树脂24的厚度为380μm、总高度为500μm的半导体装置1时，其高度(模块高度)可以为1.7mm左右。半导体模块41、43不限于层叠多个装载有NAND型闪存的半导体装置1。在半导体模块中可以适用层叠装载有逻辑元件的半导体装置和装载有NAND型闪存的半导体装置的结构、进一步层叠装载有DRAM的半导体装置的结构等各种方式。
此外，本发明不限于上述实施方式，可以适用于在电路基板的两面上分别装载半导体元件，并且连接电路基板和半导体元件的各种结构的半导体装置。这样的半导体装置也包含在本发明中。本发明的实施方式可以在本发明的技术思想的范围内扩展或者变更，该扩展、变更的实施方式也包含在本发明的技术的范围内。

Claims (17)

1.一种半导体装置，包括：
电路基板，其包括具有第1连接焊盘的第1主表面、具有第2连接焊盘并在所述第1主表面相反侧的第2主表面、以贯通所述第1连接焊盘的附近的方式设置的第1开口部、和以贯通所述第2连接焊盘的附近的方式设置的第2开口部；
第1半导体元件，其具有第1电路形成面和在所述第2开口部内露出并在所述第1电路形成面上设置的第1电极焊盘，并以所述第1电路形成面与所述电路基板的所述第1主表面相面对的方式装载在所述电路基板的所述第1主表面上；
第2半导体元件，其具有第2电路形成面和在所述第1开口部内露出并在所述第2电路形成面上设置的第2电极焊盘，并以所述第2电路形成面与所述电路基板的所述第2主表面相面对的方式装载在所述电路基板的所述第2主表面上；
第1金属引线，其以电连接所述电路基板的所述第1连接焊盘和所述第2半导体元件的所述第2电极焊盘的方式，通过所述第1开口部配置；
第2金属引线，其以电连接所述电路基板的所述第2连接焊盘和所述第1半导体元件的所述第1电极焊盘的方式，通过所述第2开口部配置；以及
密封部，其与所述第1及第2金属引线和所述电路基板的一部分一起密封所述第1和第2半导体元件。
2.根据权利要求1的半导体装置，其中：
所述电路基板具有在除了由所述第2主表面的所述密封部密封的区域之外的区域形成的外部连接端子。
3.根据权利要求1的半导体装置，其中：
所述第1连接焊盘设置在所述电路基板的第1外形边与所述电路基板的所述第1主表面上的所述第1半导体元件的装载区域之间，所述第2连接焊盘设置在与所述第1外形边相对的所述电路基板的第2外形边与所述电路基板的所述第2主表面上的所述第2半导体元件的装载区域之间。
4.根据权利要求3的半导体装置，其中：
所述第1开口部设置在所述电路基板的所述第1外形边与所述第1连接焊盘之间，所述第2开口部设置在所述电路基板的所述第2外形边与所述第2连接焊盘之间。
5.根据权利要求1的半导体装置，还包括：
具有第3电路形成面和在所述第3电路形成面上设置的第3电极焊盘的第3半导体元件，所述第3半导体元件以所述第3电极焊盘在所述第2开口部内露出并且所述第3电路形成面与所述电路基板的所述第1主表面相面对的方式在所述第1半导体元件的与所述第1电路形成面相反的第1背面上层叠，并且所述第3半导体元件的所述第3电极焊盘与所述电路基板的所述第2连接焊盘电连接。
6.根据权利要求5的半导体装置，其中：
通过所述第2金属引线顺序电连接所述第2连接焊盘、所述第1电极焊盘和所述第3电极焊盘。
7.根据权利要求1的半导体装置，还包括：
具有第4电路形成面和在所述第4电路形成面上设置的第4电极焊盘的第4半导体元件，所述第4半导体元件以所述第4电极焊盘在所述第1开口部内露出并且所述第4电路形成面与所述电路基板的所述第2主表面相面对的方式在所述第2半导体元件的与所述第2电路形成面相反的第2背面上层叠，并且所述第4半导体元件的所述第4电极焊盘与所述电路基板的所述第1连接焊盘电连接。
8.根据权利要求7的半导体装置，其中：
通过所述第1金属引线顺序电连接所述第1连接焊盘、所述第2电极焊盘和所述第4电极焊盘。
9.一种半导体装置，包括：
电路基板，其包括具有第1连接焊盘的第1主表面、具有第2连接焊盘并在所述第1主表面相反侧的第2主表面、以贯通所述第1连接焊盘的附近的方式设置的第1开口部、和以贯通所述第2连接焊盘的附近的方式设置的第2开口部；
第1元件组，其包括具有第1电路形成面和在所述第1电路形成面上设置的第1电极焊盘的多个第1半导体元件，所述第1半导体元件以所述电极焊盘在所述第2开口部内露出并且所述第1电路形成面与所述电路基板的所述第1主表面相面对的方式，阶梯状地层叠在所述电路基板的所述第1主表面上；
第2元件组，其包括具有第2电路形成面和在所述第2电路形成面上设置的第2电极焊盘的多个第2半导体元件，所述第2半导体元件以所述电极焊盘在所述第1开口部内露出并且所述第2电路形成面与所述电路基板的所述第2主表面相面对的方式，阶梯状地层叠在所述电路基板的所述第2主表面上；
第1金属引线，其以电连接所述电路基板的所述第1连接焊盘和构成所述第2元件组的所述第2半导体元件的所述第2电极焊盘的方式，通过所述第1开口部配置；
第2金属引线，其以电连接所述电路基板的所述第2连接焊盘和构成所述第1元件组的所述第1半导体元件的所述第1电极焊盘的方式，通过所述第2开口部配置；以及
密封部，其与所述第1及第2金属引线和所述电路基板的一部分一起密封所述第1和第2元件组。
10.根据权利要求9的半导体装置，其中：
所述电路基板具有在除了由所述第2主表面的所述密封部密封的区域之外的区域形成的外部连接端子。
11.根据权利要求9的半导体装置，其中：
所述密封部以构成所述第1和第2元件组的所述多个半导体元件中分别位于最上级的所述半导体元件的背面露出的方式形成。
12.一种半导体模块，其特征在于，包括：
包括根据权利要求1的半导体装置的第1装置；以及
包括根据权利要求1的半导体装置并层叠于所述第1装置上的第2装置。
13.根据权利要求12的半导体模块，其中：
构成所述第1装置的所述半导体装置的所述电路基板和构成所述第2装置的所述半导体装置的所述电路基板具有：在除了由所述第1主表面的所述密封部密封的区域之外的区域形成的第1连接盘、在除了由所述第2主表面的所述密封部密封的区域之外的区域形成的第2连接盘、和在所述第2连接盘上设置的外部连接端子；以及
所述第1装置的所述第1连接盘与所述第2装置的所述外部连接端子电连接。
14.根据权利要求12的半导体模块，其中：
所述半导体装置包括具有第3电路形成面和在所述第3电路形成面上设置的第3电极焊盘的第3半导体元件，所述第3半导体元件以所述第3电路形成面与所述电路基板的所述第1主表面相面对的方式与所述第1半导体元件层叠，并且所述第3半导体元件的所述第3电极焊盘与所述电路基板的所述第2连接焊盘电连接。
15.根据权利要求14的半导体模块，其中：
通过所述第2金属引线顺序电连接所述第2连接焊盘、所述第1电极焊盘和所述第3电极焊盘。
16.根据权利要求12的半导体模块，其中：
所述半导体装置包括具有第4电路形成面和在所述第4电路形成面上设置的第4电极焊盘的第4半导体元件，所述第4半导体元件以所述第4电路形成面与所述电路基板的所述第2主表面相面对的方式与所述第2半导体元件层叠，并且所述第4半导体元件的所述第4电极焊盘与所述电路基板的所述第1连接焊盘电连接。
17.根据权利要求16的半导体模块，其中：
通过所述第1金属引线顺序电连接所述第1连接焊盘、所述第2电极焊盘和所述第4电极焊盘。
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