TWI369771B - Leadless integrated circuit package having high density contacts and manufacturing method - Google Patents
Leadless integrated circuit package having high density contacts and manufacturing methodInfo
- Publication number
- TWI369771B TWI369771B TW098119022A TW98119022A TWI369771B TW I369771 B TWI369771 B TW I369771B TW 098119022 A TW098119022 A TW 098119022A TW 98119022 A TW98119022 A TW 98119022A TW I369771 B TWI369771 B TW I369771B
- Authority
- TW
- Taiwan
- Prior art keywords
- manufacturing
- integrated circuit
- high density
- circuit package
- leadless integrated
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (2)
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US15817009P | 2009-03-06 | 2009-03-06 | |
US16654709P | 2009-04-03 | 2009-04-03 |
Publications (2)
Publication Number | Publication Date |
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TW201034151A TW201034151A (en) | 2010-09-16 |
TWI369771B true TWI369771B (en) | 2012-08-01 |
Family
ID=42690331
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW098119022A TWI369771B (en) | 2009-03-06 | 2009-06-08 | Leadless integrated circuit package having high density contacts and manufacturing method |
TW098210112U TWM382576U (en) | 2009-03-06 | 2009-06-08 | Leadless integrated circuit package having high density contacts |
Family Applications After (1)
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TW098210112U TWM382576U (en) | 2009-03-06 | 2009-06-08 | Leadless integrated circuit package having high density contacts |
Country Status (9)
Country | Link |
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US (3) | US8072053B2 (zh) |
EP (1) | EP2248161B1 (zh) |
JP (2) | JP2011517069A (zh) |
KR (1) | KR101088554B1 (zh) |
CN (1) | CN101826501B (zh) |
MY (1) | MY163911A (zh) |
SG (1) | SG172749A1 (zh) |
TW (2) | TWI369771B (zh) |
WO (1) | WO2010099673A1 (zh) |
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2009
- 2009-05-27 MY MYPI20093312A patent/MY163911A/en unknown
- 2009-05-27 JP JP2011502218A patent/JP2011517069A/ja active Pending
- 2009-05-27 KR KR1020097018043A patent/KR101088554B1/ko active IP Right Grant
- 2009-05-27 WO PCT/CN2009/072030 patent/WO2010099673A1/en active Application Filing
- 2009-05-27 EP EP09731470.2A patent/EP2248161B1/en not_active Not-in-force
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- 2009-06-05 CN CN2009101474818A patent/CN101826501B/zh not_active Expired - Fee Related
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- 2009-06-08 TW TW098119022A patent/TWI369771B/zh not_active IP Right Cessation
- 2009-06-08 TW TW098210112U patent/TWM382576U/zh not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
US20100224971A1 (en) | 2010-09-09 |
EP2248161B1 (en) | 2019-05-01 |
KR20100121575A (ko) | 2010-11-18 |
MY163911A (en) | 2017-11-15 |
SG172749A1 (en) | 2011-08-29 |
US8497159B2 (en) | 2013-07-30 |
US9337095B2 (en) | 2016-05-10 |
CN101826501B (zh) | 2011-12-21 |
TW201034151A (en) | 2010-09-16 |
JP2013080957A (ja) | 2013-05-02 |
US20120045870A1 (en) | 2012-02-23 |
JP2011517069A (ja) | 2011-05-26 |
TWM382576U (en) | 2010-06-11 |
JP5524322B2 (ja) | 2014-06-18 |
US20130288432A1 (en) | 2013-10-31 |
EP2248161A4 (en) | 2014-01-01 |
WO2010099673A1 (en) | 2010-09-10 |
CN101826501A (zh) | 2010-09-08 |
EP2248161A1 (en) | 2010-11-10 |
KR101088554B1 (ko) | 2011-12-05 |
US8072053B2 (en) | 2011-12-06 |
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