TWI334226B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI334226B
TWI334226B TW096102441A TW96102441A TWI334226B TW I334226 B TWI334226 B TW I334226B TW 096102441 A TW096102441 A TW 096102441A TW 96102441 A TW96102441 A TW 96102441A TW I334226 B TWI334226 B TW I334226B
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wiring
source
gate
semiconductor layer
layer
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TW096102441A
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TW200729511A (en
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Tomohide Onogi
Yasuo Segawa
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Sony Corp
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136209Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

1334226 九、發明說明: 、【發明所屬之技術領域】 •, 本發明係關於一種半導體裝置’特別是關於一種配置 於顯示裝置之顯示畫素的薄膜電晶體。 【先前技術】 一般而言,在主動矩陣型之液晶顯示装置中,在玻璃 基板等絕緣基板上以矩陣狀配置之複數個顯示晝素,係形 成有晝素選擇用之薄膜電晶體。 第8圖係液晶顯示裝置之顯示晝素之等效電路圖。第 8圖中,係從配置在絕緣基板上之複數個顯示晝素中‘示 其1個。如第8圖所示’從垂直驅動電路DR1供給有晝素 選擇信號之閘極配線GL、與從水平驅動電路DR2供給有 顯示信號之汲極配線DL係相交叉。 在由閘極配線GL與汲極配線DL包圍之區域,配 有畫素選擇用之薄膜電晶體(以下簡稱「薄膜電晶體」)Τί •薄膜電晶體TR之間極係與閘極配線GL連接,並、及極 =極配線DL連接。再者,薄膜電晶體TR之源極係盘 持顯示信號之保持電容以、及做為挾持液晶 極之-者的畫素電極相連接。挾持液晶Μ之 另1個電極係連接於共通電位Vc〇m。 才、 接著,省略圖示說明上述顯示晝素之概 在絕緣基板上之複數個區以亦即 石夕等絕緣膜的緩_/者㈣例如减發或^ 題層。在作為上述薄膜==例如多_層所構成之半s k4膜电晶體之主動層的半導體層中, 318840 5 丄j J寸厶乙ό 成有經添加雜哲& .上 、 、、、、構成之源極及及極。在源極與汲極之間 , 此外,與該半導體層鄰接或分離而形成有構 成上述保持電容之另Η固半導體層。 再者纟緩衝膜上形成有例如由氧化碎膜或氮化石夕膜 成且覆盍半導體層之閘極絕緣膜。在閘極絕緣膜上形 有由鉻或!目所構成且局部地與半導體層相對向之閘極配 ^。作為以層之半導體層上之閘極喊係成為薄膜電晶
合之閘極電極’另丨個半導體層係與閘極絕緣膜及間極配 、’、共同構成保持電容°此外,在閘極絕緣膜上形成有例如 由氧化㈣錢切膜所構叙覆蓋隸配線之層間絕緣 膜。 再者在半導體層之源極及没極上之層間絕緣膜係設 有接觸孔在層間絕緣膜上形成有經由接觸孔分別與源極 及汲極連接之源極配線及汲極配線。 再者,在層間絕緣膜上形成有用以覆蓋源極配線及汲 籲極配線且在源極配線之一部分上具有開口部的平坦化膜。 在平坦化膜上形成有經由該開口部而與源極配線連接之晝 素電極。在晝素電極上形成有第i配向膜。此外,以與畫 素電極相對向之方式,配置有經形成第2配向膜及對向電 極之對向基板。在第1配向膜與第2配向膜之間封入液晶。 在此’對向電極係連接於共通電位vcom。 此外,就關聯之技術而言,可列舉例如以下之專利文 獻。 [專利文獻1]曰本特開2005-117069號公報 318840 6 1334226 基板上形成有金屬層·,金屬層係從接觸孔側延伸,並在閑 極配線之下方且與半導體層重疊之區域形成終端。此外, 本發明之半導體裝置係配置在液晶顯示裝置之顯示晝素, 且使用在帛以選擇該顯示晝素之晝素選擇電晶體。 (發明之效果) *根據本發明之半導體震置(亦即薄膜電晶體),由於係 藉由源極配線、汲極配線或金屬層來遮蔽射入至半導體層 之,,因此可儘量抑制光漏電流之產生。因此可儘量抑^ 釀因薄膜電晶體之光漏電流所造成之顯示品質的降低。 再者,可儘里使上述有關遮光之源極配線、汲極配線 或金屬層之形成區域儘量抑制在較小程度。因此,在將該 半導體裝置配置在顯示裝置之顯示晝素時,可儘量避免因 上述遮光造成之顯示晝素的開口率之降低。由此,可儘量 避免顯示畫素之亮度的降低。 【實施方式】 _ 接著,參照圖式說明本發明實施形態之半導體裝置, 亦即薄膜電晶體。該薄膜電晶體係與配置在第8圖所示之 液晶顯示裝置之顯示晝素的薄膜電晶體TR相同,作為配 置在各顯示晝素之晝素選擇用的薄膜電晶體。此外,薄膜 電晶體以外之構成係與習知例相同。 首先,說明本實施形態之薄膜電晶體的概略構成。第 \圖係本發明實施形態之薄臈電晶體之平面圖。第i圖(入) 係僅顯示用以說明後述之源極配線及汲極配線之佈局所需 要的構成元件。第1圖(B)係顯示與第】圖(八)同一之平面, 8 318840 < S > 丄州4226 =示用㈣日㈣後述之基板㈣行遮光之下部金屬層之 、佈局所需要的構成元件。此外,"圖係沿著第 :線的剖面圖。第2圖中,對於比後述之畫素電極更 上層的構成省略其圖示。 如第1圖(Α)、第}圖⑺)及第2圖 等絕緣基板(以下簡稱「A# u ^在玻璃基板 」 成具有從基板側
、電Βθ體進仃遮光之功能的下部金屬層11。再者,在 j 10上’形成有由例如氧切膜或氮切膜等絕緣膜所 成且覆蓋下部金屬層11之緩衝膜12。 在緩衝膜12 i ’形成具有直線部分^與下部金屬層 局^疊的半導體層13。該半導體層13係例如對非^ 夕曰、仃雷射退火處理而成之多晶梦層。或者,半導體層 L亦可為多晶⑪m卜的半導體層。例如,半導體層η '、°為/、 °卩分或整體由非晶矽層所構成者。在半導體層 13中形成有添加高濃度雜質所構成的源極i3s及汲極 ,、在半導體層13之鄰接源極13S及汲極UD的區域, 形成有添加低濃度雜質所構成的低濃度層A。而且,在半 導體層13之與低濃度層A對向之側的閘極配線15端的下 曲亦开乂成有添加低漢度雜質所構成的低濃度層B。在低 :度層A與低濃度層B之間存在有通道。亦即,該薄膜電 日日體係具有LDD(Lightly D〇ped Drain,輕摻雜汲 二在通=低濃度層A、B之接合部,存在有於薄膜電晶 一之關斷日才不會產生載體的空乏化區域DEP。 318840 9 ⑶4226 再者,在緩衝膜12上,形成有由例如氧化矽膜或氮化 -t :膜所構成且覆蓋半導體層13之閘極絕緣膜14。在閘極 S緣膜14上形成有由鉻或鉬所構成且局部地與半導體層 ·· 13相對向之閘極配線15。在此,半導體層13^之閘極配 線15係成為薄膜電晶體之閘極電極。此外,在閘極絕緣膜 14上形成有由例如氧化矽膜或氮化矽膜所構成且覆蓋閘 極配線15之層間絕緣膜16。 再者,在半導體層13之源極i3S及汲極〗3D上之層 間絕緣膜16設有接觸孔Ch。在層間絕緣膜16上形成有 經由接觸孔CH分別與源極l3S及汲極13D連接之源極配 線17S及汲極配線17D。源極配線17S及汲極配線係 由例如包含銘的金屬所構成,且如後所述乃具有對半導體 層13進行遮光之功能。 再者,在層間絕緣膜16上形成有用以覆蓋源極配線 HS及汲極配線17D且在源極配線17S之一部分上具有未 鲁圖示之開口部的平坦化膜18。在平坦化膜18上形成有經 由該未圖示之開口部而與源極配線丨7S連接之晝素電極 19°此外,雖未圖式,但在其更上層,在畫素電極19上形 成有第1配向膜。此外,以與晝素電極相對向之方式, 配置有形成有第2配向膜及對向電極之對向基板。在第i 配向膜與第2配向膜之間封入液晶。在此,對向電極係連 接於共通電位Vcom。 接著,參照圖式詳細說明上述構成之薄膜電晶體的詳 細構造’亦即源極配線17S及汲極配線17D之佈局。如第 318840 10 1334226 1圖⑷及第2圖所示’’源極配線ns及没極配線咖係在 間極配線15上且與半導體層】3重疊之區域形成終端。亦 ’’ Ρ在將各接觸孔Cfi做為始端時,源極配線17S及汲極 配,線17D係在半導體層13與間極配線15上覆蓋未超越間 極配線15之寬度方向之端p3的區域。 错由上述構成,源極配線〗7S及汲極配線17D係在至 少低;農度層A之形成區域卜具有用以遮蔽從比該低濃度 層A更上層所射入之光的第】遮光功能。藉由該第^遮光 _功能,儘量抑制起因於射人半導體層13之空乏化區域⑽ 之光所造成的光漏電流之產生’而儘量抑制顯示品質之降 低。 上述源極配線17S及汲極配線17D之佈局,係以本發 明之發明者等所進行之以下測定結果為依據。以下,就本 發明之發明者等所進行之以下測定結果,參照其特性圖說 明光漏電流與源極配線m及汲極配線nD之遮光長度的 I關係。 第3圖係顯示本發明實施形態之薄膜電晶體之光漏電 流與遮光長度之關係的特性圖。在此,將產生在薄膜電晶 體之光漏電流設為Ileak。而且,遮光長度係指,在閘極配 線15之寬度方向中,以接近接觸孔CH之端ρι為基點時, 在朝向與該端pi對向之端P3的方向延伸之源極配線17S 或汲極配線17D的距離,並以遮光長度L s表示之。 如第3圖所示,光漏電流係在遮光長度ls為〇 之附近、即超越端P1之附近急遽減少。然而,即使遮光 11 (·夢 318840 1334226 長度L s更加延伸且‘閘極配線15之寬度方向超越與端η _ \對向之端Ρ3,光漏電流亦成為一定狀態或大致一定狀 - ··:態而不會減少。亦即,具有超越閘極絕緣臈之端P3之遮 •光長度Ls的源極配線17S及汲極配線17D之佈局,並不 會對光漏電流Ileak之減低有所助益。因此,在本實施形態 中’將源極配線17S及汲極配線17D設為,以各接觸孔 CH為始端,在半導體層13及閘極配線15上,覆蓋未超 越閘極配線15之寬度方向之端p3的區域者。 鲁 再者如第1圖⑻及第2圖所示,關於下部金屬層 11亦同樣地以第3圖之上述特性圖為依據,而將下部金屬 層11設為,從接觸孔CH延伸,在閘極配線15之下方且 與半導體層13重疊之區域形成終端者。亦即,下部金屬層 11係從各接觸孔CH延伸’在半導體層13及閉極配線b 之下方,覆蓋未超越閘極配線15之寬度方向之端P3的區
• <藉由上述構成,下部金屬層11係在至少低濃度層A /成區域,具有用以遮蔽從比該低濃度層A更下層所射 入之光的第2遮光功能。藉由該第2遮光功能,與具有第 遮光功月b之情形相比’更確實地抑制起因於射入半導體 層13之空乏化區域DEP之光所造成的光漏電流之產生, 而抑制顯示品質之降低。 根據上述構成,藉由實現上述第1及第2遮光功能, 而可獲得如以下說明之開口率相關的效果。以下,為了額 明上述效果,說明配置於液晶顯示裝置之顯示晝素的_ 318840 12 1334226 t 曰 JEdk · 曰曰體之參考例。 " ^ 4圖係參考例之薄膜電晶體之平面圖。第4圖(A) .係僅顯示用以說明後述之源極配線及汲極配線之佈局所需 要的構成7L件。第4圖(B)係顯示與第4圖同一之平面, *’’、員示用以說明對後述之基板側進行遮光之下部金屬声 之佈局所需要的構成元件。而且,第5圖係沿著第4圖(二 =Y々線的剖面圖。第4圖及第5圖中,對於與第i圖及 赢ί 2圖所示者相同之構成元件附上同—元件符號,並省略 #其說明。 / :第4圖(Α)及第5圖所示,該薄膜電晶體係與上述實 施开U同’源極線37s及沒極配線37D係以各接 為始端,在半導體層13及_配線15上,覆蓋超越 問=線15之寬度方向之端P3的區域。因此,會產生顯 不旦f之開口率降低的問題。 再者,如第4圖(B)及第5圖所示,下部金屬層31亦 丨同樣地從各接觸孔CH延伸’在半導體層13 &間極配線 15之下方,覆蓋超越閘極配線15之寬度方向之端p3的區 域。在此構成中’亦會產生顯示晝素之開口率降低的問題。 相對於上述參考例’在本實施形態中,源極配線 及汲極配線nD係在半導體層13及閘極配線15上,覆蓋 未超越閘極配線15之寬度方向之端p3的區域。而且: 部金屬層係在半導體層13及閘極配線15之下方,覆罢未 超越閘極配線丨5之寬度方向之端以的區域。因此:=比 上述參考例保持更大之顯示晝素開口率。換言之,根據本 318840 13 口率降低之情形 。結果,可儘量 示晝素之亮度的 貝如开^態,可達成在不使顯示晝素之開 ‘ a現上述第1及第2遮光功能的效果 抑制起因於顯示晝素之開口率所造成的顯 降低,同時儘量抑制光漏電流的產生。 上述實施形態亦可具有作為本發明之其他實施 =:下構成。第6圖係本發明其他實施形態之薄膜電 線之佑^面圖° f 6圖(A)係僅顯示用以說明後述之汲極配 、门一布局所需要的構成元件。第6圖(B)係顯示與帛6圖㈧ 二:! ’且僅顯示用以說明對後述之基板側進行遮光 Γ 層之佈局所需要的構成元件。而且,第7圖係 W第6圖之Z_Z線的剖面圖。第6圖及第7圖中,對於 〇弟1圖及第2圖所示者相同之構成元件附上同一元件符 ^並4略其說明。此外,該薄膜電晶體之下部金屬層係 與第1圖(B)及第2圖所示之下部金屬層u相同。… 如第、6圖⑷及第7圖所示,汲極配線47D係以各接 觸孔CH為始端,在半導體層13及閉極配線^上 超越閘極配線15之寬度方向之端p3㈣^ ㈣ 配線❿係具有直線狀或大致直線狀的形狀^與半= 層二3之直線部分重疊而延伸,因此與參考例相比較時,可 儘量素之開口率的降低,亦即,即使 :二=起因於顯示畫素之開,造成的顯* 晝素之冗度的降低’同時儘量抑制光漏電流的產生。 再者本發明亦可適用於在上述兩實施形態之半導體 層13中’源極13S成為汲極且汲極⑽成為源極的情形。 14
3J8840 (S 1334226 此時/,源極配線〗7S係形成為沒極配線,汲極配線i7D、 47D係形成為源極配線。 • V a再者,上述兩實施形態之薄膜電晶體係做為配置在液 U不裝置之顯不晝素者’但本發明並不限定於此。亦即, 只要為使用在曝露在光的環境下者,本發明亦可適用在配 置於液晶顯示農置以外的顯示裳置、或顯示裝置以外之裝 置的薄膜電晶體。 【圖式簡單說明】 #帛1圖⑷及⑻係本發明實施形態之薄膜電晶體之平 面圖。 第2圖係沿著第!圖之χ·χ線的剖面圖。 、第3圖係顯示本發明實施形態之薄膜電晶體之光漏電 流與遮光長度之關係的特性圖。 第4圖(Α)及(Β)係參考例之薄膜電晶體之平面圖。 第5圖係沿著第4圖之γ-γ線的剖面圖。 # 第6圖⑷及(Β)係本發明其他實施形態之薄膜電晶體 之平面圖。 第7圖係沿著第6圖之Ζ-Ζ線的剖面圖。 第8圖係液晶顯示裝置之顯示晝素的等效電路圖。 【主要元件符號說明】 10 絕緣基板 11 ' 31下部金屬層 12 緩衝膜 13 半導體層 13S 源極 13D 汲極 14 閘極絕緣膜 15 閘極配線 318840 (S > 15 1334226 16 層間絕緣膜 17S、37S 源極配線 17D、37D、47D 汲極配線 18 平坦化膜 A、B低濃度層 Cs 保持電容 DL 汲極配線 DR2 水平驅動電路
Ileak 光漏電流 鲁Ls 遮光長度 TR 薄膜電晶體 19 晝素電極 CH 接觸孔 DEP 空乏化區域 DR1 垂直驅動電路 GL 閘極配線 LC 液晶 PI 、 P2 、 P3 端 Vcom共通電位
16 318840

Claims (1)

1334226
第·"9^102441號專利申請案 (99年3月9曰) 十、申請專利範圍:“ h 一種半導體裝置,係具備 絕緣基板; 形成在前述絕緣基板上之緩衝膜; 形成在前述緩衝膜上之半導體層; 在前述半導體層添加雜質而構成之源極及沒極; 以鄰接則述半導體層《前述源極&前述沒極之方 =形成’且所添加之雜質的濃度比添加至前述源極及前 述没極的濃度低的低濃度層; 覆孤如述半導體層且形成在前述緩衝膜上之閘極 絕緣膜; 與前述半導體層局部重疊且形成在前述閘極絕緣 膜上之閘極配線; 覆蓋前述閘極配線且形成在前述閘極絕緣臈上之 層間絕緣膜; 形成在前述源極及前述汲極上之前述層間絕緣膜 的接觸孔; 經由别述接觸孔而與前述源極連接且延伸在前述 層間絕緣膜上之源極配線;以及 經由别述接觸孔而與前述沒極連接且延伸在前述 層間絕緣膜上之汲極配線; 其中’前述源極配線或前述汲極配線係在前述閘極 配線上方形成終端; k平面觀之,前述低濃度層係被前述源極配線或前 318840修正版 17 1334226 第96102441號專利申請荦 (99年3月9日; 述汲極配線完全覆蓋。 2.如申請專利範圍第1項之半導體裝置,其中,前述源極 配線或前述汲極配線係在前述閘極配線上且與前述半 導體層童疊之區域形成終端。 3. 如申請專利範圍苐1項或第2項之半導體裝置,其中, 前述汲極配線係與前述半導體層重疊且以直線狀延伸。 4. 如申凊專利知圍第i項或第2項之半導體裝置,其中, 於前述絕緣基板上形成有金屬層; 八 前述金屬層係從前述接觸 ^ ^ ^ 卿孔侧延伸,並在前述閘極 配線之下方且與前述半導體居 ^ ^ 与重友之區域形成終端〇 5. 如申凊專利範圍第i項或 、编 ψ ^ ^ ^ r ^ 項之半導體裝置,其中, a牛v體裝置係配置在液 τ 用在用以還锂—s 曰曰顯不裝置之顯示晝素’且使 用在用以選擇該顯示晝素 讥 ^••畫素選擇電晶體。
318840修正版 18
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