CN104022157A - 一种薄膜晶体管、阵列基板及显示装置 - Google Patents

一种薄膜晶体管、阵列基板及显示装置 Download PDF

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CN104022157A
CN104022157A CN201410225263.2A CN201410225263A CN104022157A CN 104022157 A CN104022157 A CN 104022157A CN 201410225263 A CN201410225263 A CN 201410225263A CN 104022157 A CN104022157 A CN 104022157A
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film transistor
thin
drain electrode
active layer
source electrode
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严允晟
王孝林
姚星
王海燕
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BOE Technology Group Co Ltd
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Priority to PCT/CN2014/088768 priority patent/WO2015180376A1/zh
Priority to US14/437,155 priority patent/US20160247941A1/en
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Abstract

本发明公开了一种薄膜晶体管、阵列基板和显示装置，将薄膜晶体管中源极和漏极之间的间隙处对应的有源层区域设计为弯曲的形状，相对于现有技术中源极和漏极之间的间隙处对应的有源层区域为直线，可以在不增加薄膜晶体管所占面积的情况下，增长源极和漏极之间的间隙处对应的有源层区域的长度，从而改善了关态电流急增的问题。并且，在薄膜晶体管所占面积相同的情况下，增加了源极和漏极之间的间隙处对应的有源层区域的长度，这样可以在保证关态电流的情况下，尽量减小薄膜晶体管所占面积，尤其是在应用于高分辨率显示时，可以保证具有较大的开口率。

Description

一种薄膜晶体管、阵列基板及显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管、阵列基板及显示装置。
背景技术
目前，液晶显示面板(LCD，Liquid Crystal Display)、电致发光(EL，electroluminescence)显示面板以及电子纸等显示装置已为人所熟知。在这些显示装置中具有控制各像素开关的薄膜晶体管(TFT，Thin Film Transistor)，其中TFT按结构的不同可以分为：顶栅型TFT和底栅型TFT。
以底栅型为例，薄膜晶体管如图1所示，由依次设置在衬底基板上的栅极1、有源层3、源极4和漏极5组成；其中，栅极1与有源层3之间设置有栅绝缘层2，源极4和漏极5同层设置且相对而置，源极4和漏极5分别与有源层3电性相连，在源极4和漏极5之上设置有钝化层6，漏极5通过钝化层6中的过孔与像素电极7电性相连。一种阵列基板如图2a和图2b所示，栅极1一般与栅线10电性相连，源极4一般与数据线9电性相连，在栅极1加载栅扫描信号时，在栅极1上方的有源层3会从半导体状态变为导体状态，在源极4和漏极5之间的有源层3内与栅极1正对的区域会形成一条电流通道，通过该电流通道可以将数据线9加载到源极4的数据信号通过漏极5传输到像素电极7上，使像素电极7处于工作状态。
在将现有的薄膜晶体管具体应用于阵列基板时，如图2a和图2b所示，位于源极4与漏极5之间的有源层区域8有两种设计方式：其中一种设计方式如图2a所示，位于源极4与漏极5之间的有源层区域8的延伸方向与栅线10相互平行，这种设计的空间利用率较高，但是在应用于高分辨率显示时，由于每个像素所占面积比较小，且为了避免短路现象需要保证漏极5与数据线9之间的距离大于5.0μm，这就会限制了位于源极4与漏极5之间的有源层区域8的长度；而位于源极4与漏极5之间的有源层区域8的长度与TFT的开态电流(Ion)和关态电流(Ioff)均有关系，位于源极4与漏极5之间的有源层区域8的长度过小，会引起关态电流急增的问题。另外一种设计方式如图2b所示，位于源极4与漏极5之间的有源层区域8的延伸方向与栅线10相互垂直，这种设计虽然可以避免漏极5和数据线9之间的短路问题，但是空间利用率较低，不能保证高分辨率显示时各像素具有较高的开口率。
因此，如何在保证空间利用率的基础上，增加位于源极与漏极之间的有源层区域的长度，从而避免关态电流急增的问题，是本领域技术人员亟需解决的技术问题。
发明内容
本发明实施例提供一种薄膜晶体管、阵列基板及显示装置，用以解决现有技术中存在的薄膜晶体管的源极和漏极之间的有源层区域的长度受限导致的关态电流急增的问题。
本发明实施例提供了一种薄膜晶体管，包括位于衬底基板之上的栅极、有源层、源极和漏极，其中，所述源极和所述漏极相对而置且分别与所述有源层电性相连：
所述源极和所述漏极之间的间隙处对应的有源层区域在所述衬底基板上的正投影的形状为弯曲形状。
本发明实施例提供的上述薄膜晶体管，将源极和漏极之间的间隙处对应的有源层区域设计为弯曲的形状，相对于现有技术中源极和漏极之间的间隙处对应的有源层区域为直线，可以在不增加薄膜晶体管所占面积的情况下，增长源极和漏极之间的间隙处对应的有源层区域的长度，从而改善了关态电流急增的问题。
在一种可能的实施方式中，在本发明实施例提供的上述薄膜晶体管中，所述源极和所述漏极之间的间隙处对应的有源层区域在所述衬底基板上的正投影的形状为折线型或曲线型。
在一种可能的实施方式中，在本发明实施例提供的上述薄膜晶体管中，所述源极和漏极与所述有源层之间具有绝缘层，所述源极和漏极分别与所述有源层通过所述绝缘层中的过孔电性相连；或，
所述源极和漏极直接位于所述有源层的上层，所述源极和漏极直接与所述有源层电性相连。
在一种可能的实施方式中，在本发明实施例提供的上述薄膜晶体管中，所述有源层的材料为半导体氧化物材料。
在一种可能的实施方式中，在本发明实施例提供的上述薄膜晶体管中，所述薄膜晶体管为顶栅型或底栅型。
本发明实施例提供了一种阵列基板，包括本发明实施例提供的上述薄膜晶体管，与所述薄膜晶体管中的栅极电性相连的栅线、与所述薄膜晶体管中的源极电性相连的数据线，以及与所述薄膜晶体管中的漏极电性相连的像素电极。
本发明实施例提供的上述阵列基板中，将薄膜晶体管中源极和漏极之间的间隙处对应的有源层区域设计为弯曲的形状，相对于现有技术中源极和漏极之间的间隙处对应的有源层区域为直线，在薄膜晶体管所占面积相同的情况下，增加了源极和漏极之间的间隙处对应的有源层区域的长度，这样可以在保证关态电流的情况下，尽量减小薄膜晶体管所占面积，尤其是在应用于高分辨率显示时，可以保证具有较大的开口率。
在一种可能的实施方式中，在本发明实施例提供的上述阵列基板中，所述薄膜晶体管中的源极和漏极沿着所述栅线的延伸方向排列。
在一种可能的实施方式中，在本发明实施例提供的上述阵列基板中，所述薄膜晶体管中的漏极与最邻近的数据线之间的间隙大于5.0μm。
在一种可能的实施方式中，在本发明实施例提供的上述阵列基板中，所述薄膜晶体管中的漏极与所述像素电极之间具有钝化层，所述漏极与所述像素电极通过所述钝化层中的过孔电性相连；或，
所述像素电极直接位于所述薄膜晶体管中的漏极的上层，所述漏极直接与所述像素电极电性相连。
本发明实施例提供的一种显示装置，包括本发明实施例提供的上述阵列基板。
附图说明
图1为现有技术中的薄膜晶体管的结构示意图；
图2a和图2b分别为现有技术中的阵列基板的俯视图；
图3为本发明实施例提供的薄膜晶体管的结构示意图；
图4a、图4b和图4c分别为本发明实施例提供的薄膜晶体管的具体结构示意图之一；
图5a、图5b和图5c分别为本发明实施例提供的薄膜晶体管的具体结构示意图之二；
图6a、图6b和图6c分别为本发明实施例提供的阵列基板的具体结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的薄膜晶体管、阵列基板及显示装置的具体实施方式进行详细地说明。
附图中各膜层的厚度和区域的大小形状不反映薄膜晶体管各部件的真实比例，目的只是示意说明本发明内容。
本发明实施例提供的一种薄膜晶体管，如图3所示，包括：位于衬底基板之上的栅极01、有源层02、源极03和漏极04；源极03和漏极04相对而置且分别与有源层02电性相连；
如图4a至图4c所示，源极03和漏极04之间的间隙处对应的有源层区域a在衬底基板上的正投影的形状为弯曲形状，即在衬底基板上的正投影的形状为非直线形状。
在本发明实施例提供的上述薄膜晶体管中，将源极03和漏极04之间的间隙处对应的有源层区域a设计为弯曲的形状，相对于现有技术中源极03和漏极04之间的间隙处对应的有源层区域为直线，可以在不增加薄膜晶体管所占面积的情况下，增长源极03和漏极04之间的间隙处对应的有源层区域a的长度，从而改善了关态电流急增的问题。
进一步地，本发明实施例提供的上述薄膜晶体管在具体实施时，可以将源极03和漏极04之间的间隙处对应的有源层区域a，在衬底基板上的正投影的形状具体设置为折线型或曲线型等形状，在此不作限定。具体地，源极03和漏极04之间的间隙处对应的有源层区域a可以设置为Z字折线形，如图4a和图5a所示；源极03和漏极04之间的间隙处对应的有源层区域a也可以设置为弧线Z字形，如图4b和图5b所示；源极03和漏极04之间的间隙处对应的有源层区域a还可以设置为有夹角的折线型，如图4c和图5c所示。上述图形形状仅是举例说明，不限于此，在具体实施时，可以根据构图工艺的精度设计具体图形，在此不做限定。这样，由于将源极03和漏极04之间的间隙处对应的有源层区域a设计成弯曲的形状，有效地增加了源极03和漏极04之间的间隙处对应的有源层区域a的长度，改善了薄膜晶体管的关态电流急增的问题。
在具体实施时，在本发明实施例提供的薄膜晶体管中，在源极03和漏极04与有源层02之间还可以设置有绝缘层，具体地，源极03和漏极04与有源层02可以通过绝缘层中的过孔电性相连，如图5a至图5c所示；或者，在本发明实施例提供的薄膜晶体管中的源极03和漏极04可以直接位于有源层02的上层，这样源极03和漏极04可以直接与有源层02电性相连，如图4a至图4c所示。这样，在采用上述两种源极03和漏极04与有源层02之间连接方式设计薄膜晶体管时，均将源极03和漏极04之间的间隙处对应的有源层区域a设计成弯曲的形状，相对于现有技术中源极03和漏极04之间的间隙处对应的有源层区域为直线，可以在不增加薄膜晶体管所占面积的情况下，增长源极03和漏极04之间的间隙处对应的有源层区域的长度，从而改善了关态电流急增的问题。
具体地，本发明实施例提供的上述薄膜晶体管中的有源层02可以采用半导体氧化物材料制作，也可以采用非晶硅材料制备，在此不做限定。当薄膜晶体管的有源层02采用半导体氧化物材料制作时，更利于利用构图工艺形成弯曲形状，因此可以通过增长源极03和漏极04之间的间隙处对应的有源层区域的长度的方式，改善关态电流急增的问题。
具体地，本发明实施例提供的上述薄膜晶体管在具体实施时可以采用顶栅型，也可以采用底栅型，在此不作限定。本发明实施例提供的上述薄膜晶体管均是以底栅型薄膜晶体管为例进行说明的，如图3所示，在底栅型TFT中在栅极01和有源层02之间一般还设置有栅绝缘层05。在本发明实施例提供的薄膜晶体管应用于底栅型或顶栅型结构时，均可将源极03和漏极04之间的间隙处对应的有源层区域a设计成弯曲的形状，相对于现有技术中源极03和漏极04之间的间隙处对应的有源层区域为直线，可以在不增加薄膜晶体管所占面积的情况下，增长源极03和漏极04之间的间隙处对应的有源层区域的长度，从而改善了关态电流急增的问题。
基于同一发明构思，本发明实施例还提供了一种阵列基板，由于该阵列基板解决问题的原理与前述薄膜晶体管相似，因此该阵列基板的实施可以参见薄膜晶体管的实施，重复之处不再赘述。
本发明实施例提供的一种阵列基板，如图6a至图6c所示，包括本发明实施例提供的上述薄膜晶体管，与薄膜晶体管中的栅极01电性相连的栅线06、与薄膜晶体管中的源极03电性相连的数据线07，以及与薄膜晶体管中的漏极04电性相连的像素电极08。
本发明实施例提供的上述阵列基板中，将薄膜晶体管中源极03和漏极04之间的间隙处对应的有源层区域a设计为弯曲的形状，相对于现有技术中源极03和漏极04之间的间隙处对应的有源层区域为直线，在薄膜晶体管所占面积相同的情况下，增加了源极和漏极之间的间隙处对应的有源层区域的长度，这样可以在保证关态电流的情况下，尽量减小薄膜晶体管所占面积，尤其是在应用于高分辨率显示时，可以保证具有较大的开口率。
在具体实施时，在本发明实施例提供的上述阵列基板中，如图6a至图6c所示，一般将薄膜晶体管的源极03和漏极04沿着栅线的延伸方向排列，这样的排列方式更有利于提高阵列基板中各像素的空间利用率，尤其是应用于高分辨率显示时，可以保证具有较大的开口率。
进一步地，在将薄膜晶体管的源极03和漏极04沿着栅线的延伸方向排列时，为了避免漏极和邻近的数据线之间的短路问题，一般将薄膜晶体管中的漏极04与最邻近的数据线之间的间隙设计为大于5.0μm，这样，可以有效避免短路的问题。
进一步地，本发明实施例提供的上述阵列基板中，薄膜晶体管中的漏极04与像素电极08之间的连接关系可以采用下述两种方式：第一种，可以在漏极04和像素电极08之间设置钝化层，漏极04与像素电极08通过钝化层中的过孔电性相连；第二种，像素电极08可以直接位于薄膜晶体管中的漏极04的上层，漏极04直接与像素电极08电性相连，如图6a至图6c所示。
采用上述两种连接方式的薄膜晶体管，均可以将源极03和漏极04之间的间隙处对应的有源层区域a设计成弯曲的形状，相对于现有技术中源极03和漏极04之间的间隙处对应的有源层区域为直线，在不增加薄膜晶体管所占面积的情况下，增长了源极03和漏极04之间的间隙处对应的有源层区域的长度，从而改善了关态电流急增的问题。
在具体实施时，本发明实施例提供的上述阵列基板可以应用于液晶显示面板，也可以应用于有机电致发光显示面板，在此不做限定。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述阵列基板，该显示装置可以是显示器、手机、电视、笔记本、一体机等，对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
本发明实施例提供了一种薄膜晶体管、阵列基板和显示装置，将薄膜晶体管中源极和漏极之间的间隙处对应的有源层区域设计为弯曲的形状，相对于现有技术中源极和漏极之间的间隙处对应的有源层区域为直线，可以在不增加薄膜晶体管所占面积的情况下，增长源极和漏极之间的间隙处对应的有源层区域的长度，从而改善了关态电流急增的问题。并且，在薄膜晶体管所占面积相同的情况下，增加了源极和漏极之间的间隙处对应的有源层区域的长度，这样可以在保证关态电流的情况下，尽量减小薄膜晶体管所占面积，尤其是在应用于高分辨率显示时，可以保证具有较大的开口率。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

1.一种薄膜晶体管，包括：位于衬底基板之上的栅极、有源层、源极和漏极，其中，所述源极和所述漏极相对而置且分别与所述有源层电性相连，其特征在于：
所述源极和所述漏极之间的间隙处对应的有源层区域在所述衬底基板上的正投影的形状为弯曲形状。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述源极和所述漏极之间的间隙处对应的有源层区域在所述衬底基板上的正投影的形状为折线型或曲线型。
3.如权利要求1所述的薄膜晶体管，其特征在于，所述源极和漏极所在膜层与所述有源层之间具有绝缘层，所述源极和漏极通过所述绝缘层中的过孔分别与所述有源层电性相连；或，
所述源极和所述漏极所在膜层直接位于所述有源层的上层，所述源极和漏极分别直接与所述有源层电性相连。
4.如权利要求1所述的薄膜晶体管，其特征在于，所述有源层的材料为半导体氧化物材料。
5.如权利要求1-4任一项所述的薄膜晶体管，其特征在于，所述薄膜晶体管为顶栅型或底栅型。
6.一种阵列基板，其特征在于，包括如权利要求1-5任一项所述的薄膜晶体管，与所述薄膜晶体管中的栅极电性相连的栅线、与所述薄膜晶体管中的源极电性相连的数据线，以及与所述薄膜晶体管中的漏极电性相连的像素电极。
7.如权利要求6所述的阵列基板，其特征在于，所述薄膜晶体管中的源极和漏极沿着所述栅线的延伸方向排列。
8.如权利要求7所述的阵列基板，其特征在于，所述薄膜晶体管中的漏极与最邻近的数据线之间的间隙大于5.0μm。
9.如权利要求6-8任一项所述的阵列基板，其特征在于，所述薄膜晶体管中的漏极与所述像素电极之间具有钝化层，所述漏极与所述像素电极通过所述钝化层中的过孔电性相连；或，
所述像素电极直接位于所述薄膜晶体管中的漏极的上层，所述漏极直接与所述像素电极电性相连。
10.一种显示装置，其特征在于，包括如权利要求6-9任一项所述的阵列基板。
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CN106816473B (zh) * 2017-01-16 2020-01-21 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
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CN107577100A (zh) * 2017-10-10 2018-01-12 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN110931514B (zh) * 2019-11-29 2022-04-08 云谷（固安）科技有限公司 阵列基板和显示面板
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CN112420748B (zh) * 2020-11-16 2022-07-12 武汉华星光电技术有限公司 显示面板及显示面板的制备方法
WO2023122875A1 (zh) * 2021-12-27 2023-07-06 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板

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