CN105097898B - 一种薄膜晶体管、阵列基板及显示装置 - Google Patents

一种薄膜晶体管、阵列基板及显示装置 Download PDF

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CN105097898B
CN105097898B CN201510296173.7A CN201510296173A CN105097898B CN 105097898 B CN105097898 B CN 105097898B CN 201510296173 A CN201510296173 A CN 201510296173A CN 105097898 B CN105097898 B CN 105097898B
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王孝林
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BOE Technology Group Co Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

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Abstract

本发明提供一种薄膜晶体管，属于显示技术领域，其可解决现有的栅极和源、漏极间的电容大，易造成闪烁和残像的问题。本发明的薄膜晶体管，包括第一电极、第二电极、有源层和栅极，所述栅极和第一电极具有超出有源层之外并重叠的部分，至少在所述栅极和第一电极的重叠部分间设有导电层，用于减小栅极与第一电极之间的电容。本发明的薄膜晶体管在栅极和第一电极的重叠部分间设置导电层，导电层将栅极和第一电极屏蔽，从而减小栅极与第一电极之间的电容，改善闪烁和残像的问题。本发明的薄膜晶体管适用于各种阵列基板。

Description

一种薄膜晶体管、阵列基板及显示装置
技术领域
本发明属于显示技术领域，具体涉及一种薄膜晶体管、阵列基板及显示装置。
背景技术
氧化物薄膜晶体管(Thin Film Transistor，TFT)与非晶硅TFT均可作为驱动管用于有机发光二极管(Organic Light-Emitting Diode，OLED)面板及高分子发光二极管(polymer light-emitting diode，PLED)面板等显示面板中。氧化物TFT与非晶硅TFT相比，其载流子浓度是非晶硅TFT的很多倍。另外，氧化物TFT可通过磁控溅射的方法制备，因此采用氧化物TFT无需大幅改变现有的显示面板生产线。同时，由于没有离子注入及激光晶化等工艺所需设备的限制，相对于多晶硅技术，氧化物TFT更有利于大面积的显示面板的生产。
如图1所示，现有技术中的TFT制作方法中，利用氧化物半导体材料作为有源层31，而所述氧化物半导体对金属源极11、漏极12的刻蚀液比较敏感，在刻蚀金属层形成源极11、漏极12的过程中，为防止所述有源层31被源极11、漏极12的刻蚀液影响，需要在有源层31上形成刻蚀阻挡层21。
发明人发现现有技术中至少存在如下问题：刻蚀阻挡层21的过孔需要的面积较大，由于工艺的限制，相应的源极11、漏极12必须超出有源层31之外，而为了保证驱动效果，故栅极51也要超出有源层31，由此栅极51与源极11、漏极12超出有源层31并重叠的部分面积大，导致栅极51和源极11、漏极12间的电容大，像素电极71的反馈电压大，易造成闪烁和残像。
发明内容
本发明针对现有的薄膜晶体管的栅极和源、漏极间的电容大，将该薄膜晶体管应用至显示面板易造成显示画面闪烁和残像的问题，提供一种薄膜晶体管、阵列基板及显示装置。
解决本发明技术问题所采用的技术方案是：
一种薄膜晶体管，包括第一电极、第二电极、有源层和栅极，所述栅极和第一电极具有超出有源层之外并重叠的部分，至少在所述栅极和第一电极的重叠部分间设有导电层，用于减小栅极与第一电极之间的电容。
优选的，所述第一电极为漏极。
优选的，所述薄膜晶体管还包括刻蚀阻挡层，栅极位于有源层下方，刻蚀阻挡层位于有源层上方，第一电极和第二电极位于刻蚀阻挡层上方。
优选的，所述导电层设于栅极所在层与有源层所在层之间。
优选的，所述导电层由金属材料构成。
优选的，所述导电层厚度为
优选的，所述导电层连接定电压信号。
优选的，所述导电层至少和位于有源层外的漏极重合。
本发明还提供一种阵列基板，包括上述的任一种薄膜晶体管。
优选的，所述阵列基板设有像素电极，所述导电层至少和位于有源层外的漏极和像素电极重合。
本发明还提供一种显示装置，包括上述的阵列基板。
其中，所述导电层连接电压信号，是指对导电层连接单独的电压信号，不是像素电极的电源即可。
本发明的薄膜晶体管在栅极和第一电极的重叠部分间设置导电层，导电层将栅极和第一电极屏蔽，从而减小栅极与第一电极之间的电容，改善闪烁和残像的问题。本发明的薄膜晶体管适用于各种阵列基板。
附图说明
图1为现有的薄膜晶体管的结构示意图；
图2为本发明的实施例2的薄膜晶体管的结构示意图；
图3为本发明的实施例2的另一种薄膜晶体管的结构示意图；
其中，附图标记为：11、源极；12、漏极；21、刻蚀阻挡层；31、有源层；41、栅极绝缘层；51、栅极；61、导电层；71、像素电极。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
本实施例提供一种薄膜晶体管，包括第一电极、第二电极、有源层和栅极，所述栅极和第一电极具有超出有源层之外并重叠的部分，至少在所述栅极和第一电极的重叠部分间设有导电层，用于减小栅极与第一电极之间的电容。
本实施例的薄膜晶体管在栅极和第一电极的重叠部分间设置导电层，导电层将栅极和第一电极屏蔽，从而减小栅极与第一电极之间的电容，改善闪烁和残像的问题。本发明的薄膜晶体管适用于各种阵列基板。
实施例2：
本实施例提供一种薄膜晶体管，如图2所示，包括第一电极、第二电极、有源层31和栅极51，栅极51和第一电极具有超出有源层31之外并重叠的部分，至少在栅极31和第一电极的重叠部分间设有导电层61，用于减小栅极51与第一电极之间的电容。
优选的，第一电极为漏极12。
也就是说，在栅极51和漏极12的重叠部分间设置导电层61，利用导电层61屏蔽栅极51和漏极12之间的电容，从而减小栅极51与漏极12之间的电容，改善闪烁和残像的问题。
优选的，薄膜晶体管还包括刻蚀阻挡层21，栅极51位于有源层31下方，刻蚀阻挡层21位于有源层31上方，有源层31与栅极51之间设有栅极绝缘层41，源极11、漏极12位于刻蚀阻挡层21上方。
这是因为刻蚀阻挡层21的过孔需要的面积较大，由于工艺的限制，相应的源极11、漏极12必须超出有源层31之外，而为了保证驱动效果，故栅极51也要超出有源层31，栅极51和源极11、漏极12超出有源层31之外并重叠的部分面积大，导致栅极51和源极11、漏极12间的电容大，在栅极与漏极12之间设置导电层减小栅极与漏极12之间的电容，改善闪烁和残像效果明显。
优选的，导电层61设于栅极51所在层与有源层31所在层之间。
优选的，导电层61至少和位于有源层31外的漏极重合。
也就是说，现有工艺中的TFT一般栅极51和漏极12具有超出有源层31之外并重叠的部分，将导电层61的一端夹在栅极51所在层与有源层31所在层之间，导电层61的其余部分处于栅极51和漏极12超出有源层31之外并重叠的部分之间，从而减小栅极51与漏极12之间的电容，改善闪烁和残像的问题。
这是因为，在氧化物TFT中，为了电压保持率，通常需要大的存储电容，为了减轻残像问题，需要小的像素电压△Vp(△Vp为像素电压的变量)，在栅极51和漏极12超出有源层31之外并重叠的部分之间设置导电层61可以遮挡栅极与漏极之间的电场，不会形成介电层的感应电荷，因此不会形成栅极51和漏极12之间的电容，转而形成Cgc和Cst，从而减小像素的△Vp电压，△Vp＝Cgd*(Vgh-Vgl)/(Cgd+Cst+Clc)。
其中，△Vp正比于Cgs，反比于Cst，与栅极51和导电层61之间的电容Cgc无关，因此有效改善闪烁和残像的问题。(Cgd为栅极与漏极之间的电容，Vgh为栅极的高电压，Vgl为栅极的低电压，Cst为存储电容，Clc为液晶电容)。
优选的，导电层61由金属材料构成。
也就是说，可以导电的普通金属材料都可用来做导电层61，例如钼或钼/铝/钼(一层钼一层铝一层钼)，业界常用的做像素电极71的原料也可以做该导电层。
优选的，导电层61厚度为
优选的，导电层61连接定电压信号。
也就是说，给导电层61接任何一个给定的电压信号，避免导电层61自身的电压变化，导电层61即可更好的发挥功效。其中，导电层61连接电压信号，是指对导电层61连接单独的定电压信号(直流信号)，只要不是像素电极71的信号即可，例如可以给导电层接地。
实施例3：
本实施例提供一种阵列基板，其具有实施例2的薄膜晶体管。
优选的，阵列基板设有像素电极71，导电层61至少和位于有源层31外的漏极12和像素电极71重合。
也就是说，如图3所示，导电层61较长，不仅栅极51和漏极12超出有源层31之外并重叠的部分之间设有导电层61，导电层61还延伸到与像素电极71重合。这样导电层61可以与像素电极71形成大的电容。
显然，上述各实施例的具体实施方式还可进行许多变化；例如：导电层的材料，厚度等可以根据不同需要而进行设计和改变。
实施例4：
本实施例提供了一种显示装置，其包括实施例2中的阵列基板。所述显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (7)

1.一种阵列基板，包括薄膜晶体管，所述薄膜晶体管包括第一电极、第二电极、有源层和栅极，所述栅极和第一电极具有超出有源层之外并重叠的部分，其特征在于，至少在所述栅极和第一电极的重叠部分间设有导电层，用于减小栅极与第一电极之间的电容；所述第一电极为漏极；所述阵列基板设有像素电极，所述导电层至少和位于有源层外的漏极和像素电极重合，且所述导电层与所述像素电极形成电容。
2.根据权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管还包括刻蚀阻挡层，栅极位于有源层下方，刻蚀阻挡层位于有源层上方，第一电极和第二电极位于刻蚀阻挡层上方。
3.根据权利要求1所述的阵列基板，其特征在于，所述导电层设于栅极所在层与有源层所在层之间。
4.根据权利要求1所述的阵列基板，其特征在于，所述导电层由金属材料构成。
5.根据权利要求1所述的阵列基板，其特征在于，所述导电层厚度为
6.根据权利要求1所述的薄膜晶体管，其特征在于，所述导电层连接定电压信号。
7.一种显示装置，其特征在于，包括权利要求1-6中任一项所述的阵列基板。
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CN101055384A (zh) * 2006-04-12 2007-10-17 中华映管股份有限公司 像素结构及其液晶显示面板

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