TWI310962B - - Google Patents

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Publication number
TWI310962B
TWI310962B TW093100368A TW93100368A TWI310962B TW I310962 B TWI310962 B TW I310962B TW 093100368 A TW093100368 A TW 093100368A TW 93100368 A TW93100368 A TW 93100368A TW I310962 B TWI310962 B TW I310962B
Authority
TW
Taiwan
Prior art keywords
wafer
oxide film
bonded
thickness
soi
Prior art date
Application number
TW093100368A
Other languages
English (en)
Chinese (zh)
Other versions
TW200416813A (en
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of TW200416813A publication Critical patent/TW200416813A/zh
Application granted granted Critical
Publication of TWI310962B publication Critical patent/TWI310962B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H10P30/209—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
TW093100368A 2003-01-10 2004-01-07 Method of producing SOI wafer and SOI wafer TW200416813A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003004833A JP4407127B2 (ja) 2003-01-10 2003-01-10 Ｓｏｉウエーハの製造方法

Publications (2)

Publication Number Publication Date
TW200416813A TW200416813A (en) 2004-09-01
TWI310962B true TWI310962B (https=) 2009-06-11

Family

ID=32708980

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093100368A TW200416813A (en) 2003-01-10 2004-01-07 Method of producing SOI wafer and SOI wafer

Country Status (5)

Country Link
US (1) US20050118789A1 (https=)
EP (1) EP1583145A4 (https=)
JP (1) JP4407127B2 (https=)
TW (1) TW200416813A (https=)
WO (1) WO2004064145A1 (https=)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1719179B1 (en) * 2004-02-25 2018-10-03 Sony Semiconductor Solutions Corporation Photodetecting device
JP4830290B2 (ja) 2004-11-30 2011-12-07 信越半導体株式会社 直接接合ウェーハの製造方法
JP5183874B2 (ja) * 2004-12-28 2013-04-17 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
KR20080086893A (ko) * 2005-12-27 2008-09-26 신에쓰 가가꾸 고교 가부시끼가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
JP2007243038A (ja) * 2006-03-10 2007-09-20 Sumco Corp 貼り合わせウェーハ及びその製造方法
JP2008016534A (ja) 2006-07-04 2008-01-24 Sumco Corp 貼り合わせウェーハの製造方法
FR2910702B1 (fr) * 2006-12-26 2009-04-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat mixte
JP4820801B2 (ja) * 2006-12-26 2011-11-24 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
WO2008078132A1 (en) * 2006-12-26 2008-07-03 S.O.I.Tec Silicon On Insulator Technologies Method for producing a semiconductor-on-insulator structure
SG144092A1 (en) * 2006-12-26 2008-07-29 Sumco Corp Method of manufacturing bonded wafer
WO2008078133A1 (en) * 2006-12-26 2008-07-03 S.O.I.Tec Silicon On Insulator Technologies Method for producing a semiconductor-on-insulator structure
WO2008096194A1 (en) * 2007-02-08 2008-08-14 S.O.I.Tec Silicon On Insulator Technologies Method of fabrication of highly heat dissipative substrates
EP2128891B1 (en) 2007-02-28 2015-09-02 Shin-Etsu Chemical Co., Ltd. Process for producing laminated substrate
WO2008114099A1 (en) 2007-03-19 2008-09-25 S.O.I.Tec Silicon On Insulator Technologies Patterned thin soi
JP5135935B2 (ja) * 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
US20100193899A1 (en) * 2007-11-23 2010-08-05 S.O.I.Tec Silicon On Insulator Technologies Precise oxide dissolution
JP5466410B2 (ja) * 2008-02-14 2014-04-09 信越化学工業株式会社 Ｓｏｉ基板の表面処理方法
DE112008003726B4 (de) 2008-02-20 2023-09-21 Soitec Oxidation nach Oxidauflösung
JP5263509B2 (ja) 2008-09-19 2013-08-14 信越半導体株式会社 貼り合わせウェーハの製造方法
FR2938119B1 (fr) * 2008-10-30 2011-04-22 Soitec Silicon On Insulator Procede de detachement de couches semi-conductrices a basse temperature
FR2938118B1 (fr) 2008-10-30 2011-04-22 Soitec Silicon On Insulator Procede de fabrication d'un empilement de couches minces semi-conductrices
JP5493345B2 (ja) 2008-12-11 2014-05-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.
FR2964495A1 (fr) * 2010-09-02 2012-03-09 Soitec Silicon On Insulator Procede de fabrication d'une structure seoi multiple comportant une couche isolante ultrafine
FR2972564B1 (fr) 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
JP5802436B2 (ja) 2011-05-30 2015-10-28 信越半導体株式会社 貼り合わせウェーハの製造方法
US8653596B2 (en) * 2012-01-06 2014-02-18 International Business Machines Corporation Integrated circuit including DRAM and SRAM/logic
US8994085B2 (en) 2012-01-06 2015-03-31 International Business Machines Corporation Integrated circuit including DRAM and SRAM/logic
FR2998418B1 (fr) * 2012-11-20 2014-11-21 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur sur isolant
JP5780234B2 (ja) 2012-12-14 2015-09-16 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR3003684B1 (fr) * 2013-03-25 2015-03-27 Soitec Silicon On Insulator Procede de dissolution d'une couche de dioxyde de silicium.
FR3034565B1 (fr) 2015-03-30 2017-03-31 Soitec Silicon On Insulator Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3522482B2 (ja) * 1997-02-24 2004-04-26 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JPH11307472A (ja) * 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP3395661B2 (ja) * 1998-07-07 2003-04-14 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP4273540B2 (ja) * 1998-07-21 2009-06-03 株式会社Ｓｕｍｃｏ 貼り合わせ半導体基板及びその製造方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
FR2797713B1 (fr) * 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
KR100730806B1 (ko) * 1999-10-14 2007-06-20 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼
US6566233B2 (en) * 1999-12-24 2003-05-20 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
JP2003204048A (ja) * 2002-01-09 2003-07-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
KR100511656B1 (ko) * 2002-08-10 2005-09-07 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼
US7129123B2 (en) * 2002-08-27 2006-10-31 Shin-Etsu Handotai Co., Ltd. SOI wafer and a method for producing an SOI wafer
JP2004193515A (ja) * 2002-12-13 2004-07-08 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法
JP2004247610A (ja) * 2003-02-14 2004-09-02 Canon Inc 基板の製造方法
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
FR2855908B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince
US7052978B2 (en) * 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
US7018484B1 (en) * 2005-02-09 2006-03-28 Translucent Inc. Semiconductor-on-insulator silicon wafer and method of formation

Also Published As

Publication number Publication date
JP4407127B2 (ja) 2010-02-03
US20050118789A1 (en) 2005-06-02
TW200416813A (en) 2004-09-01
EP1583145A4 (en) 2008-01-02
EP1583145A1 (en) 2005-10-05
JP2004221198A (ja) 2004-08-05
WO2004064145A1 (ja) 2004-07-29

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