WO2012086122A1 - Soiウェーハの製造方法 - Google Patents
Soiウェーハの製造方法 Download PDFInfo
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- WO2012086122A1 WO2012086122A1 PCT/JP2011/006430 JP2011006430W WO2012086122A1 WO 2012086122 A1 WO2012086122 A1 WO 2012086122A1 JP 2011006430 W JP2011006430 W JP 2011006430W WO 2012086122 A1 WO2012086122 A1 WO 2012086122A1
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 230000002093 peripheral effect Effects 0.000 claims abstract description 47
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- 239000007789 gas Substances 0.000 claims abstract description 23
- 239000012298 atmosphere Substances 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims abstract description 16
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims abstract description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000001257 hydrogen Substances 0.000 claims abstract description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000007864 aqueous solution Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 20
- 238000000926 separation method Methods 0.000 abstract description 5
- 238000010276 construction Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 16
- 238000011109 contamination Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 230000005465 channeling Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000012300 argon atmosphere Substances 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- -1 hydrogen (H + ) ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
Definitions
- the present invention relates to a method for manufacturing an SOI wafer in which an epitaxial layer is formed on an SOI layer of an SOI wafer manufactured by an ion implantation separation method.
- Patent Document 1 is cited as a method for realizing this.
- a thin SOI layer is formed by an ion implantation delamination method that can relatively easily obtain an SOI layer having a film thickness uniformity of ⁇ 0.01 ⁇ m or less, and thereafter, epitaxial growth is performed on the SOI layer. In this method, the SOI layer is increased.
- epitaxial growth is performed after the SOI wafer is immersed in an HF aqueous solution to remove the oxide film on the terrace portion, but the back oxide film for preventing warpage is the base.
- the film thickness of the backside oxide film also decreases, which causes a problem that the warpage of the manufactured SOI wafer increases.
- the method of performing HF spin cleaning as in Patent Document 2 is used. There is a method of performing epitaxial growth after completely removing only the oxide film.
- an oxide film may be formed on the base wafer side when a thick buried oxide film is required or when the above-described warp problem is considered. In many cases, an oxide film is formed only on the bond wafer and bonded to the base wafer.
- an oxide film is not formed on the terrace portion of the SOI wafer immediately after peeling, and the outer peripheral edge of the SOI layer of the manufactured SOI wafer and the outer peripheral edge of the buried oxide film are substantially in the same position (in the radial direction). Position). Therefore, when the oxide film is formed only on the bond wafer, the etching of the oxide film in the terrace portion is not performed as in the case where the oxide film is formed on the base wafer.
- FIG. 7 shows a schematic cross-sectional view of the boundary portion between the SOI layer and the terrace when epitaxial growth is performed with the above structure.
- a new problem that the step 25 (hereinafter referred to as “Epi Valley”) occurs is revealed.
- the epitaxial layer 20 grown from the SOI layer 21 and the epitaxial layer 24 from the terrace portion 23 come into contact with each other, and this portion becomes a dust generation source and causes particle contamination in a later process.
- the present invention has been made in view of the above problems, and performs epitaxial growth on an SOI wafer without a silicon oxide film on a terrace portion produced by an ion implantation separation method without generating the above-mentioned epi valley, It is an object to provide a method capable of manufacturing an SOI wafer having a desired SOI layer thickness.
- a silicon oxide film is formed on the surface of a bond wafer made of a silicon single crystal, and at least one gas ion of hydrogen and a rare gas is ion-implanted through the silicon oxide film.
- an SOI wafer having no oxide film on the outer peripheral terrace portion of the base wafer and using the silicon oxide film as a buried oxide film is manufactured, and the outer peripheral edge of the SOI layer of the SOI wafer
- the outer periphery of the buried oxide film has a structure located outside the outer peripheral edge of the buried oxide film.
- An SOI layer is formed on the surface of the SOI layer after the SOI wafer is subjected to a heat treatment in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas.
- a silicon oxide film is formed on the surface of a bond wafer made of a silicon single crystal, and at least one gas ion of hydrogen and a rare gas is ion-implanted through the silicon oxide film to thereby generate an inside of the bond wafer.
- An ion-implanted layer is formed on the surface of the bond wafer, and the surface of the base wafer made of silicon single crystal is bonded to the surface of the base wafer made of silicon single crystal through the silicon oxide film.
- the embedded portion exposed on the outer periphery of the SOI layer of the SOI wafer Performs a process of removing the oxide film, then, provides a method for manufacturing an SOI wafer, comprising forming an epitaxial layer on a surface of the SOI layer.
- the epitaxial layer can be satisfactorily formed on the SOI layer. Therefore, it is possible to manufacture a high-quality thick film SOI wafer that prevents the occurrence of an epi valley and does not cause particle contamination in a subsequent process.
- the treatment for removing the buried oxide film exposed on the outer periphery of the SOI layer is preferably performed by immersing the SOI wafer in an HF-containing aqueous solution. By performing in this way, the exposed outer peripheral portion of the buried oxide film can be efficiently removed by a simple method.
- an epitaxial layer can be formed while preventing the formation of a valley-shaped step, and a high-quality thick film SOI wafer can be efficiently manufactured.
- FIG. 1 is a flowchart showing an example of a method for manufacturing an SOI wafer according to the present invention.
- a bond wafer 10 and a base wafer 11 made of a silicon single crystal are prepared.
- the bond wafer 10 and the base wafer 11 are not particularly limited as long as they are made of a silicon single crystal.
- the silicon single crystal wafer contains a dopant at a high concentration.
- the conductivity type may be either n-type or p-type.
- a silicon oxide film 12 is formed on the surface of the bond wafer 10. (An oxide film is not formed on the base wafer 11)
- the thickness of the silicon oxide film 12 formed at this time is not particularly limited, and can be formed by a thermal oxidation method such as wet oxidation, for example.
- the formed silicon oxide film 12 has an effect of preventing channeling at the time of ion implantation in a later step, and becomes a buried oxide film 14 after bonding.
- the thickness of the SOI layer 16 can be controlled by performing ion implantation while controlling the implantation energy and the like.
- the ion-implanted surface of the bond wafer 10 and the surface of the silicon single crystal of the base wafer 11 are interposed via the silicon oxide film 12. to paste together.
- an oxide film is not formed on the base wafer as in the present invention, but is formed on a bond wafer to prevent channeling.
- the buried silicon oxide film is used as a buried oxide film.
- the bond wafer 10 is peeled off by the ion implantation layer 13, so that the SOI layer 16 is provided, the terrace portion 18 on the outer periphery of the base wafer 11 has no oxide film, and silicon An SOI wafer 15 having the oxide film 12 as a buried oxide film 14 is produced.
- a bonded wafer is subjected to a heat treatment at a temperature of 500 ° C. or higher for 30 minutes or more in an inert gas atmosphere such as Ar, the bond wafer 10 is ion-implanted by crystal rearrangement and bubble aggregation.
- the layer 13 can be peeled off.
- chamfered part or chamfered part that is slightly thinner in the peripheral part of the base wafer and bond wafer to be bonded, and that part is not bonded after bonding and becomes an unbonded part, Since there is the unbonded portion, a region where the bonding surface of the base wafer is exposed is formed around the SOI layer after peeling, and the region is referred to as a terrace portion.
- the buried oxide film 14 has a structure in which the outer peripheral edge of the SOI layer 16 of the SOI wafer 15 is positioned outside the outer peripheral edge of the buried oxide film 14.
- a process of removing the outer peripheral portion is performed.
- the amount of removal of the outer peripheral portion of the buried oxide film 14 is not particularly limited as long as it has an overhang-shaped structure as described above. For example, it is larger than the width that is reduced by etching the SOI layer 16 during the heat treatment in the subsequent process. If the width of the buried oxide film 14 is removed, the buried oxide film 14 can be surely not exposed by etching by heat treatment.
- the process of removing the outer peripheral portion of the buried oxide film 14 is not particularly limited, and it is preferable to perform, for example, by immersing the SOI wafer 15 in an HF-containing aqueous solution. If the aqueous solution contains HF, the end surface of the outer peripheral portion of the buried oxide film 14 can be efficiently etched and removed so that the surface of the SOI layer 16 is not etched as much as possible, and the structure as described above is obtained. Easy.
- the SOI wafer 15 is heat-treated in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas.
- a planarization heat treatment By this planarization heat treatment, the surface roughness of the SOI layer after peeling can be improved and the damaged layer can be removed.
- the etching of the end face of the outer peripheral portion of the SOI layer proceeds and the outer peripheral portion of the SOI layer is etched and removed with a predetermined width.
- the outer peripheral portion of the buried oxide film is removed in advance and originally overhangs Due to the shape, the buried oxide film is not exposed to the outer periphery of the SOI layer.
- an epitaxial layer 17 is formed on the surface of the SOI layer 16 of the SOI wafer 15.
- a growth gas such as trichlorosilane (SiHCl 3 ) or dichlorosilane (SiH 2 Cl 2 ) and a hydrogen gas (H 2 ) as a carrier gas are supplied to an SOI wafer that has been grown to a growth temperature.
- the silicon epitaxial layer can be epitaxially grown.
- 2 and 3 are schematic cross-sectional views partially showing an SOI wafer manufactured by the manufacturing method of the present invention. As shown in FIG.
- the epitaxial layer 17 grown from the terrace portion 18 and the SOI layer 16 is connected and grown as one layer, an epi valley is not formed, and a high-quality thick film SOI wafer without dust generation and can do.
- the outer peripheral end of the SOI layer 16 and the buried oxide film 14 do not coincide with each other, and the outer peripheral end of the SOI layer 16 is located outside the outer peripheral end of the buried oxide film 14 (overhang shape). However, it can be epitaxially grown well. At this time, a cavity may be formed at the outer peripheral end portion of the buried oxide film 14, but since it has a small size of several ⁇ m or less, it does not affect the subsequent process.
- FIG. 4 is a flowchart showing an example of a method for manufacturing an SOI wafer according to another aspect of the present invention.
- the steps shown in FIGS. 4A to 4E from the bonding of the bond wafer 10 and the base wafer 11 to the separation of the SOI wafer 15 are shown in FIG. It can be carried out in the same manner as the steps a) to (e).
- FIG. 4F heat treatment is performed on the SOI wafer 15 in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas.
- a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas By this heat treatment, the surface of the SOI layer 16 is flattened and the outer peripheral portion is etched, so that the outer peripheral portion of the buried oxide film 14 is exposed.
- FIG. 4G a process of removing the buried oxide film 14 exposed on the outer periphery of the SOI layer 16 of the SOI wafer 15 is performed. In this case, at least a portion exposed on the outer periphery of the buried oxide film 14 may be removed. As shown in FIG. 3, the structure is further removed so that the outer peripheral edge of the SOI layer 16 is located outside the outer peripheral edge of the buried oxide film 14. It may be.
- the method for removing the exposed portion of the buried oxide film 14 is not particularly limited, and for example, the etching can be efficiently removed by immersing the SOI wafer 15 in an aqueous solution containing HF.
- an epitaxial layer 17 is formed on the surface of the SOI layer 16 as shown in FIG. Since the exposed portion of the buried oxide film 14 is removed in the previous step, the epitaxial layer 17 is well formed as shown in FIGS. 2 and 3, and the occurrence of an epi valley can be prevented.
- the SOI wafer manufacturing method of the present invention as described above can manufacture a high-quality thick film SOI wafer with good epitaxial growth.
- Example 1 An SOI wafer was manufactured through the steps of FIGS. First, a silicon single crystal wafer having a diameter of 300 mm and a crystal orientation ⁇ 100> was prepared as a bond wafer and a base wafer. An oxide film having a thickness of 150 nm was formed only on the bond wafer. Next, hydrogen (H + ) ions were implanted through the oxide film of the bond wafer (implantation conditions: 40 keV, 5 ⁇ 10 16 atoms / cm 2 ) to form an ion implantation layer inside the bond wafer.
- the manufactured SOI wafer was immersed in a 15% HF aqueous solution, and the BOX layer was etched. As a result, the outer peripheral edge of the BOX layer was formed 5 ⁇ m inside the outer peripheral edge of the SOI layer.
- the BOX layer was not exposed on the outer periphery of the SOI layer of the SOI wafer after the heat treatment.
- an epitaxial layer was grown to a film thickness of 4 ⁇ m on the SOI layer of the SOI wafer by using dichlorosilane as a source gas at 1080 ° C. for 4 minutes.
- An SEM photograph of the boundary between the SOI layer and the terrace portion of the SOI wafer manufactured as described above is shown in FIG. As shown in FIG. 5, there was almost no step at the boundary between the SOI layer and the terrace, and good epitaxial growth could be performed.
- FIG. 1 (f) shows an SEM photograph of the boundary portion between the SOI layer and the terrace portion of the manufactured SOI wafer.
- a valley-shaped step (Epi Valley) was formed at the boundary between the SOI layer and the terrace. Such an epi valley causes particle contamination in a later process.
- an epitaxial layer was grown to a film thickness of 4 ⁇ m on the SOI layer of the SOI wafer by using dichlorosilane as a source gas at 1080 ° C. for 4 minutes.
- An SEM photograph of the boundary between the SOI layer and the terrace portion of the SOI wafer manufactured as described above is shown in FIG. As shown in FIG. 6, no step was formed at the boundary between the SOI layer and the terrace portion, and good epitaxial growth could be performed.
- Example 2 As in Example 2, however, the SOI wafer was manufactured without performing etching removal (FIG. 4G) of the outer peripheral portion of the BOX layer after the heat treatment (HCl etching). In the SEM photograph of the boundary portion between the SOI layer and the terrace portion of the manufactured SOI wafer, an epi valley was formed as in FIG.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
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Abstract
Description
従って、前記熱処理が終了した段階(エピタキシャル成長が行われる直前)では、SOI層の外周の全周にわたって埋め込み酸化膜が露出した構造となってしまう。
このような場合、SOI層21から成長するエピタキシャル層20と、テラス部23からのエピタキシャル層24が接触し、この部分が発塵源となり、後の工程でのパーティクル汚染の原因となる。
このように行うことで、埋め込み酸化膜の外周部除去を簡易な方法で効率的に行うことができる。
このように行うことで、埋め込み酸化膜の露出した外周部の除去を簡易な方法で効率的に行うことができる。
本発明の製造方法では、まず、図1(a)に示すように、シリコン単結晶からなるボンドウェーハ10とベースウェーハ11を準備する。
ボンドウェーハ10及びベースウェーハ11としては、シリコン単結晶からなるものであれば、特に限定されないが、例えば、ゲッタリング能力を高める等といった目的のため、シリコン単結晶ウェーハに高濃度にドーパントを含ませたものを準備しても良く、その導電型はn型、p型のいずれであってもよい。
このとき形成するシリコン酸化膜12の厚さとしては特に限定されず、また、形成方法としても、例えば、wet酸化等の熱酸化方法により形成することができる。当該形成したシリコン酸化膜12は、後工程のイオン注入の際のチャネリング防止の効果を有し、また、貼り合わせ後には、埋め込み酸化膜14となる。
このとき形成するイオン注入層13の深さは、剥離後に形成されるSOI層16の厚さに反映される。従って、注入エネルギー等を制御してイオン注入することにより、SOI層16の厚さを制御できる。
例えば、200nm以下の比較的薄い埋め込み酸化膜を有するSOIウェーハを製造する場合等には、本発明のように、ベースウェーハには酸化膜を形成しないで、チャネリング防止のためにボンドウェーハに形成されたシリコン酸化膜を埋め込み酸化膜とする。
例えば、貼り合わせたウェーハに対して、Ar等の不活性ガス雰囲気下、500℃以上の温度、30分以上熱処理を加えれば、結晶の再配列と気泡の凝集とによって、ボンドウェーハ10をイオン注入層13で剥離することができる。
なお、貼り合わされるベースウェーハ、ボンドウェーハの周辺部には厚さが僅かに薄くなった研磨ダレと呼ばれる部分や面取り部が存在し、その部分は貼り合わせ後にも結合されず未結合部分となり、当該未結合部分があるため、剥離後には、SOI層の周りに、ベースウェーハの貼り合わせ面が露出したままの領域ができ、当該領域をテラス部という。
埋め込み酸化膜14の外周部を除去する量としては、上記のようなオーバーハング形状の構造となれば、特に限定されず、例えば、後工程の熱処理時にSOI層16がエッチングされて減少する幅以上の幅を除去すれば、熱処理のエッチングにより埋め込み酸化膜14が確実に露出しないようにできる。
HF含有水溶液であれば、SOI層16の表面をできるだけエッチングしないように、埋め込み酸化膜14の外周部の端面を効率的にエッチングして除去することができ、上記のような構造とすることが容易である。
この平坦化熱処理により、剥離後のSOI層の面粗さを改善し、ダメージ層を除去することができる。この際、SOI層の外周部の端面のエッチングが進行してSOI層の外周部が所定の幅でエッチング除去されるが、本発明では、予め埋め込み酸化膜の外周部は除去され、もともとオーバーハング形状なので、埋め込み酸化膜がSOI層の外周に露出することはない。
この際、例えば、成長温度にされたSOIウェーハに、トリクロロシラン(SiHCl3)、ジクロロシラン(SiH2Cl2)等の成長ガスと、キャリアガスとしての水素ガス(H2)を供給することで、シリコンエピタキシャル層をエピタキシャル成長させることができる。
図2、3は、本発明の製造方法により製造したSOIウェーハを部分的に示す概略断面図である。図2に示すように、テラス部18及びSOI層16から成長するエピタキシャル層17が一つの層として繋がって成長するため、エピ渓谷が形成されず、発塵のない高品質の厚膜SOIウェーハとすることができる。また、図3のようにSOI層16と埋め込み酸化膜14の外周端が一致せず、SOI層16の外周端が埋め込み酸化膜14の外周端より外側に位置する構造(オーバーハング形状)のままでも、良好にエピタキシャル成長させることができる。この際、埋め込み酸化膜14の外周端部分に空洞が形成される場合があるが、数μm以下の微小なサイズであるため、後工程への影響はない。
図4は、本発明の他の態様のSOIウェーハの製造方法の一例を示すフロー図である。
図4における本発明の製造方法では、ボンドウェーハ10とベースウェーハ11とを貼り合わせた後剥離してSOIウェーハ15を作製するまでの図4(a)-(e)の工程は、図1(a)-(e)の工程と同様に行うことができる。
次に、図4(g)に示すように、SOIウェーハ15のSOI層16の外周に露出した埋め込み酸化膜14を除去する処理を行う。
この場合、埋め込み酸化膜14の少なくとも外周に露出した部分を除去すればよく、図3のように、さらに除去してSOI層16の外周端が埋め込み酸化膜14の外周端より外側に位置する構造にしてもよい。
前工程で埋め込み酸化膜14の露出した部分を除去しているため、図2,3のように、エピタキシャル層17は良好に形成されて、エピ渓谷の発生を防止できる。
(実施例1)
図1(a)-(h)の工程でSOIウェーハを製造した。
まず、ボンドウェーハ及びベースウェーハとして、直径300mm、結晶方位<100>のシリコン単結晶ウェーハを準備した。ボンドウェーハのみに、厚さ150nmの酸化膜を形成した。次に、ボンドウェーハの酸化膜を通して水素(H+)をイオン注入して(注入条件:40keV、5×1016atoms/cm2)、ボンドウェーハ内部にイオン注入層を形成した。次に、常温で貼り合わせて、500℃、30分、アルゴン雰囲気で剥離熱処理を行い、ボンドウェーハを剥離して、テラス部に酸化膜のないSOIウェーハ(SOI層/BOX層=300nm/150nm)を作製した。
次に、エピタキシャル成長炉内で、1100℃、5分、塩化水素ガスを含む雰囲気(HCl=0.5SLM、H2=50SLM)で熱処理を行い(HClエッチング)、エッチング代185nmまでSOI層表面をエッチングした。この際、熱処理後のSOIウェーハのSOI層外周には、BOX層は露出していなかった。
上記のように製造したSOIウェーハのSOI層とテラス部の境界部分のSEM写真を図5に示す。図5に示すように、SOI層とテラス部の境界部分での段差はほとんど無く、良好なエピタキシャル成長を行うことができた。
実施例1と同様に、ただし、熱処理(HClエッチング)前のBOX層の外周部のエッチング除去(図1(f))は行わないで、SOIウェーハを製造した。
図8に、製造したSOIウェーハのSOI層とテラス部の境界部分のSEM写真を示す。
図8に示すように、SOI層とテラス部の境界部分には、渓谷状の段差(エピ渓谷)が形成されていた。このようなエピ渓谷は、後工程でのパーティクル汚染の原因となる。
図4(a)-(h)の工程でSOIウェーハを製造した。
まず、ボンドウェーハ及びベースウェーハとして、直径300mm、結晶方位<100>のシリコン単結晶ウェーハを準備した。ボンドウェーハのみに、厚さ150nmの酸化膜を形成した。次に、ボンドウェーハの酸化膜を通して水素(H+)をイオン注入して(注入条件:40keV、5×1016atoms/cm2)、ボンドウェーハ内部にイオン注入層を形成した。次に、常温で貼り合わせて、500℃、30分、アルゴン雰囲気で剥離熱処理を行い、ボンドウェーハを剥離して、テラス部に酸化膜のないSOIウェーハ(SOI層/BOX層=300nm/150nm)を作製した。
次に、SOIウェーハを15%HF水溶液に浸漬させて、露出したBOX層をエッチングした。これにより、BOX層の外周端はSOI層の外周端とほぼ同一の位置に形成された。
上記のように製造したSOIウェーハのSOI層とテラス部の境界部分のSEM写真を図6に示す。図6に示すように、SOI層とテラス部の境界部分での段差は形成されず、良好なエピタキシャル成長を行うことができた。
実施例2と同様に、ただし、熱処理(HClエッチング)後のBOX層の外周部のエッチング除去(図4(g))は行わないで、SOIウェーハを製造した。
製造したSOIウェーハのSOI層とテラス部の境界部分のSEM写真についても、比較例1の図8と同様にエピ渓谷が形成されていた。
Claims (4)
- シリコン単結晶からなるボンドウェーハの表面にシリコン酸化膜を形成し、該シリコン酸化膜を通して水素及び希ガスのうち少なくとも1種類のガスイオンをイオン注入して前記ボンドウェーハの内部にイオン注入層を形成し、該ボンドウェーハのイオン注入した表面と、シリコン単結晶からなるベースウェーハの表面とを前記シリコン酸化膜を介して貼り合わせた後、前記イオン注入層で前記ボンドウェーハを剥離することにより、前記ベースウェーハの外周のテラス部に酸化膜がなく、前記シリコン酸化膜を埋め込み酸化膜としたSOIウェーハを作製し、
該SOIウェーハのSOI層の外周端が、前記埋め込み酸化膜の外周端よりも外側に位置した構造となるように、該埋め込み酸化膜の外周部を除去する処理を行い、その後、前記SOIウェーハに水素を含む還元性雰囲気もしくは塩化水素ガスを含む雰囲気で熱処理を行った後、前記SOI層の表面にエピタキシャル層を形成することを特徴とするSOIウェーハの製造方法。 - 前記埋め込み酸化膜の外周部を除去する処理を、前記SOIウェーハをHF含有水溶液に浸漬させることによって行うことを特徴とする請求項1に記載のSOIウェーハの製造方法。
- シリコン単結晶からなるボンドウェーハの表面にシリコン酸化膜を形成し、該シリコン酸化膜を通して水素及び希ガスのうち少なくとも1種類のガスイオンをイオン注入して前記ボンドウェーハの内部にイオン注入層を形成し、該ボンドウェーハのイオン注入した表面と、シリコン単結晶からなるベースウェーハの表面とを前記シリコン酸化膜を介して貼り合わせた後、前記イオン注入層で前記ボンドウェーハを剥離することにより、前記ベースウェーハの外周のテラス部に酸化膜がなく、前記シリコン酸化膜を埋め込み酸化膜としたSOIウェーハを作製し、
該SOIウェーハに水素を含む還元性雰囲気もしくは塩化水素ガスを含む雰囲気で熱処理を行った後、該SOIウェーハのSOI層の外周に露出した前記埋め込み酸化膜を除去する処理を行い、その後、前記SOI層の表面にエピタキシャル層を形成することを特徴とするSOIウェーハの製造方法。 - 前記SOI層の外周に露出した埋め込み酸化膜を除去する処理を、前記SOIウェーハをHF含有水溶液に浸漬させることによって行うことを特徴とする請求項3に記載のSOIウェーハの製造方法。
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