TWI296434B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
TWI296434B
TWI296434B TW092115253A TW92115253A TWI296434B TW I296434 B TWI296434 B TW I296434B TW 092115253 A TW092115253 A TW 092115253A TW 92115253 A TW92115253 A TW 92115253A TW I296434 B TWI296434 B TW I296434B
Authority
TW
Taiwan
Prior art keywords
film
metal film
barrier metal
conductor pattern
pattern
Prior art date
Application number
TW092115253A
Other languages
English (en)
Chinese (zh)
Other versions
TW200401403A (en
Inventor
Watanabe Kenichi
Kawano Michiari
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW200401403A publication Critical patent/TW200401403A/zh
Application granted granted Critical
Publication of TWI296434B publication Critical patent/TWI296434B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW092115253A 2002-06-06 2003-06-05 Semiconductor device and method for manufacturing the same TWI296434B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002165818 2002-06-06
JP2003076962A JP4250006B2 (ja) 2002-06-06 2003-03-20 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
TW200401403A TW200401403A (en) 2004-01-16
TWI296434B true TWI296434B (en) 2008-05-01

Family

ID=29714357

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092115253A TWI296434B (en) 2002-06-06 2003-06-05 Semiconductor device and method for manufacturing the same

Country Status (5)

Country Link
US (2) US7119439B2 (https=)
JP (1) JP4250006B2 (https=)
KR (2) KR100930556B1 (https=)
CN (1) CN1290186C (https=)
TW (1) TWI296434B (https=)

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US20040245636A1 (en) * 2003-06-06 2004-12-09 International Business Machines Corporation Full removal of dual damascene metal level
US7387960B2 (en) * 2003-09-16 2008-06-17 Texas Instruments Incorporated Dual depth trench termination method for improving Cu-based interconnect integrity
JPWO2005034234A1 (ja) * 2003-10-02 2006-12-14 富士通株式会社 半導体装置及びその製造方法
JP2005136215A (ja) * 2003-10-30 2005-05-26 Toshiba Corp 半導体装置
JP2005142262A (ja) * 2003-11-05 2005-06-02 Toshiba Corp 半導体装置および半導体装置の製造方法
JP4603281B2 (ja) 2004-03-31 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4946436B2 (ja) * 2004-03-31 2012-06-06 日本電気株式会社 半導体装置及びその製造方法
JP4280204B2 (ja) 2004-06-15 2009-06-17 Ｏｋｉセミコンダクタ株式会社 半導体装置
JP2006073891A (ja) * 2004-09-03 2006-03-16 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
US7777338B2 (en) * 2004-09-13 2010-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure for integrated circuit chips
US7125791B2 (en) * 2004-10-12 2006-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced copper damascene structure
KR100782202B1 (ko) 2005-02-25 2007-12-05 가부시끼가이샤 도시바 반도체 장치 및 그 제조 방법
US7479447B2 (en) * 2005-04-04 2009-01-20 International Business Machines Corporation Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses
JP2007012996A (ja) * 2005-07-01 2007-01-18 Toshiba Corp 半導体装置
JP2007019188A (ja) * 2005-07-06 2007-01-25 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP4282646B2 (ja) * 2005-09-09 2009-06-24 株式会社東芝 半導体装置の製造方法
JP4699172B2 (ja) * 2005-10-25 2011-06-08 ルネサスエレクトロニクス株式会社 半導体装置
US7449785B2 (en) * 2006-02-06 2008-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump on a semiconductor substrate
JP2008016638A (ja) * 2006-07-06 2008-01-24 Sony Corp 半導体装置
JP4864608B2 (ja) * 2006-08-28 2012-02-01 東京エレクトロン株式会社 課金方法、記憶媒体及び半導体デバイス製造装置
JP4506767B2 (ja) * 2007-02-28 2010-07-21 カシオ計算機株式会社 半導体装置の製造方法
JP5332200B2 (ja) * 2007-03-22 2013-11-06 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
KR100995558B1 (ko) 2007-03-22 2010-11-22 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법
WO2008126268A1 (ja) * 2007-03-30 2008-10-23 Fujitsu Microelectronics Limited 半導体装置
JP5117791B2 (ja) * 2007-08-22 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置
JP2009076782A (ja) * 2007-09-21 2009-04-09 Sharp Corp 半導体基板、その製造方法、および半導体チップ
JP2009088269A (ja) * 2007-09-28 2009-04-23 Toshiba Corp 半導体装置、およびその製造方法
JP2009135139A (ja) * 2007-11-28 2009-06-18 Toshiba Corp 半導体装置及びその製造方法
US7704804B2 (en) 2007-12-10 2010-04-27 International Business Machines Corporation Method of forming a crack stop laser fuse with fixed passivation layer coverage
US7956466B2 (en) * 2008-05-09 2011-06-07 International Business Machines Corporation Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
US8772156B2 (en) * 2008-05-09 2014-07-08 International Business Machines Corporation Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications
JP2010153543A (ja) * 2008-12-25 2010-07-08 Fujitsu Ltd 半導体装置およびその製造方法
US7892926B2 (en) 2009-07-24 2011-02-22 International Business Machines Corporation Fuse link structures using film stress for programming and methods of manufacture
US8124448B2 (en) 2009-09-18 2012-02-28 Advanced Micro Devices, Inc. Semiconductor chip with crack deflection structure
US8592941B2 (en) 2010-07-19 2013-11-26 International Business Machines Corporation Fuse structure having crack stop void, method for forming and programming same, and design structure
CN103185998B (zh) * 2011-12-30 2015-07-15 上海天马微电子有限公司 非晶硅栅极驱动线路的形成方法及液晶显示器形成方法
JP5834934B2 (ja) 2012-01-17 2015-12-24 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
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Also Published As

Publication number Publication date
US20050042816A1 (en) 2005-02-24
TW200401403A (en) 2004-01-16
KR20090094204A (ko) 2009-09-04
CN1467837A (zh) 2004-01-14
KR100964263B1 (ko) 2010-06-16
CN1290186C (zh) 2006-12-13
US7119439B2 (en) 2006-10-10
KR100930556B1 (ko) 2009-12-09
US7241676B2 (en) 2007-07-10
JP4250006B2 (ja) 2009-04-08
US20030227089A1 (en) 2003-12-11
KR20030095245A (ko) 2003-12-18
JP2004064046A (ja) 2004-02-26

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