JP4250006B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP4250006B2
JP4250006B2 JP2003076962A JP2003076962A JP4250006B2 JP 4250006 B2 JP4250006 B2 JP 4250006B2 JP 2003076962 A JP2003076962 A JP 2003076962A JP 2003076962 A JP2003076962 A JP 2003076962A JP 4250006 B2 JP4250006 B2 JP 4250006B2
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Japan
Prior art keywords
film
barrier metal
pattern
interlayer insulating
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003076962A
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English (en)
Japanese (ja)
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JP2004064046A5 (https=
JP2004064046A (ja
Inventor
健一 渡邉
通有 河野
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to JP2003076962A priority Critical patent/JP4250006B2/ja
Priority to KR1020030035584A priority patent/KR100930556B1/ko
Priority to TW092115253A priority patent/TWI296434B/zh
Priority to US10/454,667 priority patent/US7119439B2/en
Priority to CNB031424244A priority patent/CN1290186C/zh
Publication of JP2004064046A publication Critical patent/JP2004064046A/ja
Priority to US10/948,569 priority patent/US7241676B2/en
Publication of JP2004064046A5 publication Critical patent/JP2004064046A5/ja
Application granted granted Critical
Publication of JP4250006B2 publication Critical patent/JP4250006B2/ja
Priority to KR1020090067257A priority patent/KR100964263B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2003076962A 2002-06-06 2003-03-20 半導体装置及びその製造方法 Expired - Fee Related JP4250006B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2003076962A JP4250006B2 (ja) 2002-06-06 2003-03-20 半導体装置及びその製造方法
KR1020030035584A KR100930556B1 (ko) 2002-06-06 2003-06-03 반도체 장치 및 그 제조 방법
US10/454,667 US7119439B2 (en) 2002-06-06 2003-06-05 Semiconductor device and method for manufacturing the same
TW092115253A TWI296434B (en) 2002-06-06 2003-06-05 Semiconductor device and method for manufacturing the same
CNB031424244A CN1290186C (zh) 2002-06-06 2003-06-06 半导体器件及其制造方法
US10/948,569 US7241676B2 (en) 2002-06-06 2004-09-24 Semiconductor device and method for manufacturing the same
KR1020090067257A KR100964263B1 (ko) 2002-06-06 2009-07-23 반도체 장치 및 그 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002165818 2002-06-06
JP2003076962A JP4250006B2 (ja) 2002-06-06 2003-03-20 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2004064046A JP2004064046A (ja) 2004-02-26
JP2004064046A5 JP2004064046A5 (https=) 2006-05-11
JP4250006B2 true JP4250006B2 (ja) 2009-04-08

Family

ID=29714357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003076962A Expired - Fee Related JP4250006B2 (ja) 2002-06-06 2003-03-20 半導体装置及びその製造方法

Country Status (5)

Country Link
US (2) US7119439B2 (https=)
JP (1) JP4250006B2 (https=)
KR (2) KR100930556B1 (https=)
CN (1) CN1290186C (https=)
TW (1) TWI296434B (https=)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4360881B2 (ja) * 2003-03-24 2009-11-11 Ｎｅｃエレクトロニクス株式会社 多層配線を含む半導体装置およびその製造方法
US20040245636A1 (en) * 2003-06-06 2004-12-09 International Business Machines Corporation Full removal of dual damascene metal level
US7387960B2 (en) * 2003-09-16 2008-06-17 Texas Instruments Incorporated Dual depth trench termination method for improving Cu-based interconnect integrity
JPWO2005034234A1 (ja) * 2003-10-02 2006-12-14 富士通株式会社 半導体装置及びその製造方法
JP2005136215A (ja) * 2003-10-30 2005-05-26 Toshiba Corp 半導体装置
JP2005142262A (ja) * 2003-11-05 2005-06-02 Toshiba Corp 半導体装置および半導体装置の製造方法
JP4603281B2 (ja) 2004-03-31 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4946436B2 (ja) * 2004-03-31 2012-06-06 日本電気株式会社 半導体装置及びその製造方法
JP4280204B2 (ja) 2004-06-15 2009-06-17 Ｏｋｉセミコンダクタ株式会社 半導体装置
JP2006073891A (ja) * 2004-09-03 2006-03-16 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
US7777338B2 (en) * 2004-09-13 2010-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure for integrated circuit chips
US7125791B2 (en) * 2004-10-12 2006-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced copper damascene structure
KR100782202B1 (ko) 2005-02-25 2007-12-05 가부시끼가이샤 도시바 반도체 장치 및 그 제조 방법
US7479447B2 (en) * 2005-04-04 2009-01-20 International Business Machines Corporation Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses
JP2007012996A (ja) * 2005-07-01 2007-01-18 Toshiba Corp 半導体装置
JP2007019188A (ja) * 2005-07-06 2007-01-25 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP4282646B2 (ja) * 2005-09-09 2009-06-24 株式会社東芝 半導体装置の製造方法
JP4699172B2 (ja) * 2005-10-25 2011-06-08 ルネサスエレクトロニクス株式会社 半導体装置
US7449785B2 (en) * 2006-02-06 2008-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump on a semiconductor substrate
JP2008016638A (ja) * 2006-07-06 2008-01-24 Sony Corp 半導体装置
JP4864608B2 (ja) * 2006-08-28 2012-02-01 東京エレクトロン株式会社 課金方法、記憶媒体及び半導体デバイス製造装置
JP4506767B2 (ja) * 2007-02-28 2010-07-21 カシオ計算機株式会社 半導体装置の製造方法
JP5332200B2 (ja) * 2007-03-22 2013-11-06 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
KR100995558B1 (ko) 2007-03-22 2010-11-22 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법
WO2008126268A1 (ja) * 2007-03-30 2008-10-23 Fujitsu Microelectronics Limited 半導体装置
JP5117791B2 (ja) * 2007-08-22 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置
JP2009076782A (ja) * 2007-09-21 2009-04-09 Sharp Corp 半導体基板、その製造方法、および半導体チップ
JP2009088269A (ja) * 2007-09-28 2009-04-23 Toshiba Corp 半導体装置、およびその製造方法
JP2009135139A (ja) * 2007-11-28 2009-06-18 Toshiba Corp 半導体装置及びその製造方法
US7704804B2 (en) 2007-12-10 2010-04-27 International Business Machines Corporation Method of forming a crack stop laser fuse with fixed passivation layer coverage
US7956466B2 (en) * 2008-05-09 2011-06-07 International Business Machines Corporation Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
US8772156B2 (en) * 2008-05-09 2014-07-08 International Business Machines Corporation Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications
JP2010153543A (ja) * 2008-12-25 2010-07-08 Fujitsu Ltd 半導体装置およびその製造方法
US7892926B2 (en) 2009-07-24 2011-02-22 International Business Machines Corporation Fuse link structures using film stress for programming and methods of manufacture
US8124448B2 (en) 2009-09-18 2012-02-28 Advanced Micro Devices, Inc. Semiconductor chip with crack deflection structure
US8592941B2 (en) 2010-07-19 2013-11-26 International Business Machines Corporation Fuse structure having crack stop void, method for forming and programming same, and design structure
CN103185998B (zh) * 2011-12-30 2015-07-15 上海天马微电子有限公司 非晶硅栅极驱动线路的形成方法及液晶显示器形成方法
JP5834934B2 (ja) 2012-01-17 2015-12-24 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
US8906801B2 (en) * 2012-03-12 2014-12-09 GlobalFoundries, Inc. Processes for forming integrated circuits and integrated circuits formed thereby
JP5504311B2 (ja) * 2012-08-06 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8916461B2 (en) 2012-09-20 2014-12-23 International Business Machines Corporation Electronic fuse vias in interconnect structures
TWI495074B (zh) 2012-11-30 2015-08-01 財團法人工業技術研究院 減能結構
US9691719B2 (en) * 2013-01-11 2017-06-27 Renesas Electronics Corporation Semiconductor device
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
US10475796B1 (en) * 2018-06-28 2019-11-12 Micron Technology, Inc. Method of forming an array of capacitors, a method of forming DRAM circuitry, and a method of forming an elevationally-elongated conductive structure of integrated circuitry
US10461149B1 (en) 2018-06-28 2019-10-29 Micron Technology, Inc. Elevationally-elongated conductive structure of integrated circuitry, method of forming an array of capacitors, method of forming DRAM circuitry, and method of forming an elevationally-elongated conductive structure of integrated circuitry
US11373962B2 (en) * 2020-08-14 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Advanced seal ring structure and method of making the same
JP2024147901A (ja) * 2023-04-04 2024-10-17 イビデン株式会社 配線基板

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291891B1 (en) * 1998-01-13 2001-09-18 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device
JP3469771B2 (ja) * 1998-03-24 2003-11-25 富士通株式会社 半導体装置およびその製造方法
JPH11312680A (ja) * 1998-04-30 1999-11-09 Nec Corp 配線の形成方法
JP3293792B2 (ja) 1999-01-12 2002-06-17 日本電気株式会社 半導体装置及びその製造方法
JP4108228B2 (ja) 1999-07-15 2008-06-25 富士通株式会社 半導体装置の製造方法
JP4192348B2 (ja) 1999-08-09 2008-12-10 株式会社デンソー 半導体装置
US6566258B1 (en) 2000-05-10 2003-05-20 Applied Materials, Inc. Bi-layer etch stop for inter-level via
US6362524B1 (en) * 2000-07-26 2002-03-26 Advanced Micro Devices, Inc. Edge seal ring for copper damascene process and method for fabrication thereof
JP2002076114A (ja) 2000-08-30 2002-03-15 Hitachi Ltd 半導体装置の製造方法
JP4118029B2 (ja) * 2001-03-09 2008-07-16 富士通株式会社 半導体集積回路装置とその製造方法
JP4523194B2 (ja) * 2001-04-13 2010-08-11 富士通セミコンダクター株式会社 半導体装置とその製造方法
US6566171B1 (en) * 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
JP4948715B2 (ja) * 2001-06-29 2012-06-06 富士通セミコンダクター株式会社 半導体ウエハ装置およびその製造方法
JP2003115535A (ja) * 2001-10-04 2003-04-18 Hitachi Ltd 半導体集積回路装置
JP3757143B2 (ja) * 2001-10-11 2006-03-22 富士通株式会社 半導体装置の製造方法及び半導体装置
US6734090B2 (en) * 2002-02-20 2004-05-11 International Business Machines Corporation Method of making an edge seal for a semiconductor device
JP3813562B2 (ja) * 2002-03-15 2006-08-23 富士通株式会社 半導体装置及びその製造方法
JP4088120B2 (ja) * 2002-08-12 2008-05-21 株式会社ルネサステクノロジ 半導体装置

Also Published As

Publication number Publication date
US20050042816A1 (en) 2005-02-24
TW200401403A (en) 2004-01-16
KR20090094204A (ko) 2009-09-04
CN1467837A (zh) 2004-01-14
KR100964263B1 (ko) 2010-06-16
CN1290186C (zh) 2006-12-13
US7119439B2 (en) 2006-10-10
KR100930556B1 (ko) 2009-12-09
US7241676B2 (en) 2007-07-10
TWI296434B (en) 2008-05-01
US20030227089A1 (en) 2003-12-11
KR20030095245A (ko) 2003-12-18
JP2004064046A (ja) 2004-02-26

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