TWI265526B - Semiconductor memory device and arrangement method thereof - Google Patents

Semiconductor memory device and arrangement method thereof

Info

Publication number
TWI265526B
TWI265526B TW094131055A TW94131055A TWI265526B TW I265526 B TWI265526 B TW I265526B TW 094131055 A TW094131055 A TW 094131055A TW 94131055 A TW94131055 A TW 94131055A TW I265526 B TWI265526 B TW I265526B
Authority
TW
Taiwan
Prior art keywords
signal lines
memory device
semiconductor memory
column selecting
arrangement method
Prior art date
Application number
TW094131055A
Other languages
English (en)
Other versions
TW200614257A (en
Inventor
Chul-Woo Park
Sung-Hoon Kim
Hyuk-Joon Kwon
Jung-Bae Lee
Youn-Sik Park
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200614257A publication Critical patent/TW200614257A/zh
Application granted granted Critical
Publication of TWI265526B publication Critical patent/TWI265526B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
TW094131055A 2004-09-10 2005-09-09 Semiconductor memory device and arrangement method thereof TWI265526B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040072761A KR100615575B1 (ko) 2004-09-10 2004-09-10 반도체 메모리 장치 및 이 장치의 배치 방법

Publications (2)

Publication Number Publication Date
TW200614257A TW200614257A (en) 2006-05-01
TWI265526B true TWI265526B (en) 2006-11-01

Family

ID=36159688

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094131055A TWI265526B (en) 2004-09-10 2005-09-09 Semiconductor memory device and arrangement method thereof

Country Status (4)

Country Link
US (3) US7295454B2 (zh)
JP (1) JP5068438B2 (zh)
KR (1) KR100615575B1 (zh)
TW (1) TWI265526B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632550B (zh) * 2011-09-22 2018-08-11 瑞薩電子股份有限公司 半導體裝置

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7161823B2 (en) * 2004-06-03 2007-01-09 Samsung Electronics Co., Ltd. Semiconductor memory device and method of arranging signal and power lines thereof
KR100665837B1 (ko) * 2004-11-18 2007-01-09 삼성전자주식회사 반도체 메모리 장치에서의 라인 배치 구조
JP2008258425A (ja) * 2007-04-05 2008-10-23 Matsushita Electric Ind Co Ltd 標準セルおよびこれを有する半導体装置
KR100833596B1 (ko) * 2007-04-30 2008-05-30 주식회사 하이닉스반도체 반도체 장치 및 그의 레이아웃 방법
JP5690464B2 (ja) * 2007-11-20 2015-03-25 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
KR20090090602A (ko) * 2008-02-21 2009-08-26 삼성전자주식회사 워드 라인 저항을 감소시킬 수 있는 상 변화 메모리 장치
JP2012043486A (ja) * 2010-08-13 2012-03-01 Elpida Memory Inc 半導体装置
US9214219B2 (en) 2011-08-30 2015-12-15 Rambus Inc. Distributed sub-page selection
JP2013131615A (ja) * 2011-12-21 2013-07-04 Elpida Memory Inc 半導体装置
CN105825881B (zh) * 2015-01-09 2019-01-01 旺宏电子股份有限公司 记忆体
KR102291518B1 (ko) 2015-03-20 2021-08-20 삼성전자주식회사 불휘발성 메모리 장치 및 불휘발성 메모리 장치를 포함하는 스토리지 장치
US9818623B2 (en) 2016-03-22 2017-11-14 Globalfoundries Inc. Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
US9786545B1 (en) 2016-09-21 2017-10-10 Globalfoundries Inc. Method of forming ANA regions in an integrated circuit
US9818640B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines
US9818641B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines
US9852986B1 (en) 2016-11-28 2017-12-26 Globalfoundries Inc. Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US10043703B2 (en) 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US9887127B1 (en) * 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US9812351B1 (en) 2016-12-15 2017-11-07 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned continuity cuts
US10262935B2 (en) * 2016-12-16 2019-04-16 Samsung Electronics Co., Ltd. Memory device and method of disposing conduction lines of the same
KR20200132035A (ko) 2019-05-15 2020-11-25 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법
US11043500B1 (en) * 2020-03-19 2021-06-22 Micron Technology, Inc. Integrated assemblies comprising twisted digit line configurations

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04340252A (ja) * 1990-07-27 1992-11-26 Mitsubishi Electric Corp 半導体集積回路装置及びセルの配置配線方法
JP3212795B2 (ja) * 1994-03-15 2001-09-25 株式会社東芝 ダイナミック型半導体記憶装置
JPH0863957A (ja) 1994-08-24 1996-03-08 Hitachi Ltd データ線ツイスト部配置方法及びこれを用いた半導体集積回路装置
JP3666671B2 (ja) * 1994-12-20 2005-06-29 株式会社日立製作所 半導体装置
JP3453235B2 (ja) * 1995-09-14 2003-10-06 三菱電機株式会社 半導体記憶装置
JPH09253806A (ja) 1996-03-25 1997-09-30 Nippon Steel Corp 連続鋳造用タンディッシュおよびその使用方法
US5821592A (en) * 1997-06-30 1998-10-13 Siemens Aktiengesellschaft Dynamic random access memory arrays and methods therefor
KR100300047B1 (ko) * 1998-05-30 2001-09-22 김영환 노이즈 간섭 방지를 위한 데이터라인 배열 구조를 갖는 반도체 메모리 소자
JP2000022108A (ja) * 1998-07-02 2000-01-21 Hitachi Ltd 半導体記憶装置
JP3779480B2 (ja) * 1999-02-10 2006-05-31 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
KR20010016800A (ko) * 1999-08-04 2001-03-05 윤종용 반도체 메모리 장치의 신호 라인 배치방법
KR100310992B1 (ko) * 1999-09-03 2001-10-18 윤종용 멀티 뱅크 메모리 장치 및 입출력 라인 배치방법
JP4127605B2 (ja) 2001-09-07 2008-07-30 株式会社東芝 半導体記憶装置
JP2003085976A (ja) * 2001-09-11 2003-03-20 Seiko Epson Corp 半導体集積回路
US6980462B1 (en) * 2003-11-18 2005-12-27 Lsi Logic Corporation Memory cell architecture for reduced routing congestion
KR100642636B1 (ko) * 2004-07-30 2006-11-10 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 라인 배치 방법
US7142471B2 (en) * 2005-03-31 2006-11-28 Sandisk 3D Llc Method and apparatus for incorporating block redundancy in a memory array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632550B (zh) * 2011-09-22 2018-08-11 瑞薩電子股份有限公司 半導體裝置

Also Published As

Publication number Publication date
KR20060023866A (ko) 2006-03-15
US20080013397A1 (en) 2008-01-17
US20060055045A1 (en) 2006-03-16
JP5068438B2 (ja) 2012-11-07
KR100615575B1 (ko) 2006-08-25
US7295454B2 (en) 2007-11-13
US7679985B2 (en) 2010-03-16
US20080013357A1 (en) 2008-01-17
TW200614257A (en) 2006-05-01
US7391636B2 (en) 2008-06-24
JP2006080537A (ja) 2006-03-23

Similar Documents

Publication Publication Date Title
TWI265526B (en) Semiconductor memory device and arrangement method thereof
WO2007143393A3 (en) Method and system for providing a magnetic memory structure utilizing spin transfer
TW200633281A (en) Semiconductor device and driving method of the same
TW200636974A (en) Semiconductor device and method for controlling operation thereof
TW200721177A (en) Semiconductor memory device
WO2008006081A3 (en) Memories with selective precharge
WO2007134247A3 (en) Dynamic cell bit resolution
TW200624842A (en) Structure and method for failure analysis in a semiconductor device
WO2010079450A3 (en) System, method and apparatus for memory with semaphore controlled access of component ram cells by an external component
EP1710804A3 (en) Line layout structure, semiconductor memory device, and layout method
TW200802813A (en) Single-mask phase change memory element
TW200710871A (en) Memory device and tracking circuit
WO2009035505A3 (en) Storing operational information in an array of memory cells
TW200625334A (en) Memory system, memory device, and output data strobe signal generating method
TW200707189A (en) Memory block erasing in a flash memory device
WO2005064478A3 (en) Unified memory organization for power savings
TW200733106A (en) Nonvolatile semiconductor memory device
TW200604787A (en) Method for testing and programming memory devices and system for same
TW200802369A (en) Nonvolatile semiconductor memory device
TW200737182A (en) High-bandwidth magnetoresistive random access memory devices and methods of operation thereof
TW200703362A (en) Memory modules and memory systems having the same
TW200744203A (en) Non-volatile memory integrated circuit device and method of fabricating the same
TW200603158A (en) System and method for a high-speed access architecture for semiconductor memory
TW200731271A (en) Nonvolatile semiconductor memory device
TW200610104A (en) Semiconductor memory devices and signal line arrangements and related methods

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees