TWI235457B - Fin FET devices from bulk semiconductor and method for forming - Google Patents

Fin FET devices from bulk semiconductor and method for forming Download PDF

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Publication number
TWI235457B
TWI235457B TW092114901A TW92114901A TWI235457B TW I235457 B TWI235457 B TW I235457B TW 092114901 A TW092114901 A TW 092114901A TW 92114901 A TW92114901 A TW 92114901A TW I235457 B TWI235457 B TW I235457B
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Taiwan
Prior art keywords
fin
semiconductor substrate
fins
substrate
layer
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TW092114901A
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English (en)
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TW200411833A (en
Inventor
David M Fried
Edward J Nowak
Beth Ann Rainey
Devendra K Sadana
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Ibm
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Publication of TWI235457B publication Critical patent/TWI235457B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

1235457 玫、發明說明： 【發明所屬之技術領域】 本發明概言之係關於半導體製造領域，更具體而言，係 關於一種製造鰭式場效電晶體之方法。 【先前技術】 在半導體裝置生產中維持成本及效能競爭力之需求，已 促使積體電路中裝置密度增大。為利於達成裝置密度之增 大，需要技術不斷的推陳出新以縮小該等半導體裝置之形 體尺寸。 持續增大裝置密度之推動力在CM0S技術中（例如在場效 電晶體（^ET)設計及製造中）尤為強烈。場效電晶體構成 CMOS的取王要組件。為在CM〇s中獲得更高的裝置密度而 按比例縮小場效電晶體會導致效能及/或可靠性的降低。 人們已提出的可料提高裝置密度的—種附為韓式場 =電晶體。在鰭式場效電晶體中，電晶體本體自—垂直結 構形成，因其形似於魚類背鍅 *、肩N -而通常稱作鰭片。爾後，在 成鰭式場效電晶體之閑極。‘鳍式場效 大裝置尺寸即可達成更 C刪尺寸，同時維持可體有利於按比例縮小 遺憾的是，在鰭式電晶f
難。首先，在缺又故計及製造中出現數種困 難首先，在鰭式電晶體中，一 t + M 效電晶體裝置。具體而言，Μ Ή要電絕緣每一鰭式場 且單個裝置之源極和沒極亦y要^^曰日:需要相互絕緣， 耦。為此，鰭式場效電晶體已1A ^萑保源極對汲極解 85802 ^ ¥自矽絕緣體（SOI)晶圓製 .6 1235457 成，以提供不同裝置之鰭片間的絕緣。具體而言，電晶體 之鰭片自隱埋絕緣層上的矽層製成，因此每一鰭片皆藉^ 鰭片下的隱埋絕緣層與其㈣片絕緣。同樣，錢=效 電晶體之源極區與汲極區之間亦#由隱埋絕緣層相互解 韓0 儘管使用SOI晶圓可提供‘緯式場效電晶體所需的絕緣，但 其並非無顯著缺點。自S0I晶圓製成鰭式場效電晶體的最顯 著缺點在於··與體型$晶圓相比，⑽晶圓的成本增大。舉 例而言，SO;圓的成本通常二至三倍於體型珍晶圓的成 本。SOI晶圓的該種增大的成本儘管在某些應用中尚可接 受，但在其他應用中則高得令人難以接受。此外，S0I晶圓 的使用並非相容於所有製造製程，例如常用的㈣製程。 在體型晶圓上實施裝置絕緣的方法曾闡述於Hlsamot。等 人所著”一種全耗盡窄通道電晶體（DELTA)_ 一種新穎的 垂直超薄 S0I M0SFET(A fully Depleted Lean channel
Trans1Stor(DELTA) A novel vertical ultra thm §〇I M〇SFET)” （1989年國際電子裝置會議（加⑽如嶋^
Electron Deuces Meeting 1989)，^34.5.1^1^ , ^ 833-6 頁）中。該方法要求在鰭片上建構—氮化物襯塾，從而在氧 化底層基板以製成絕緣區域的過程中保護鰭片。由此即可 相對錯片選擇性地氧化基板。該製程的限制在於氧化溫度 車乂同（1,100 C )且在形成絕緣層時不能調㈣片厚度。隨著 裝置持續縮小，其耐受高溫狀態的能力亦隨之降低；因此， Hisamoto等人提出的製程無法相容於錯式電晶體可發揮其 85802 Ϊ235457 用途的奈米級技術。況且，不能調整鰭片厚度意味著該等 裝置的一關键尺寸僅決定於微影技術。如下文所詳細論 述，本發明方法之一特徵在於其可提供藉由氧化來調整鰭 片之能力，從而旎夠超越微影技術能力而最佳化鰭片厚度。 此外，msamoto提出的製程未提供一種控制鰭片高度之 方法。體型晶圓缺少一可在上面終止鰭片蝕刻之層面，例 如藉由於SOI晶圓中隱埋氧化層而提供之層面。若無該蝕刻 、、冬止層，則蝕刻厚度之變化性轉變為鰭片高度之變化性。 由於孩裝置所傳導的電流量正比於鰭片高度，因此最小化 轉片高度之變化性至關重要。 、因此，需要提供改良的製造方法和結構，以利於自體型 矽材製成鰭式電晶體裝置，同時最小化裝置變化性並提供 充分的裝置絕緣。 【發明内容】 ，本發明提供一種裝置結構及已克服先前技術眾多缺點的 、曰式％效電晶體（FET)製成方法。具體而言，該裝置結構及 ^ 仏自心型半導體晶圓製成鰭式場效電晶體之能力， 同時提供改良的裝置均勻度。 弋P罘、怨樣中，本發明係一種在半導體基板中製成一鰭 野^包晶體之方法，該方法包括下列步半導體基 板製成缺 ^ 戶 —鳍片；及對該基板實施一可進一步界定該鰭片寬 又且同時絕緣該鳍片之製程。 ,吊—態樣中，本發明係一種在半導體基板中製成一鳍 式場致兩曰舰 兒曰曰随之方法，該方法包括下列步騾：自苹導體基 1235457 板製成一包括一鰭片側壁的鰭片，該鰭片的製成暴露出田比 鄰該錯片的半導體基板區；損壞鄰接該鰭片的半導體基板 區之至少一邵分；氧化該半導體基板，使在該半導體基板 <受損部分中形成的氧化物厚於在鰭片側壁上形成的氧化 物。 由下文如附圖所闡釋的本發明一較佳具體實施例之更具 體說明可知曉本發明之前述及其他優點和特點。 【實施方式】 本發明提供一種裝置結構及已克服先前技術眾多缺點的 鰭式場效電晶體（FET)製成方法。具體而言，該裝置結構及 方法提供自體型半導體晶圓製成鰭式場效電晶體裝置且同 時改良裝置均勻度之能力。該方法有助於自體型半導體晶 圓製成鰭式場效電晶體裝置，並改良鰭片高度控制。此外， 孩方法亦提供自體型半導體製成鰭式場效電晶體之能力， 同時k供各鰭片之間的絕緣及單個鰭式場效電晶體中源極 區與汲極區之間的絕緣。最後，該方法亦可達成鳍片寬度 的最佳化。目A ’本發明裝置結構及方法可提供在體型晶 圓上均勻製成鳍式場效電晶體之優點。 本發明之一具體實施例在鰭片圖案化之前使用一製程以 改艮鰭片高度控制。該製程可包括植人—種可將基板損壞 至—所需深度之重離子’以改變受損基板相對於未受損基 板之姓刻率。由此可藉由最小化蚀刻速度變化之影變而在 鰭片圖案化過程中改良高度控制。第二替代製程可^括在 一所需深度處植入或製成一標記層。在鳍片蝕刻過程中， 85802 1235457 監測標記層之各元件，藉以精確確定何時達到所需餘刻、、果 度。該兩種製程控制技術皆可改良鰭片高度之均勻度，從 而能夠自體型半導體晶圓製成鰭片且將晶圓間之差異降至 最低。 本發明之第二態樣係在相鄰鰭片之間及在單個績式場效 電晶體之源極區與汲極區間形成絕緣。此外，該製程可最 佳化鰭片自身寬度。該製程首先選擇性地損壞各鰭片之間 的半導fa晶圓。此種選擇性損壞可藉由在各鳍片間植入適 當重離子或藉由植入一 p型物質並隨之實施一選擇性陽極 反應來達成。該等方法損壞毗鄰於鰭片的暴露的半導體晶 圓，但可藉由鰭片頂部的一保護性硬光罩層來最小化對鰭 片自身的損壞。爾後氧化晶圓，由此在各鰭片側壁上及在 各鰭片之間的區域中形成氧化。受損晶圓區域的氧化快於 未受損區域，因而使各鰭片之間的氧化物厚度大於鰭片自 身上的氧化物厚度。該氧化速率差可使各鰭片之間形成足 夠的氧化物而不使鰭片過度變_。 泫製私在各鰭片之間形成充分氧化，以在各鰭片之間及 在鰭片源極區與汲極區之間提供絕緣。此外，在鰭片上形 成氧化物會縮笮鰭片自身。當自鰭片側壁移除該氧化物之 後，由此得到的鰭片寬度將比原始寬度進一步最佳化，而 各鳍片4間則留存足夠的氧化物以提供絕緣。因此，該製 程可絕緣各鰭片並同時最佳化鰭片寬度。 因此，所提供方法有利於自骨豊型石夕材製成鰭式場效電晶 體裝置，同時可提供對鰭片高度和寬度的增強控制及鰭片 85802 -10- 1235457 源極區域與汲極區域之間的增強絕緣。 本發明可方便地適用於多種鰭式場效電晶體及以前曾大 多在S0I基板上製造的其相關裝置。舉例而言，該等方法可 用於製成帛6,252,284號美目㈣所揭示的雙雜鰭式場效 電晶體。因此，凡熟習此項技藝者即可理解，本發明並非 局限於附圖所闡釋之具體結構或本文所詳述之具體步驟。 残瞭解，本發明並㈣限於任何具體摻雜劑類型，其限 =條件為選擇用於各组件的轉劑類型與該裝置擬實施的 電作業相一致。 現在參見圖卜該圖闡釋依據本發明料製成鰭式場效電 晶體之實例性方法1〇〇。該製造 良以万去100容許自體型半導體 田日貝I成鰭式場效電晶體，並達成改良的晶圓間均句卢及 酬裝置絕緣。因此，方法100可提供以_種更加成本有 =製造製程來生產鰭式場效電晶體的優點。現在將詳細 單、万法100及在圖2-7所示製程過程中— 實施例實例。 嶺分《具體 、圖/中的第—步驟1G1係提供—適當的體型半導體晶圓。 二]^下—步驟⑽係沉積—適當的硬光罩阻擒層並隨 :=適當的硬光罩覆蓋層。該等硬光罩阻擔層與硬光 盖層皆可包括任意適當材料及任意適當厚度。舉例而 吕’孩硬光罩阻擋層可包括4〇 卜 灣苦爲 栝抓⑽㈣二氧化矽，而硬光罩 ":包括WO·11化矽。由下文可知，該硬光罩覆| ^硬光罩阻擔層將料_案化該底層半㈣基板並在^ 緣的形成過程中保護鰭片。 、巴 85802 1235457 現在參見圖2。該圖閣釋一包括一硬光罩阻撐層和一 硬光罩覆蓋層202之實例性晶圓部分·。同樣，該晶圓部 :200可包括任意通#的體料導體晶圓，例如 晶圓。同樣’硬光罩阻擋層2()4與硬光罩覆蓋層搬可包括 任意通當的硬光罩材料，例如分別為：氧切與氮化石夕。 現在參見圖卜下一步驟104將圖案化硬光罩阻擒層和硬 光罩覆蓋層以製成,鳍片圖案。本步驟可採用任—適當製程 達成，且通常會涉及-適當光阻的沉#及圖案化。爾後， 可採用-反應性離子__)針對已顯影光阻選擇性圖 案化該硬光罩阻擋層和硬光罩覆蓋層。隨後，㈣案化硬 光罩層將在一矽RIE過程中用於圖案化底層半導體基板，以 界定將用於製成鰭式場效電晶體裝置的鰭片。由此，圖案 化<長度與寬度將決定於具體應用中所需要的鰭片尺寸。 現在參見圖3，該圖闡述在硬光罩阻擋層2〇4與硬光罩覆 蓋層202已圖案化之後的晶圓部分2〇〇。 現在重新參見圖1。下一步驟1〇6係在半導體晶圓中製成 一高度控制層。然後，在下一步驟1〇8中圖案化該半導體晶 圓以使用該南度控制層製成鰭片，藉以控制鰭片高度。具 有數種不同類型的高度控制層可供使用。舉例而言，該層 可包括植入一種可將基板損壞至一所需深度並由此使受損 基板之蚀刻速率相對未受彳貝基板之姓刻速度而改變的重離 子。由此可藉由最小化|虫刻速率變化之影響而在鰭片圖案 化過程中達成改良的高度控制。或者，高度控制層可包括 在一所需丨衣度製成一標記層。在績片圖案化過程中，監測 85802 -12- 1235457 該標記層之元素，藉以猜確偵測何時達到所需鰭片高度。 因此，該兩種技術皆可達成改良的靖片高度控希;，從:能 夠自體型半導體晶圓可靠地製成鰭片。 當高度控制層包括-可損壞基板的離子植人劑時，可使 用任-種可充分損壞半導體基板暴露部分之適當離子來使 受損基板之姓刻速度相對於未受損基板之姓刻速度發生改 變。舉例而言，可使用-砷離子植入劑來損壞半導體晶圓。 其他週當離子將包括錯、鉋、銻或其他重離子。爾後，選 擇植入劑的能量以將韓片損壞至所需深度。舉例而言，若 需生成約800埃的緒片古命 θ 續片心’則可使用HO千電子伏特且劑 I*為1 X 10e16/cm2的砷拮人如 + 植入。使用適當的蝕刻時，受損部 /刀的韻刻可快於未受損部 ^ 致的蚀刻深度•之，未，疋時㈣更有可能形成- 口 未文抽邵分的蝕刻慢於受損部分， 且在疋時姓刻中可最小化夫 離子植入劑可改良所製成^ ^域中的_刻。因此， 火、、丄 叮I成鰭片的高度控制。 當該鬲度控制層包本一轳 ρ 軚圮層時，在蝕刻製程中偵測標 "己崦子即可指示何時已達 意適當物質，例如n 求？己層可包括任 植入样卞你μ, 虱或鍺。該標記層可藉由在基板中 板上沉積該等物質並隨之在所f该仏己層可猎由在基 半導體基板層而製成層之上製成一附加 刻半導體基板層的同時監標記Γ員層触刻績片。在1虫 偵剛到標記物質時：蚀；^物吳’精以界足鳍片。當 明已達到所需^刻，此乃因該等物質的出現表 85802 孩f秸記層物質的出現有助於確定何 -13- 1235457 時應停止姓刻製程，並由此生成一致的蝕刻深度。舉例而 吕，遺k s己層可為一 8 〇 〇 -1，〇 〇 〇埃厚的S i G e層，其中鍺的濃 度為 25% - 50%。 该兩種技術皆可達成改良的鰭片高度控制，從而能夠自 體型半導體晶圓可靠製成高度一致的鰭片。在所有該等具 體實施例中，蝕刻化學品皆應選擇為相容於高度控制層類 型，並應對用於界定鰭片圖案的硬光罩覆蓋層具有選擇性。 現在參見圖4。该圖闡述在已製成一高度控制層且半導體 基板已圖案化;^而製成鰭片2丨〇之後的晶圓部分2〇〇。同 樣，由於曾使用一高度控制層，因而各晶圓之間的鰭片高 度將具有改良的均勻度。 在木二狀況下，需要在該點移除覆蓋層。其可使用任一 適田技術（例如對底層硬光罩及暴露的矽具有選擇性的濕 蝕刻或乾蝕刻）來達成。底層硬光罩阻擋層得到保留，並= 用於在後績製程中保護鰭片。在其他狀況下，覆蓋層可保 留在原處，以在後續製程中進一步保護鰭片。 損壞基板的意圖為相對於鰭片 片自身氧化速度提南各緒片P』
的一種重離子較佳。 在下一步驟110中損壞各鰭片之間的基板。由下文可知， 85802 :吧偵m &板並由此提高基 為此，植入坤（以介於約j -14- l235457 X l〇e16/cm2與1 X 10e17/cm2之間的劑量及約4〇-6〇千電子伏 特之能量實施植入）為一適當選擇。其他適當植入物質包括 絶、氧及鍺。 劑可 一種選擇性地損壞半導體基板的替代方法係藉由—種對 一 P型植入劑具有選擇性的陽極反應。在此種製程中，向各 鰭片間的半導體基板中植入一種P型離子。該p型植入 包括任一適當物質，例如硼。同樣，硬光罩阻擋層可防止P 型植入劑直接損壞鰭片。在植入p型植入劑之後，對基板部 分貫施退火。爾後，將植入區域暴露於一化學蝕刻劑（例如 氫氟酸/乙醇）並發生陽極反應。由此可損壞植入區域。具體 而言，陽極反應可使植入區域變為孔隙狀。損壞程度可藉 由P型植入劑的密度和能量、氫氟酸濃度及氫氟酸/乙醇混 合物，及反應電流密度和時間來控制。同樣，受損區域具 有提高的氧化速度，由此將在基板與鰭片之間產生不同的 氧化物厚度。 現在參見圖5。該圖闡述在已移除硬光罩覆蓋層2〇2且已 實施一損壞製程以形成基板受損部分212之後的晶圓部分 200。因為鰭片受到留存的硬光罩阻擋層2〇4的保護，且植 入劑基本垂直植入，所以半導體基板的受損部分212將集中 於各鰭片之間的區域中。 重新參見圖1。在下一步驟112中氧化晶圓的受損區域。 /、可使用任適當氧化製程來實施。如上文所述，晶圓受 才貝區 < 氧化速度遠大於未受損區。因此，各鰭片之間區域 中氧化物的形成較鰭片自身上氧化物的形成更快且更深。 85802 -15- 1235457 當在 800 SsLIC 的 M # $ & 从 4、 的較佳虱化條件下維持4〇分鐘，兩種氧化 速度之比約為5:1。蕻私可六々缺α、 产的4 " 一片 < 間生成-具有足夠厚 度的乳化物，以使鰭片相互絕緣，而無需完 此外，鰭片下的氧化峰I ^ q片 虱化生長可進一步絕緣鰭片。具體而言， 下的氧化生長將達成電晶體自身源極與汲極之間的改 艮釦緣。若無此種絕緣，則電流可能會在源極與汲極之間 的鰭片之下流過’此乃因該區域可能未由電晶體閑極完全 &制。應注意：在鰭片下生長的氧化物未必需要在鰭片下 完全延伸才能提供電晶體源極與沒極之間的充分絕緣，縱 使在某些狀況下需要如此。 該步驟的另-態樣為··鰭片側壁上氧化物的生長可縮窄 4 ^上留存半導體材料之寬度。縮窄鰭片可藉由改良閘極 所實施之電流控制而改良電晶體之效能。應注意：在許多 狀況下，需要鰭片窄於使用傳統微影技術精確圖案化之寬 度。為此，在許多狀況下將需要使用側壁圖像轉移等圖像 加強技術來界定鰭片寬度。因此，本發明之具體實施例藉 由在各鰭片間形成絕緣過程中進一步縮窄鰭片寬度且無需 元全氧化掉鰭片而提供附加優點。 現在參見圖6，該圖闡述氧化作用已在各鰭片2丨〇間形成 絕緣2 1 4之後的晶圓邵分200。此外，氧化作用已在鰭片2 j 〇 側壁上形成氧化物2 1 6。由於各鳍片之間的基板區域已在氧 化之蓟受到損壞’因此各鰭片間的’氧化物生長速度遠大於 鰭片側壁等其他區域中的氧化物生長速度。另外，在鳍片 210上形成氧化物216可進一步縮窄鰭片寬度。 85802 -16- 1235457 重新參見圖i ’在下一步驟114中清除非吾人所樂見之氧 化物並製造完成鰭式場效電晶體裝置。由於形成於鰭片侧 壁上的氧化物遠薄於形成於各鳍片間的氧化物，因此既可 移除側壁上的氧化物，亦可同時在各鰭片間留存足夠的絕 緣氧化物。此外，在續片側壁上形成氧化物可進—步縮窄 靖片自身見度。 後，接下來即可製造完成 所述方法可應用於任一類 在已界定鰭片並已形成絕緣之 鰭式場效電晶體。如上文所述， 型的鰭式場效電晶體製造過程。現在將簡要闇述—膏例性 製程’但熟習此項技藝者將可知曉：亦可使用其他適當製 程0 該實例性製程的第一步驟係摻雜績片。通常，其可包括 對鰭片實施離子植人，從而製成P·井區結構和N井區結構。 在本發明之CMOS技術中’ p_井區結構和_區結構 可容許將NFET與PFET整合於—八业其4 士 正口万、公共基板中。舉例而言，
夕午、坤和銻非常適用於PF
井£，而硼、銦和鎵則非常適 用於NFET井區。論子^ 1〇nc .3S 1S離子植入通常設計達到介於例如1X m 土 5X10 cm-3之濃度。在一具體實施例中， 入可包括向半導體声吴霞的射 且將用、人τ /層暴路的對置垂直側壁實施傾斜植入， 且知用於正確摻雜鰭片。 步驟中將製成閘極堆疊。其可包括在鳍片中 直側壁和對置端壁上製成閘極絕緣 猎由熱氧化作用（通常在750 — _ >uc條件層可 者可莽由、、” 4主 、下）衣成，或 85802 儿和—介電膜製成。為本發明示例之目μ 一 ；02 4 <目的，閘極 -17- 1235457 絕緣層可為該項技藝領域中眾所周知的Si〇2、 材料、一高κ值介電材料或其組合物。 人虱 在下一步驟中製成覆蓋於閑極絕緣層上的間柯n 閉極導體層可為任意適當導電材料，通常為—多=材 料，但是非晶態石夕、-非晶態石夕與多晶石夕之組合物 石夕-錯或任意其他適當材料亦可料製成間極導體展。二 外，在本發明某些具體實施例中，使用一金屬閑柄導體芦 (例如mn或任意其他難溶金屬）或者一包括添加有錄 或銘的多⑭㈣化間極導體層可能較佳。當閉柄導^ 為一侧時’其可沉積作為-摻雜層(原位置摻雜)。當； 極導體層為-金屬層時，該等層可使用物理蒸氣或化學芙 氣沉積方法或任意其他此項技藝中眾所習知之技術來沉 積。藉由此種方式’閘極結構可眺鄰於在由半導體層部分 製成的鰭片對置垂直側壁上製成的氧化物層而製成。 在下一步驟中圖案化閘極導體層和間極絕緣層。其通常 藉由沉積並圖案化—硬光罩膜來達成。通常，硬光罩膜材 料可為二氧化矽或四氮化三矽。因此’可以採用眾所習知 之微影和蝕刻技術來圖案化並結構化閘極導體層，藉以製 成閘極堆疊，意即在閘極導體層的方向性蝕刻過程中，使 用硬光罩覆蓋膜作為蝕刻掩膜。其涉及選擇性地自上而下 移除部分閘極導體層，直至絕緣層，但並不移除形成硬光 罩膜所保護的鰭片的半導體層部分。因此，鰭片可延伸超 出閘極堆宜。圖案化和結構化製程亦留存可界定毗鄰於鳍 片本體的閘極結構的閘極導體層部分。 85802 -18- 1235457 在下一步驟中，使用源極/汲極植入劑摻雜鰭片的暴露部 分。源極/汲極區域可採用多種已開發用於製成源極/汲極區 域且適合具體效能要求的方法中任一種方法製成。具有許 多種用於製成源極/汲極區域且具有不同複雜度的方法。因 此，在本發明的某些具體實施例中，使用離子植入法例如 可製成輕度摻雜的源極/汲極區域或其他源極/汲極區域。因 此、，對於NFET，iff採用例如鱗、坤或銻料源極/沒極植 入劑j其介於1至5千電子伏特範圍内且劑量為5><1〇14至2
Xl〇15cm-3。同理，對於PFET，則通常採用例如硼、錮或鎵 作為源極/沒極植入劑，其彳於〇.5至3千電子伏特範圍内且 劑量為 5 X 1〇14至 2 X 1〇i5cm-3。 一而，5F可製成用於？文良短通道效應（SCE)的延展植乂 劑及暈圈植人劑。對於NFET，通常可使用、銦或嫁心 =植入劑’其能量範圍為5至15千電子伏特且劑量為h 至8X101W。同理，對於PFET，可使用鱗、 2晕圈植人劑，其能量為跑45千電子伏特且劑量 為 1Χ1〇13 至 8xl〇13cm-3。 里 的二 等裝置，可隨後製成至源極，和閑極 :；!因此’通常可採用-⑽製程沉積並平面化—電 85802 :::化=可广用一各向異性製程(例如RIE)或類似製程來 刻接點孔。接點孔可使用任意導電材 =雜多晶.、侧_如简)、金屬(例如金:鋁，、 材二二：。(銦錫氧化物))或類似材料，該等 、 或，、他已知之技術沉積，藉以製成S/D接 -19- 1235457 點。爾後可使用一 RIE製程或類似製程來沉積並結構化第一 金屬層。或者，第一金屬層可按照一金屬鑲嵌製程流程來 結構化。 現在參見圖7，該圖闡述位於晶圓部分2〇〇上的已製造完 畢々貝例性鰭式場效電晶體裝置。其展示一具有最低複雜 度的本發明具體實施例。閘極絕緣層220製成於鰭片210的 每一側面及鰭片的對置端壁上。閘極222製成於閘極絕緣層 220和硬光罩膜224之上。在該特定具體實施例中，閘極導 體層222部分亦連續跨過鰭片的兩側，而在其他具體實施例 中’該閘極導體層分為兩部分。 位於同一基板上且使用不同晶體平面作為FET電流通道 的本發明CMOS鰭式場效電晶體可用於許多不同種類的電 路中，例如高效能邏輯電路、低功率邏輯電路或高密度記 匕衣置’包括咼密度數十億位元級DRAM。此外，CMOS 、、、曰式悬放私日曰體可方便地組合其他元件，例如電容器、電 阻斋、二極體、記憶單元等等。 本發明由此提供一種裝置結構及已克服先前技術眾多缺 點的鰭式場效電晶體（FET)製成方法。具體而言，該方法有 利方、自心型半導體晶圓製成鰭式場效電晶體裝置，並可改 L鳍片高度控制。此外，該方法提供自體型石夕製成鰭式場 效電晶體的能力，同時提供各鰭片之間及單個鰭式場效電 •晶體之源極區域與汲極區域間的絕緣。本發明之裝置結2 及万法由此提供使用成本有效的體型晶圓達 、一 的蜻式場效電晶體製造之優點。本文所提及之且髀备浐
85802 -20. ^ -貝她歹J 1235457 和實例用於最佳地解釋本發明及其實際應用，並進而 熟習此項技藝者皆可實施和使用本發明。然而，凡孰習此 項技蟄者即知，上文之說明及示例僅用於闊釋和示例之目 的^作說明並非意欲作為窮盡性說明或將本發明限制為 所揭示的精確形式。根據上二 、、、 、 上又祝明，可作出眾多修改和變 化，、並未月離以下申請專利範圍之精神及範田壽。因此， 除另有說明外，附圖或本文所述的本發明任何元 能元件的一實例形式而非—限定形式給出。 說明外，本文所述本發明 除另有 的任何步驟或步驟順序皆以 a或步驟順序的實例形式而非㈣形式給出。 【圖式簡單說明】 上文結合附圖闡述本發 士…^明《較佳實例性具體實施例，其 中相同標識表示相同的元件，且 /、 圖1為—_本發明—製造方法之流程圖； 構Γ:在圖1所示製造方法過程中，本發明-半導體結 構<一具體實施例之剖面側視圖。 【圖式代表符號說明】 85802 100 用於製成鰭式場效電 法 101 提供體型半導體晶圓 102 沉積硬光罩阻擋層， 104 圖案化硬光罩阻擋層 片圖案 106 在半導體晶圓中製成1 -21 - 1235457 108 110 112 114 200 202 204 210 212 214 216 220 222 224 使用高度控制層圖案化半導 片，藉以控制鰭片高度 損壞各鰭片之間的晶圓 氧化晶圓 移除非吾人所樂見之氧化物： 場效電晶體裝置 一實例性晶圓部分 硬光罩覆蓋層 硬光罩阻擋層 鰭片 基板受損部分 絕緣 氧化物 閘極絕緣層 閘極 硬光罩膜 體晶圓以製成鰭 並製造完成鰭式 85802 -22

Claims (1)

1235457 拾、申請專利範圍： 1 . 一種用於在半導體基板中製成一鰭式場效電晶體之方 法，該方法包括下列步驟： 自遠半導骨豆基板製成一鰭片；及 對該基板實施一可進一步界定該鰭片寬度且同時絕緣 該鰭片的製程。 2.根據申請專利範圍第1項之方法，其中，，對該基板實施一 可進一步界定該鰭片寬度且同時絕緣該鰭片的製程，，之 步騾包括： 損壞鄰接該鰭片的半導體基板區域之至少一部分；及 氧化該半導體基板，使形成於該半導體基板受損部分 中的氧化物厚於形成於一鰭片侧壁上的氧化物。 3. 根據申請專利範圍第2項之方法，其中”損壞鄰接該鰭片 的半導體基板之至少—部分”之步驟包括：向鄰接該績片 的半導體基板之至少一部分實施一離子植入。 4. 根據申請專利範圍第3項之方法，其中該離子植入包括： 實質上平行於該，鳍片實施—植人，以最小化對該緒片倒 壁的損壞。 5·根據中請專利範圍第3項之方法，其進—步包括在該韓片 《頂# &供-阻擒層以減小對該鳍片的損壞之步驟。 6.根據申請專利範圍第2 |、丄 ... 靶图弟2員〈万法，其中”損壞鄰接該鳍片 的半導體基板之至少一邱八π、 、、^秕I 土 y 口15刀〈步驟包括··實施一陽極反 應以提鬲鄰接該鰭片的半導、 丁寸基板又至少一邵分的孔隙 度。 85802 1235457 7·根據申請專利範圍第6項之方法，其中"實施一陽極反應 以提高鄰接該鰭片的半導體基板之至少一部分的孔隙度 "之步騍包括·對毗鄰該鰭片的半導體基板實施一 ρ型植 入，使該半導體基板退火，並使半導體基板之至少一部 分接受一化學i虫刻劑作用。 8.根據申4專利範圍第i項之方法，其中"自該半導體基板 製成一鰭片"之步驟包括： 在該半導體基板中製成—高度控制層；及 蝕刻孩半導體基板以界定該鰭片，從而使該高度控制 層有利於達成鰭片高度均勻度。 9.根據申請專利範圍第8項之方法，在該半導體基板 中製成-南度控制層，，之步驟包括：對該半導體基板實施 -可損壞該基板之離子植人，藉以使該基板受損部分之 蝕刻速度相對於該基板未受損部分發生改變。 1〇·根據申請專利範圍第8項之方法，其巾，，在該半導體基板 中製成-高度控制層”之步驟包括：在該半導體基板中製 成-標記層，且其中”蚀刻該半導體基板以界定該績片， 從而使該高度控制層有利於達成鳍片高度均句度，，之步 驟包括··在該半導體基板蚀刻過程中監測該標記層。 11,根據申請專利範圍第丄項之方法，其中,,對該基板實施— 可進-步界疋孩，鰭片寬度且同時絕緣該績片的製程”之 步驟可將該鰭片寬度縮窄至小於—用於”自該半導體基 板製成一鰭片，，之步驟的製程的最小形體尺寸。 其中f’對該基板實施一 12.根據申請專利範圍第1項之方法， 85802 -2- 1235457 可進一步界定該鳍片寬度且同時絕緣該鳍片的製程，，之 步驟可將該鰭片寬度縮窄至小於―料”自該半導體基 板製成一鰭片”之步驟的製程的最小形體尺寸。 1 3 _種在半導體基板中製成一鰭式場效電晶體之方法，該 方法包括下列步驟： 自蒸半導體基板製成一包括一鰭片側壁的鰭片，該鰭 片的製成使毗鄰於該鰭片的該半導體基板區域暴露出 來； 損壞鄰接該鰭片的半導體基板區域之至少一部分；及 氧化孩半導體基板，使形成於該半導體基板受損部分 中的氧化物厚於形成於該鰭片側壁上的氧化物。 Μ·根據申請專利範圍第13項之方法，其中，，損壞鄰接該鰭片 的半導體基板之至少一部分”之步驟包括：對鄰接該鰭片 的半導體基板之該至少一部分實施一離子植入。 1 5·根據申請專利範圍第13項之方法，其中，，損壞鄰接該鰭片 的半導體基板之至少一部分”之步驟包括：實施一陽極反 應’以提高鄰接該鰭片的半導體基板之至少一部分之孔 隙度。 16.根據申請專利範圍第15項之方法，其中，，實施一陽極反 應’以提高鄰接該鰭片的半導體基板之至少一部分之孔 隙度’’之步驟包括··對鄰接該鰭片的半導體基板實施一 p 型植入，使該半導體基板退火，並使該半導體基板之至 少一部分接受一化學蝕刻劑作用。 17·根據申請專利範圍第13項之方法，其中”自該半導體基板 85802 1235457 製成一鰭片”之步驟包括： 在該半導體基板中製成一高度控制層；及 蝕刻該半導體基板以界定該鰭片，從而使該高度控制 層有利於達成鰭片高度均勾度。 1 8 ·根據申請專利範圍第17項之方法，其中”在該半導體基板 中製成一高度控制層”之步驟包括：對該半導體基板實施 一可損壞該基板之離子植入，藉以使基板受損部分之蝕 刻速度相對於基板未受損部分發生改變。 19·根據申請專利範圍第π項之方法，其中，，在該半導體基板 中製成一高度控制層”之步驟包括：在該半導體基板中製 成一標1己層，且其中”蝕刻該半導體基板以界定該鰭片， 從而使該高度控制層有利於達成鳍片高度均勻度，，之步 騾包括·在蝕刻該半導體基板過程中監測該標記層。 20· —種自一體型半導體基板製成鰭式場效電晶體裝置之方 法，該方法包括下列步驟： 在該半導體基板中製成一高度控制層； 在遠半導體基板上製成一阻擔硬光罩層； 蝕刻該阻擋硬光罩層及半導體基板，以界定複數個鰭 片，從而使？豕高度控制層有利於達成鰭片高度均勻度， 其中該阻擋硬光罩層的-部分留存^該複數個鰭片的每 一鰭片上，且其中該複數個鰭片中的每一鳍片皆包括一 側壁’且其中㈣該半導體基板可暴露出，該績片的 半導體基板區域； 損壞鄰接該鰭片的半導體基板區域之至少—部八· 85802 -4- 1235457 氧化該半導體基板，從而使形成於該半導體基板受損 部分中的氧化物厚於形成於該鰭片侧壁上的氧化物；及 自該鰭片側壁移除氧化物，同時留存鄰接該鰭片的氧 化物之至少一部分。 85802
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US6642090B1 (en) 2003-11-04
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WO2003103019A2 (en) 2003-12-11
CN1653608A (zh) 2005-08-10
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JP2005528793A (ja) 2005-09-22
WO2003103019A3 (en) 2004-03-18
ATE500610T1 (de) 2011-03-15
AU2003237320A1 (en) 2003-12-19
KR20050003401A (ko) 2005-01-10
KR100702553B1 (ko) 2007-04-04
CN1296991C (zh) 2007-01-24
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