TW587336B - Germanium field effect transistor and method of fabricating the same - Google Patents

Germanium field effect transistor and method of fabricating the same Download PDF

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TW587336B
TW587336B TW092107386A TW92107386A TW587336B TW 587336 B TW587336 B TW 587336B TW 092107386 A TW092107386 A TW 092107386A TW 92107386 A TW92107386 A TW 92107386A TW 587336 B TW587336 B TW 587336B
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TW200306008A (en
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Massimo V Fischetti
Steven E Laux
Paul M Solomon
Hon-Sum Philip Wong
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Description

587336 玖、發明說明： 【發明所屬之技術領域】 本發明一般係關於在相同晶圓上製造一 η型通道場效電晶 體（n-channel field effect transistor; nFET)及一ρ型通道場 效電晶體（p-channel Held effect transistor; pFET)，使每個 裝置的載子傳輸最佳化。具體而言，在一鍺層上，在（lu) 表面，沿<110>方向製造一 n型通道FET，在（1〇〇)表面，沿 <110〉方向製造一 ρ型通道FET。 【先前技術】 載子傳輸在鍺場效電晶體（Ge FET)中相對於在矽場效電 晶體中是已知的。因此，先前技術認為鍺提供的電子遷移 率遠遠大於矽。此外，先前技術通常將nFE 丁及pFE 丁組合在 一互補金氧半導體電路（c〇mplementary metal 〇xide semiconductor ; CM0S)之單一晶圓上。然而，先前技術未 能根據載子遷移率的特性將該等互補裝置之結構及定向最 佳化。 【發明内容】 本發明者不但已經理解在鍺中載子遷移率高於在矽中， 而且也理解’為最大限度利用載子傳輸，有必要選擇適當 的晶體定向及載子億給+ A 40- '/v ” 丁傅輸万向。對於包含兩種載子的CMOS， 该理解更為重要。目此，本發明認為，一電路的每個裝置 有、/裝置〈載子類型為基礎的一較佳晶體定向及方 =-項範例性具體實施例係— nFET，具有— 晶 體表面形成的㈣。本發明額外提供—種在相同晶片上製 84143 造兩個裝置之方法，其中每個裝置包含一不同載子類型， /、在 日日眼表面具有取佳載子遷移率。一項範例性具體實 施例係在鍺上兼有n型通道及卩型通道FET，其採用各自較佳 的晶體定向。 圖1顯示石夕及鍺反轉層電子遷移率在包括及不包括介面輪 度散射的計算比較結果，該電子遷移率與電子片密度呈函 數關係。如曲線1所示，一鍺反轉層（111)表面電子遷移率明 顯大於鍺（1〇〇)表面（曲線2)及矽（1〇〇)表面（曲線3)。此等三 條曲線中的空心符號代表無表面糙度，而對應於曲線4、5 及6中的實心符號代表有表面縫度。 具體而言，在鍺中，在（111)晶體表面及沿<11〇>方向，η 型通道FET載子傳輸較快，而在（1〇〇)晶體表面及沿<11〇>方 向，ρ型通道FET載子傳輸較快。發明者已經認識到，遵循 該指導方針，根據晶體方向為每個裝置選擇一裝置結構， 並將該裝置定向於<110>方向，藉此可使η型通道FE 丁及ρ型 通道FET在鍺中的載子傳輸最佳化。 因此，本發明的一目的係提供一種用以在（m)表面，沿 <110〉方向製造一 η型通道FET的結構及方法。 本發明另一目的係提供一種在相同晶圓上製造具有第一 類型載子的一第一裝置以及具有第二類型載子的一第二裝 置之結構及方法，其中第一類型載子的載子遷移率沿（ιιι) 晶體定向更高，第二類型載子的載子遷移率沿（1〇〇)晶體定 向更高。 一特定具體實施 本發明又一目的係提供此方法及結構的 84143 587336 例’以便使用鍺作為下層，在相同晶片上形成一η型通道PM 及一 P型通道FET。 本發明另-目的是揭示在鍺金屬氧化物半導體場效電晶 體中m〇sfet)，或任何在（⑴）及陶表面具有不同傳 輸特性的金屬氧化半導體場.效電晶體中獲得nFET& _丁最 佳傳輸特性的方法。 為達到上述及其他目@ ’本發明之—第一方面係說明一 :電子晶片的製造方法以及結構，該電子晶片包括具有一 :-類型載子的一第一裝置’該第一裝置形成在—載子遷 移率表面大於在（⑽）表面的材料之⑴叫體表面 上4第方面之一項較佳具體實施例係在鍺的（丨i丨）表面 沿<110>方向製造的η型通道fet。 本發明一第二方面係說明一種電子晶片的製造方法以及 結構，該電子晶片包括具有一第一類型載子的一第一裝置， 該第-裝置形成在一種材料之（111)晶體表面内，該材料的 載子遷移率在（111)表面大於在（⑽）表面，ϋ包括具有一第 二類型載子的一第二裝置，，第二裝置形成在一種材料之 (100)晶體表面内，該材料之第二載子類型的載子遷移率在 (100)表面大於在（111)表面。該第二方面之一項較佳具體實 施例包括一在（π 1)表面沿 < 丨丨〇>方向的η型通道FET以及一 在（1 〇〇)表面沿<Π 0>方向的p型通道feT，其中二裝置都开< 成於同一錯層内。 【實施方式】 參照附圖，特別是圖1，藉由將曲線！與曲線2、3及6比較， 84143 587336
Ge反轉層在（111)表面上的電子遷移率明顯大於以或以反轉 層的（10G)表面。透過嚴格的裝置模擬及分析，本發明者输 製了該圖並從而決定’當n型通道FET電流傳輸係在⑴〇晶 體表面沿<ιιο>方向’以及p型通道FET電流傳輸係在⑽） 晶體表面沿<ιιο>方向時，鍺場效電晶體（Ge fet)具有較高 的電流驅動力。 圖2顯示由計算值繪製出的汲極電流對汲極-源極電壓曲 線20，用以說明在（100)表面上25nm通道長度以底材n型 MOSFET (曲線21)，以及在⑴υ表面上類似的以裝置（曲線φ 22) 。 Ge裝置呈現明顯較大的電流及跨導 (transconductance) 〇 因此，為最大限度利用載子傳輸，不僅有必要選擇材料， 也要選擇適當的晶體定向及載子傳輸方向。本發明揭示選 擇一較佳的晶體定向及方向以使載子傳輸最佳化。 由於晶圓只是沿一個主要晶體方向從鑄錠上切下，因此 通常難以在相同晶圓上製造不同晶體定向之FET。因此，本 發明也揭示一種在相同晶圓上製造η型通道及p型通道_ FET的方法’該方法使用不同的FET結構，其具有使各載子 遷移率最佳化之晶體平面及方向。 使用石夕（Si)當作具有（111)結構的閘通道iFET組態已為吾 人所熟知。圖3顯示一實例，如sah〇等人在「三角平行線通 道M0SFET中短通道效應的抑制」（IEEE矽奈米電子學研究 講習會，第6至7頁，曰本東京，2〇〇1年6月1〇至u 日）（Suppression of Short Channel Effect in Triangular 84143
Parallel Wire Channel MOSFETs 」（IEEE Silicon Nanoelectronics Workshop,pp.6-7, Kyoto，Japan, June 10-11，2001))中所述，其具有一形成於矽上之埋入氧化物 (BOX)32上面，並包括三角平行線通道31的MOSFET結構 30。該三角平行線通道31係藉由用四甲基氫氧化銨（TMAH) 進行各向異性蝕刻而獲得。所形成之矽（111)平面隨後藉由 具有一氧化層及閘電極的閘結構32所覆蓋。用於線通道的 相同矽層也用於源極33及汲極34的形成。 在「短通道效應」抑制技術中同樣為吾人所熟知的是： 以矽為基礎、自行對準雙閘極MOSFET結構，稱為FinFET(鰭 式場效電晶體）。圖4係FinFET40之一縱向斷面圖，Huang等 人在「50 nm 以下 FinFET ： PMOS」（Sub50- nm FinFET:PMOS)(IEEE國際電子裝置會議（IEDM)，第67至70 頁，1999 年）(IEEE International Electron Devices Meeting (IEDM)，pp.67-70，1999)對其進行了論述。使用多晶矽鍺 (poly-SiGe)，在埋入氧化（BOX)層43(在矽晶圓44上）與藉由 矽氧化層46所覆蓋之矽鰭片45上製造源極41及汲極42。由 SiGe所構成之氮化物間隔層（Nitride spacer)47及閘極48完成 FinFET結構，其可使短通道結構短到17nm，並可能將閘極 長度減小到1 〇nm。 超薄矽鰭片45用於抑制短通道效應。氮化物間隔層47之 間的兩個間隔定義該通道*度。由多晶矽鍺所構成的昇起 式源極（raised source)4 1及汲極42降低了寄生電阻。
圖5顯示該基於矽的FinFET之一可能製造順序。在步驟A 84143 -10- 中，將厚度為50nm — Si層51沈積到一 S0I晶圓Β〇χ層5〇之 上，隨後係厚度為10〇1^的一 Si〇#52。在步驟B中，將矽 層51蝕刻以形成氧化物覆蓋的鰭片結構，使用電子束微影 去蝕刻Si〇252層以形成一硬光罩，以在蝕刻矽時形成鰭片 結構。在步驟c中，將一 300nm厚低溫氧化物（LT〇)沈積在 200nm厚p+多晶矽鍺層上，在步驟D中，將此二層“及” 進订蝕刻，首先藉由蝕刻LT〇層使其成為一光罩，以在該多 晶矽鍺層反應離子蝕刻時形成源極56及汲極57。該氮化物 間隔層58係在步驟e中藉由1〇〇nm氮化層之沈積而形成，隨 後對之進行蝕刻。間隔層間之間隙通常小於2〇nm。 為形成步驟F中的閘結構59，首先生長一 1511〇1厚犧牲氧 化層’然後對其實施濕式蝕刻，W除去在先前鰭片側面的 一乾式蝕刻時造成的損害。該步驟進一步降低該鰭片的厚 度，使孩鰭片之最終厚度範圍為15至3〇11111。在75〇<>c下，一 2.5nm閘極氧化物生長於該鰭片側面，與一額外的退火步驟 結合的該「高溫」步驟將硼從該SiGe昇起式源極/汲極區域 驅入到該氮化物間隔層下面的鰭片中，以形成对源極/沒極 延伸部分。在沈積20〇nm原處摻雜以(}6(6〇%(^，其功函數 為4.75eV)作為閘極材料後，將該電極圖案化並加以蝕刻。 藉由此等先前技術實例說明該等技術，其中為一裝置之 一特疋組件製備一特足晶體平面，如（丨丨丨），並將一適當先 則技術與圖1及結論結合，使用鍺作為材料、fet通道作 為特定裝置組件來說明兩項範例性較佳具體實施例。 第一項範例性具體實施例包括藉由圖6所述之方法6〇。在 84143 -11 - 587336 第61步’將一鍺（Ge)材料確定為一材料，在其（ιη)晶體平 面内一 η型通道FEt具有一最佳載子遷移率，及在（1〇〇)晶體 平面内，一ρ型通道FE 丁具有一最佳載子遷移率。兩種類型 載子之最佳載子遷移方向均為<11 〇>方向。 因此’為說明本發明之第一項範例性具體實施例，特設 计最佳鍺n型通道FET。由於發生在一 FET中的相關活動 都^生在違通道中’因此本發明之相關組件包括該MET通 這，本發明揭示其在（111)平面具有一最佳載子遷移率。因 此，第63步及第64步揭示，GenFET之閘極及通道應在（I") φ 表面上製備。其餘nFE丁組件（如源極與汲極）的製造較為簡 早，但取決於所選擇的特定nFET結構。因此，在步驟63之 則所製備 < 孩等特定裝置組件及在步驟64之後所製備之該 寺特疋裝置組件取決於該裝置結構，可能之實例為圖3所示 之平行線結構或圖4所示之。 由於最佳載子遷移發生在<110>方向’因此要將通道定向 =將源極及沒極定位，對熟知技術人士此乃易事。亦應注 意’熟悉技術人士很容易明白第63步及第64步可以在順序鲁 上^開’以在此等兩步中間製造一或多個裝置組件。熟悉 技咖人士亦應理解，該鍺材料可能是一基板、或可能是加 到一石夕晶圓之上的一層、或加到一絕緣層之上的-層，如 在一石夕晶圓之上的氧切、或提供鍺作為—晶圓上之一層 或-區域的任何其他方法一錯層之最小厚度要使咖了（^) 平面表面足以獲得四角錐形晶體結構。 本發明之-第二項範例性具體實施例係圖7所示的方法 84143 -12- 587336 70。在此項具體實施例中，將具有各自不同類型載子的二 不同裝置製造在同一晶片上，以根據個別載子特性使每個 裝置最佳化。如上述第一項具體實施例中所述，此非限制 性實例包括一 riFE 丁及一pFET，其使用與第7;[步中所確定之 相同鍺材料。由於使用（111)平面才能獲得最佳nFET通道及 使用（100)平面才能獲得最佳pFET通道，因此第73A、74A、 73B及74B步包括使用一（111)蝕刻劑在一鍺材料一第一區域 製備該nFET及使用一蝕刻劑在該鍺材料之一第二區域製備 一（100)平面用於該pFET。 鲁 應明白’該第一及第二區域的製備可以以任何順序實施， 且该製備的某些步驟可以共用。此外，與上面第一範例性 具體實施例類似，該nFET及PFET裝置可以具有任何一種為 吾人所熟知的基本結構。此二裝置可使用相同的基本結構， 只是通道製備不同，或此二裝置可具有不同的基本結構。 如上所述，該鍺可以為一層，其具有足以在nFET(丨11)平面 表面獲得四角錐形晶體結構的最小厚度。或者，該鍺材料 可此疋一晶圓基板、或可能是加到一矽晶圓上的一鍺層、籲 或加到一絕緣層之上的一鍺層，如在一矽晶圓之上的氧化 矽或提供鍺作為一晶圓上之一層或一區域的任何其他方
法。同樣如上所述，步驟72A、72B、74A、74B、75A及75B 中的特定組件製造將根據該裝置結構而變化，如上所述， 邊通迢及其餘裝置組件之定向要滿足兩種載子1…較佳載 子方向之要求。 圖8為通逍nFET8 1及一通道pFET82的示範性斷面圖 84143 -13- 587336 8〇此兩通迢形成於同一晶片83上及在同一埋入氧化層 (B〇X)84上製造。源極及汲極未顯示，但圖3及4中所示的裝 置佈局可用以說明：源極及汲極可以定位於該圖8斷面圖的 支面或納面。忒通道以由一閘極絕緣體8 6，如氧化石夕及閘 電極87所t蓋。肖閘極i緣體及閘電極之製造為吾人所熟 知。應明白，該圖說明上述第二項範例性具體實施例，藉 由研艽與PFET82相間隔層的nFET81，也說明了第一範例性 具體實施例。 圖9顯示Ge層92 nFET區域之（ill)晶體製備90。有一硬光 _ 罩91位於與<ιι〇>方向相適應的nFET通道區域之上。為獲 得該（1 11)平面之棱鏡結構94，使用一範例性酸性化學配方 (H3P〇4:H202:C2H5〇H，比例：1:1:1，或 HF:H202:H20， 比例：17:17:66)(如Lang等人在微機械微工程雜誌（j,
Micromech. Microeng. ν〇1·6，ρρ·46-48，1996·)6卷 46至 48 頁刊 登的「用於紅外光柵製造的鍺整體微細加工」（Bulk micromachining of Ge for IR gratings)中所述）實施鍺各向異 性蚀刻93)。前者最好係使用一絡硬光罩。 _ 在該nFET右側顯示的區域95可以以另一方式製備，如在 一 pFET之Ge(100)平面，使用標準垂直蝕刻方法，如圖8之 右側所示。 只要該nFET是基於四棱鏡結構及該pFE丁是以該平面表面 為基礎，如在圖8之斷面圖所示，可以使用任何已知方法完 成該nFET及pFET結構，本發明之該較佳具體實施例中二通 道結構的定位使nFET及pFET之載子移動都發生在<11〇>方 84143 -14- 587336 向0 根據上面所述可以清楚看到，本發明—主要優點為，益 論在GeM〇SFET或在任何在⑴丨）及⑽）表面具有不同傳輸 特性的Μ0贿中，鑛及_裝置都能獲得最佳載子傳 輸特性。 雖然本發明僅就一單一較佳具體實施例加以說明，但是 熟悉技術人士應明白，本發明可在隨附申請專利範圍的精 神及範疇内進行修改。 【圖式簡單說明】 攸本發明較佳具體貫例的上述詳細說明並參考圖式，即 可更加瞭解上述及其它目的、觀點及優點，其中·· 圖1顯示矽及鍺反轉層電子遷移率的計算比較結果，該電 子遷移率與電子片密度成函數關係； 圖2顯示由計算值繪製出的汲極電流對汲極-源極電壓曲 線’用以說明在（100)表面上之矽底材η型MOSFET，以及在 (111)表面上類似的Ge裝置·； 圖3顯示一在SOI基板上，具有三角平行線通道的MOSFET 結構’如在先前技術中所述； 圖4顯示該FinFET結構之一縱向斷面圖，如在先前技術中 所述； 圖5顯示圖4中所示之一 FinFET製造範例； 圖6顯π本發明一範例性弟'一具體貫施例之一範例性方 法； 圖7顯示本發明一範例性第二具體實施例之一範例性方 84143 -15- 587336 法； 圖8顯示根據本發明製造的π範例性#£ 丁及pFET之一橫 向斷面圖；以及 圖9顯示一範例性鍺材料之（1丨丨）平面的一範例性製備方 法0 【圖式代表符號說明】 30 MOSFET 結構 3 1 三角平行線通道 32 埋入氧化物 33 源極 3 4 汲極 41 源極 42 沒極 43 埋入氧化層 44 矽晶圓 45 矽鳍片 46 氧化層 47 氮化物間隔層 48 閘極 50 埋入氧化層 51 Si 層
52 SiOJ 54 低溫氧化物 55 P+多晶矽鍺層 84143 • 16 - 源極 汲極 氮化物間隔層 閘結構 N型通道場效電晶體 P型通道場效電晶體 晶片 共用埋入氧化層 通道 閘絕緣體 閘電極 晶體製備 硬光罩 Ge層 棱鏡結構 17-

Claims (1)

  1. 587336 拾、申請專利範圍： 1· 一種至少具有一層材料之電 子類型在-第-晶触矣“ 層材料的一第—載 在罘日曰岐表面内的載子遷移率大於在一# 體表面内的載子遷移率， 罘一晶 表面内的-載子遷移率大於 吊… 移率，該電子晶片包括： 心表面内的載子遷 弟-裝置’其至少具有形成於該材料之該第触 表面上之一組件，其中該第_ T ^裝置 < 琢至少'组件的 動王要涉及該第一載子類型；以及 / 一第二裝置， 表面上之一組件 動主要涉及該第
    其至少具有形成於該材料之該第二晶體 ’其中該第二裝置之該至少—組件的―： 二載子類型。 電子晶片，其中該第一晶體表面 而該第二晶體表面則包括一（丨00) 2·如申請專利範圍第丨項之 包括一（111)晶體表面， 表面。 3. 如申請專利範圍第2嗔之電子晶片，其中該材料包括錯。
    4. 如申請專利範圍第2項之電子晶片，其中該第—裝置包括 1型通道而(場效電晶體），而該第：裝置包括—^通 道FET ’ JL 1¾至少一組件包括該等FET之一通道。 5’如申請專利範圍第4項之電子晶片’其中該n型通道印丁及 孩Ρ型通道FET之至少—個的該通道與一 <11〇>方向對齊。 6. 如申請專利範圍第4项之電子晶片，其中該第—裝置及該 第二裝置之至少一個包括一 FinFET結構。 7. 如申請專利範圍第4項之電子晶片，其中該材料包括鍺。 84143 8·—種電子晶片，其包括： —、弟—裝置’其至少具有—層材料，該層材料的-第 —載子類型在一第一晶體表面内 # 载子遷移率大於在一 ^晶體表面内的載子遷移率’且該層材料的-第二載子 2型在孩第二晶體表面内的—載子遷移率大於在該第—晶 體表面内的載子遷移率，嗜筐世罢^ 、 、夕手落罘一裝置至少具有由該材料之 琢第-晶體表面形成之一組件，該至少一組件的一活動主 要涉及該第-載子類型，其中該第一晶體表面包括一⑴” 晶體表面’而該第二晶體表面則包括—(100)表面。 9.如申請專利範圍第8項之電子晶片，其中該材料包括鍺。 10·如申請專利範圍第9項之電子晶片，其中該第一裝置包括 — η型通道FET (場效電晶體），且該至少一組件包括該η型 通道FET之一通道。 .如申請專利範圍第10項之電子晶片，其中該11型通道邱丁 之該通道與一 <11 〇>方向對齊。 12·如申請專利範圍第1〇項之電子晶片，其中該η型通道吓丁 之一結構包括一 FinFET結構。 13·如申請專利範圍第8項之電子晶片，其進一步包括： 一第二裝置，其至少具有一層該材料，該第二裝置至 少具有一由該材料之該第二晶體表面形成之一組件，該第 —裝置之該至少一組件的—活動主要涉及該第二載子類 型。 14.如申請專利範圍第13項之電子晶片，其中該第二裝置包 括一 p型通道FET。 84143 587336 15:如：請±專利範園第14項之電子晶片，其中該第-裝置及 μ第I置之土少一個的一結構包括一FinFET結構。 16•如申請專利範圍第13項之電子晶片，其中該材料包括錯。 17·-種在-晶圓上製造一第—裝置及一第二裝置的方法， 該第:裝置具有—第一類型的一載子，而該第二裝置則具 有-第二類型的一載子，該第一類型載子在一⑴”晶體 表面的載子遷移率大於在_ (1〇〇)晶體表面的載子遷移 率，該帛二類型載子在該⑽）晶體表面的載子遷移率大 於在该（1 1 1 )晶體表面的載子遷移率，該方法包括： 提供一層材料，其具有一特性，即該第一類型載子在 一⑴1)晶體表面的-載子遷移率大於在 的載子遷移率，還具有一特性，即該第二類型載子在二 晶體表面的-載子遷移率大於在該⑴”晶體表面的載子 遷移率； 使用一（111)蝕刻劑在該層之一第一區域蝕刻，以提供 該第一裝置之至少一組件；以及 使用一蝕刻劑在該層之一第二區域蝕刻，以提供該第 二裝置之至少一組件的該（100)晶體表面。 18.如申請專利範圍第17項之方法，其中該材料包含鍺。 19·如申請專利範圍第17項之方法，其中該第一裝置包括一打 型通适FET(場效電晶體），且該第二裝置包括一 ρ型通道 FET，且該至少一組件包括該等FET之一通道。 20.如申請專利範圍第丨7項之方法，其進一步包括： 將該第一裝置之該至少一組件及該第二裝置之該至少 一組件中至少一個的一載子方向與一 <11〇>方向對齊Λ。 ’ 84143
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