CN100375291C - 电子芯片及其制造方法 - Google Patents

电子芯片及其制造方法 Download PDF

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CN100375291C
CN100375291C CNB038062151A CN03806215A CN100375291C CN 100375291 C CN100375291 C CN 100375291C CN B038062151 A CNB038062151 A CN B038062151A CN 03806215 A CN03806215 A CN 03806215A CN 100375291 C CN100375291 C CN 100375291C
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crystal face
carrier
effect transistor
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electronic chip
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CN1643694A (zh
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马西莫·菲谢帝
波·所罗门
宏萨姆·菲力普·王
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

一种用于电子芯片的方法(和结构)，该芯片具有至少一层材料，对于所述材料来说，第一载流子类型的载流子迁移率在第一晶面上高于在第二晶面上，且第二载流子类型的载流子迁移率在第二晶面上高于在第二晶面上，包括具有至少一个在所述材料的所述第一晶面上制造的部件，和具有至少一个在所述材料的第二晶面上制造的第二器件，其特征在于所述第一器件的所述部件的活性主要涉及第一载流子类型，所述第二器件的所述部件的活性主要涉及第二载流子类型。

Description

电子芯片及其制造方法
技术领域
本发明涉及以优化每一器件的载流子传输方式而在同一晶片上制造n沟道场效应晶体管(FET)和p沟道FET。
背景技术
锗场效应晶体管(Ge FET)中的载流子传输已知相对于硅场效应晶体管得到增强。因此，现有技术认识到，与硅相比，锗具有更好的电子迁移率。此外，现有技术通常将n-FET和p-FET组合在用于CMOS电路的一个晶片上。然而，现有技术中缺乏的是基于载流子迁移率特性对互补器件结构和方位的优化。
而且，现有技术就载流子迁移率论述了晶体取向。例如，在本领域的现有技术中，包括尼桑汽车有限公司的US5317175，它公开了在(011)取向的半导体上形成P沟道MOSFET和N沟道MOSFET，以所述P沟道MOSFET的沟道垂直于N沟道MOSFET的沟道的方式。Forbes等的US2001/0026006公开了一种具有侧面的结构，该侧面具有(110)晶面，而使这种结构的电流沿<110>方向传导。USA的US4119996由国家航空和航天管理局提出，公开了一种在一个半导体衬底上形成的高速CMOS，包括具有非对称沟道的DMOS和具有较短沟道长度的VMOS。US42259879公开了一种V-MOS场效应晶体管，该晶体管具有增强的源极电容，而提供一个晶体管动态存储单元。US4233617公开了一种V-MOST型场效应晶体管，其中沟道区域包含邻接源区的更高掺杂的部分，和围绕所述区域的较低掺杂部分，所述沟道邻接所述表面且通过绝缘扩散被围绕。然而，现有技术中缺乏的是基于载流子迁移率特性对互补器件结构和方位的优化。
发明内容
本发明人已经发现，不仅在锗中相对于硅来说载流子迁移率较高，而且还发现为了使载流子迁移率的益处最大化，必须选择适当的发生载流子传输的晶体取向和方向。对于包含两种载流子类型的CMOS来说，这种认识变得更为重要。
因此，根据本发明的第一方面，提供了一种电子芯片，具有至少一层材料，对于所述材料来说，第一载流子类型的载流子迁移率在第一晶面上高于在第二晶面上，第二载流子类型的载流子迁移率在所述第二晶面上高于所述第一晶面上，所述电子芯片包含：第一器件，具有至少一个在所述材料的所述第一晶面上制造的部件，其中所述第一器件的所述至少一个部件的活性主要涉及所述第一载流子类型，第二器件，具有至少一个在所述材料的所述第二晶面上制造的部件，其中所述第二器件的所述至少一个部件的活性主要涉及所述第二载流子类型。
根据本发明的第二方面，提供了一种在晶片上制造具有第一类型载流子的第一器件和具有第二类型载流子的第二器件的方法，所述第一类型载流子在晶面上具有比在晶面上高的载流子迁移率，所述第二类型载流子在晶面上具有比在晶面上高的载流子迁移率，所述方法包含：提供一层材料，所述材料具有所述第一类型载流子的载流子迁移率在晶面上比在晶面上高的特性，以及所述第二类型载流子的载流子迁移率在所述晶面上比在所述晶面上高的特性；用蚀刻剂蚀刻所述层的第一区域，使所述晶面用于所述第一器件的至少一个部件；使用蚀刻剂蚀刻所述层的第二区域，使所述晶面用于所述第二器件的至少一个部件。
因此，本发明还提供了一种在同一芯片上制造两个器件的方法，其中每一器件包含具有最佳载流子迁移率的晶面的不同载流子类型。示例性实施例提供了在锗上的n沟道和p沟道FET，且使用各自优选的晶体取向。
根据本发明的第三方面，提供了一种电子芯片，该芯片具有至少一层材料，对于所述材料来说第一载流子类型的载流子迁移率在第一晶面上高于在第二晶面上，且第二载流子类型的载流子迁移率在所述第二晶面上高于在所述第一晶面上，所述电子芯片包含：第一器件，该器件具有至少一个由所述材料的所述第一晶面制造的部件，其中所述第一器件的所述至少一个部件包括主要是所述第一载流子类型的活性；第二器件，该器件具有在所述材料的所述第二晶面上制造的至少一个部件，其中所述第二器件的所述至少一个部件的活性主要涉及所述第二载流子类型。
图1示出了作为电子薄层密度的函数的硅和锗反型层中电子迁移率的计算比较，包括和不包括界面粗糙度的散射。如折线1所示，(111)表面上的锗反型层的电子迁移率明显高于锗的(100)表面(折线2)和硅的(100)表面(折线3)。在这三条折线中空心符号表示没有表面粗糙度，实心符号表示有表面粗糙度的对应折线4，5，6。
具体而言，在锗中，n沟道FET载流子传输在(111)晶面上沿<110>方向较高，而p沟道FET的载流子传输在(100)晶面上沿<110>方向上较高。本发明人已经认识到通过重视这一规则，载流子传输可以通过根据晶体取向为每一器件选择器件结构，且使所述器件沿<110>方向定位而针对锗的n沟道FET和p沟道FET优化。
可取的是，所述结构和方法在(111)表面上沿<110>方向制造锗n沟道FET。
可取的是，所述结构和方法在同一晶片上制造具有第一类型载流子的第一器件和具有第二类型载流子的第二器件，其中第一类型载流子的载流子迁移率在(111)晶向上较高，第二类型载流子的载流子迁移率在(100)晶向上较高。
可取的是，所述方法和结构在同一芯片上一起形成n沟道FET和p沟道FET，使用锗作为底层。
可取的是，所述方法在Ge MOSFET，或任何在(111)和(100)表面上具有不同传输性能的MOSFET上获得最佳的nFET和pFET载流子传输性能。
根据本发明的第四方面，描述的是一种用于电子芯片的方法和结构，包括具有第一载流子类型的第一器件，所述第一器件在其中所述第一载流子类型的载流子迁移率在(111)表面上高于(100)表面上的材料的(111)晶面上制成。该第一方面的优选实施例是在锗中在(111)表面上沿(110)方向制造的n沟道FET。
根据本发明的第五方面，描述的是一种用于电子器件的方法和结构，包括具有第一载流子类型的第一器件，和具有第二载流子类型的第二器件，所述第一器件在其中所述第一载流子类型的载流子迁移率在(111)表面上高于(100)表面上的材料的(111)晶面上制成，所述第二器件在所述材料的(100)晶面上制成，所述材料中第二载流子类型的载流子迁移率在(100)表面上高于(111)表面上。该第二方面的优选实施例包含在(111)表面上沿(110)方向的n沟道FET，和在(100)表面上沿(110)方向的p沟道FET，其中两器件在锗层上制成。
附图说明
现在将通过示例，参照附图中所示的优选实施例描述本发明，其中：
图1示出了作为电子薄层密度的函数的硅和锗反型层中电子迁移率的计算比较；
图2示出了(100)表面上的Si衬底n-MOSFET和(111)表面上的类似Ge器件的计算漏电流与漏源电压；
图3示出了在SOI衬底上具有三角形平行线沟道的MOSFET结构，如现有技术中已知；
图4示出了FinFET结构的纵向剖面图，如现有技术中已知；
图5示出了图4所示的FinFET的示例性制造；
图6示出了用于本发明的第一示例性实施例的示例性方法；
图7示出了用于本发明的第二示例性实施例的示例性方法；
图8示出了根据本发明制造的示例性nFET和pFET的侧向剖面图；
图9示出了制备用于示例性材料锗的(111)平面的示例性方法。
具体实施方式
现在参照附图，更准确地说参照图1，通过比较折线1和折线2，3和6，在(111)表面上的Ge反型层的电子迁移率明显高于(100)表面上的Si或Ge。通过严格的器件模拟和分析，本发明人已经作出了该图，从而得出当n沟道FET的电流传输在(111)表面上沿(110)方向时，p沟道FET电流传输在(100)表面上沿(110)方向时，锗场效应晶体管(Ge FET)具有较高的电流驱动。
图2示出了在(100)表面上的25nm沟道长度的Si衬底n-MOSFET(折线21)和在(111)表面上类似的Ge器件(折线22)的计算漏电流和漏源电压折线20。所述Ge器件显示出明显更大的电流和跨导。
所以，为了使载流子传输的益处最大化，不仅需要选择所述材料，而且还要选择载流子传输发生的正确的晶体取向和方向。在优选实施例中，选择优选的晶体取向和方向，以使载流子传输最优化。因为晶片通常是从仅具有一个主要的晶体取向的锭坯上切成，所以通常难以在同一晶片上沿不同的晶体取向制造FET。所以，所述优选实施例使用这样的方法在同一晶片上制造n沟道和p沟道Ge FET，该方法利用具有晶体平面和方向的不同的FET结构来优化各自的载流子迁移率。
使用硅(Si)作为栅极沟道的具有(111)结构的FET结构是已知的。图3示出了一个示例，如Saito等在“三角形平行线沟道MOSFET中的短沟道效应的抑制”(IEEE硅纳米电子研究组，第6-7页，Kyoto，日本，6月10-11，2001)中所述，具有三角形平行线沟道且在硅的内置氧化物(BOX)上制造的MOSFET结构30。所述三角形平行线沟道31通过利用氢氧化四甲铵(TMAH)进行各向异性蚀刻而实现。然后，所生成的Si(111)平面由具有氧化层和栅电极的栅极结构32覆盖。用于所述线沟道的相同硅层也用于源极33和漏极34的形成。
在用于抑制“短沟道效应”的技术领域还已知的是硅基、自对准双栅极MOSFET结构，称作FinFET。图4示出了由Huang等在“50nm以下的FinFET：PMOS”(IEEE国际电子器件会议(IEDM)，第67-70页，1999)中描述的FinFET的纵向剖面图。源极41和漏极42利用在内置氧化物(BOX)层43(在硅晶片44)上顶部和在由硅氧化物层46覆盖的硅翅片45顶部的多晶SiGe制造。氮化物间隔层47和SiGe构成的栅极48形成FinFET结构，该结构可以使短沟道结构短至17nm，且模拟显示可以缩小到10nm的栅极长度。
超薄Si翅片45用于抑制短沟道效应。在氮化物间隔层47之间的两间距形成沟道长度。由多聚-SiGe形成的升高的源极41和漏极42减小了寄生电阻。
图5示出了这种硅基FinFET的一种可行的制造顺序。在步骤A，厚度50nm的Si层51淀积在SOI晶片的BOX层50顶部，随后是厚度100nm的SiO2层52。硅层51在步骤B中蚀刻，形成氧化物覆盖的翅片结构，利用电子束光刻法蚀刻SiO2层52，形成用于蚀刻硅而产生所述翅片结构的硬掩模。在步骤C，300nm厚的低温氧化物(LTO)层淀积在200nm的p+多晶SiGe层上，且这两层54和55在步骤D蚀刻，首先蚀刻LTO层，成为用于多晶SiGe层的反应离子蚀刻而生成源极56和漏极57的掩模。通过淀积100nm的氮化物层并随后蚀刻，在步骤E中形成氮化物间隔层58。间隔层之间的间隙通常小于20nm。
为形成步骤F的栅极结构，生长15nm的牺牲氧化物层并进行湿蚀刻而去除翅片侧面的早期干蚀刻造成的损坏。该步骤还减小了翅片的厚度，而使翅片的最终厚度在15nm至30nm的范围内。2.5nm的栅极氧化物在750℃下在翅片的所述侧面上生长，该“高温”步骤与附加的退火步骤组合，驱使硼从SiGe的升高的源极/漏极区域进入氮化物间隔层下方的翅片中，形成p+源极/漏极延伸部分。在淀积了200nm原位掺杂的SiGe(60％Ge，具有4.75ev的逸出功)作为栅极材料之后，对所述电极进行构图并蚀刻。
通过将这些现有技术示例作为其中特定晶面比如(111)用于器件的特定部件的技术示范，并将这些现有技术中适当之一与图1和2的结论组合，现在将解释本发明的两个示例性优选实施例，其中使用锗作为所述材料，和FET沟道作为具体的器件部件。
第一示例性实施例包含由图6概括的方法60。在步骤61中，材料锗(Ge)作为在(111)晶面上n沟道FET载流子具有最佳载流子迁移率、在(100)晶面上p沟道FET载流子具有最佳载流子迁移率的材料。载流子传输的最佳方向对两种载流子类型来说是<110>方向。
因此，为了证明本发明的第一示例性实施例，n沟道FET将针对锗优化设计。因为在FET中感兴趣的活性出现在沟道内，所以nFET沟道在(111)平面内具有最佳的载流子迁移率。所以，在步骤63和64中，所述Ge nFET的沟道和栅极在(111)表面上制备。剩余nFET部件的制造，比如源极和漏极，是直接的，但取决于所选择的具体的nFET结构。因此，在步骤63之前制备的具体器件的部件和在步骤64之后制备的具体器件的部件取决于所述器件的结构，可行的示例是图3所示的平行线结构或图4中所示的FinFET。
因为最佳的载流子传输出现在<110>方向上，所以相应地确定了沟道取向和源极和漏极的位置，对于普通技术人员来说这很容易实现。还应指出的是，本领域的普通技术人员将容易地认识到步骤63和64可以依次分离，而在这两个步骤之间制造一或多个器件部件。对于本领域的技术人员来说，显然锗材料可以是衬底或者可以是添加在硅晶片的层或者可以是添加在隔离层比如硅晶片顶部的硅氧化物上的层，或者提供锗作为晶片上的层或区域的任何其他方法。锗层的最小厚度应当足以实现nFET(111)平面的沟道的锥形晶体结构。
本发明的第二示例性实施例是图7中所示的方法70。在该实施例中在同一芯片上制造两个不同器件，每一器件具有各自的载流子类型，从而根据各自的载流子特性优化每一器件。该非限制性示例包含nFET，如上面的第一实施例所述，与pFET组合且再次使用锗作为步骤71确认的材料。因为nFET沟道最优于使用(111)平面，pFET沟道最优于使用(100)平面，步骤73A，74A和74B包含使用(111)蚀刻剂制备锗的第一区域，使其成为nFET，且使用蚀刻剂制备锗的第二区域的(100)平面，用于pFET。
显然，第一和第二区域的制备可以任何顺序完成，且制备的某些步骤可以共享。此外，类似于上面第一示例性实施例的描述，nFET和pFET器件可以具有多种已知基本结构的任一种。所述两器件可以使用相同的基本结构，而仅在沟道的制备上不同，或者所述两器件可以具有不同的基本结构。如上所述，锗可以是具有足以实现用于nFET(111)平面的沟道的锥形晶体结构的最小厚度的层。作为选择，锗可以是晶片衬底，添加在硅晶片的锗层，或添加在绝缘层比如硅晶片上的二氧化硅顶部的锗层，或者任何其他的提供锗作为晶片上的层或区域的方法。如上所述，步骤72A，72B，74A，74B，75A和75B的特定部件的制造将根据器件结构而不同，且如上所述，所述沟道和剩余器件部件将确定方位而适应两载流子的<110>载流子优选方向。
图8示出了安装在同一芯片83上且在共同的内置氧化物层(BOX)84上制造的nFET 81沟道和pFET 82沟道的示例性剖面图80。源极和漏极没有示出，但图3和4中所示的器件布局可用于解释所述源极和漏极将位于该图8的剖面图后面或在其前面。沟道85覆盖有栅极绝缘体86(比如二氧化硅)和栅电极87。栅极绝缘体和电极的制造在本领域是公知的。显然，通过考虑nFET沟道81与pFET沟道82隔离，该图示出了上述的第二示例性实施例以及第一示例性实施例。
图9示出了用于Ge层92的nFET区域的(111)晶体预制品90。硬掩模91位于nFET沟道区域上方，沿<110>方向。为实现(111)平面的这种棱柱结构94，对锗进行各向异性蚀刻93，例如使用酸性化学物质(1∶1∶1的H3PO4∶H2O2∶C2H5OH，或17∶17∶66的HF∶H2O2∶H2O(如Lang等“用于IR光栅的Ge的大规模微机械加工”所述，J.Mieromech.Microeng.，Vol.6，pp.46-48，1996)。前者是优选的，使用铬硬掩模。
示为在nFET右侧的区域95可以另一种方式制备，比如用于pFET的Ge(100)平面，且使用标准的垂直蚀刻法，如图8的右侧所示。
任何已知的FET结构可以用于完成nFET和pFET结构，只要nFET的沟道结构基于棱柱结构，pFET的沟道结构基于所述平面，如图8的剖面所示。本发明的优选实施例放置两沟道结构，而使得对nFET和pFET来说，载流子的运动在<110>方向上发生。
从上述可以明显看出，本发明的主要优点是对于Ge MOSFET或任何在(111)和(100)晶面上具有不同传输性能的MOSFET上的nFET和pFET器件来说获得了最佳的传输性能。

Claims (14)

1.一种电子芯片，具有至少一层材料，对于所述材料来说，第一载流子类型的载流子迁移率在第一晶面上高于在第二晶面上，第二载流子类型的载流子迁移率在所述第二晶面上高于所述第一晶面上，所述电子芯片包含：
第一器件，具有至少一个在所述材料的所述第一晶面上制造的部件，其中所述第一器件的所述至少一个部件的活性主要涉及所述第一载流子类型，
第二器件，具有至少一个在所述材料的所述第二晶面上制造的部件，其中所述第二器件的所述至少一个部件的活性主要涉及所述第二载流子类型。
2.如权利要求1所述的电子芯片，其特征在于：所述第一晶面包含(111)晶面，所述第二晶面包含(100)晶面。
3.如权利要求2所述的电子芯片，其特征在于：所述第一器件包含n沟道场效应晶体管，所述第一器件的至少一个部件包含所述n沟道场效应晶体管的沟道。
4.如权利要求3所述的电子芯片，其特征在于：所述n沟道场效应晶体管的所述沟道与<110>方向对齐。
5.如权利要求3所述的电子芯片，其特征在于：所述n沟道场效应晶体管的结构包含FinFET结构。
6.如前述任一权利要求所述的电子芯片，其特征在于：所述第二器件包含p沟道场效应晶体管。
7.如权利要求6所述的电子芯片，其特征在于：至少所述第一器件和所述第二器件之一的结构包含FinFET结构。
8.如权利要求1至5任一所述的电子芯片，其特征在于：所述第一器件包含n沟道场效应晶体管，所述第二器件包含p沟道场效应晶体管，且所述至少一个部件包含所述场效应晶体管的沟道。
9.如权利要求8所述的电子芯片，其特征在于：至少所述n沟道场效应晶体管和所述p沟道场效应晶体管之一的所述沟道与<110>方向对齐。
10.如前述权利要求1-5之一所述的电子芯片，其特征在于：所述材料包含锗。
11.一种在晶片上制造具有第一类型载流子的第一器件和具有第二类型载流子的第二器件的方法，所述第一类型载流子在(111)晶面上具有比在(100)晶面上高的载流子迁移率，所述第二类型载流子在(100)晶面上具有比在(111)晶面上高的载流子迁移率，所述方法包含：
提供一层材料，所述材料具有所述第一类型载流子的载流子迁移率在(111)晶面上比在(100)晶面上高的特性，以及所述第二类型载流子的载流子迁移率在所述(100)晶面上比在所述(111)晶面上高的特性；
用(111)蚀刻剂蚀刻所述层的第一区域，使所述(111)晶面用于所述第一器件的至少一个部件；
使用蚀刻剂蚀刻所述层的第二区域，使所述(100)晶面用于所述第二器件的至少一个部件。
12.如权利要求11所述的方法，其特征在于：所述材料包含锗。
13.如权利要求11所述的方法，其特征在于：所述第一器件包含n沟道场效应晶体管，所述第二器件包含p沟道场效应晶体管，且所述至少一个部件包含所述场效应晶体管的沟道。
14.如权利要求11所述的方法，其特征在于还包含：
对于至少所述第一器件的所述至少一个部件和所述第二器件的所述至少一个部件之一，使载流子方向与<110>方向对齐。
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