WO2018182685A1

WO2018182685A1 - Germanium cmos channel structures with optimized quantum confinement and multiple threshold voltage operation

Info

Publication number: WO2018182685A1
Application number: PCT/US2017/025355
Authority: WO
Inventors: Raseong KIM; Uygar E. Avci; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

Embodiments are generally directed to Germanium CMOS (Complementary Metal-Oxide Semiconductor) structures with optimized quantum confinement and multiple threshold voltage operation. An embodiment of a CMOS device includes one or both of: one or more nMOS devices (n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors)) or one or more pMOS devices (p-type MOSFETs). Each of each of the one or more nMOS devices or one or more pMOS devices includes a Germanium or Germanium alloy channel, a quantum confined channel structure, an optimum crystal orientation for the quantum confined channel structure, and a plurality of threshold voltage options.

Description

GERMANIUM CMOS CHANNEL STRUCTURES WITH OPTIMIZED QUANTUM CONFINEMENT AND MULTIPLE THRESHOLD VOLTAGE OPERATION

TECHNICAL FIELD

Embodiments described herein generally relate to the field of electronic devices and, more particularly, Germanium CMOS channel structures with optimized quantum confinement and multiple threshold voltage operation.

BACKGROUND

In microelectronic devices, Silicon CMOS (Complementary Metal-Oxide

Semiconductor) logic technology, utilizing silicon based n-type and p-type MOSFETs (Metal- Oxide-Semiconductor Field-Effect Transistors) (which may be referred to as nMOSFET (nMOS) and pMOSFET (pMOS) devices), has been extremely successful in providing a wide range of devices, and has been successfully scaled to smaller and smaller sizes with advances in microelectronic technology.

However, as Silicon CMOS scaling continues, it becomes increasingly challenging to maintain good current drivability in the MOSFET devices. As a result, the known CMOS technology is reaching a stage in which improvements in scaling and performance will be difficult and expensive.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments described here are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

Figure 1 is an illustration of a CMOS device including Germanium nMOS and pMOS elements with quantum confined channel structures having optimum crystal orientations according to an embodiment;

Figure 2 is an illustration of an ultra-thin body Germanium device according to an embodiment;

Figures 3A and 3B are illustrations of quantum confinement of an ultra-thin body Germanium nMOS device according to an embodiment;

Figure 4 is an illustration of nanowire Germanium device according to an embodiment;

Figures 5A and 5B are illustrations of quantum confinement of a nanowire Germanium nMOS device according to an embodiment;

Figures 6A, 6B, and 6C illustrate simulation results for source-drain currents in ultra- thin body nMOS devices with varying materials; Figures 6D, 6E, and 6F illustrate simulation results for source-drain currents in nanowire nMOS devices with varying materials;

Figures 7A and 7B illustrate the effect of the optimum crystal orientations for

Germanium ultra-thin body (UTB) and nanowire (NW) nMOSFETs;

Figures 8A, 8B, and 8C illustrate implementation of varying threshold voltage (Vth) transistors using different Source/Drain structures according to an embodiment;

Figures 9A and 9B illustrate the effective inverter drive current (I_eff) versus supply voltage (VDD) for ultra-thin body nMOS devices with different channel materials and high- and low OFF-current (IOEF) operations;

Figures 10A and 10B illustrate effective inverter drive current (I_eff) versus VDD for nanowire nMOS devices with different channel materials and high- and low IOEF operations;

Figures 11A and 11B illustrate simulation results for source-drain currents in ultra-thin body pMOS devices with varying materials;

Figures 12A and 12B illustrate simulation results for source-drain currents in nanowire pMOS devices with varying materials;

Figures 13A and 13B illustrate the effect of the optimum crystal orientations for Germanium UTB and NW pMOSFETs;

Figures 14A and 14B illustrate the effective inverter drive current (I_eff) versus VDD for ultra-thin body pMOS devices with different channel materials and high- and low IOEF operations;

Figures 15A and 15B illustrate the effective inverter drive current (I_eff) versus VDD for nanowire pMOS devices with different channel materials and high- and low IOFF operations;

Figure 16 is an illustration of a methodology for design and fabrication of a CMOS device including highly scaled Germanium nMOS and pMOS elements with quantum confined channel structures and multiple possible threshold voltages according to an embodiment; and

Figure 17 is an illustration of a system on chip including a CMOS device including Germanium nMOS and pMOS elements with quantum confined channel structures according to an embodiment.

DETAILED DESCRIPTION

Embodiments described herein are generally directed to Germanium CMOS channel structures with optimized quantum confinement and multiple threshold voltage options to deliver high drive currents for both low and high voltage circuits.

For the purposes of this description: "Quantum confinement" refers to a condition in which the diameter or width of a material is of the same magnitude as the de Broglie wavelength of the electron wave function, and in which the electronic and optical properties of the material will deviate greatly from the properties of a bulk material. As used herein, a material with quantum confinement in one dimension may be referred to as an ultra-thin body (UTB) and a material with quantum confinement in two dimensions may be referred to as a nanowire (NW, which may also be referred to as a quantum wire).

To continue the pace of improvements in microelectronic performance, Silicon CMOS device are continuing to be scaled to smaller sizes, and in particular the channel length (i.e., distance between the source and the drain in a field effect transistor (FET)) is being reduced to shorter and shorter lengths. With such scaling of Silicon CMOS, there is a challenge in maintaining good current drivability, and as a result alternative channel materials such as III-V materials (semiconductor materials combining Group III and Group V elements of the periodic table) for nMOS and Germanium for pMOS are attracting attention due to their high carrier mobility.

However, in the scaling of microelectronic semiconductor devices, the semiconductor body should be scaled accordingly with the channel length (for example a thin body or nanowire channel structure) to maintain good electrostatics for the short channel length. In such structures, where the effects of quantum confinement (due to the scaled body) and ballistic transport (as a result of the short channel) become very important. At these quantum sizes, the classical point of view providing that high carrier mobility (usually measured for bulk) results in high current drivability may not be valid.

In quantum confined channel structures, it becomes critical to choose the optimum crystal orientations for confinement and transport because such orientations determine band parameters such as density-of-states (DOS) and carrier effective mass (m *) that directly affect the device performance.

Another critical issue in using III-V materials for nMOS and Germanium for pMOS is integration compatibility. Using inhomogeneous materials for nMOS and pMOS may create many process challenges in implementing CMOS logic on the same wafer. Further, transistors with different threshold voltage (Vth) targets are required to meet different power-performance requirements for different blocks or products in a technology. This may become increasingly challenging when heterogeneous materials are used for nMOS and pMOS.

In some embodiments, a structure is formed with Germanium nMOS and pMOS elements having quantum-confined channel structures (ultra-thin bodies or nanowires) having optimized crystal orientations and multiple Vth options in order to provide both high- and low-voltage operations while delivering good current drivability, and further enabling homogeneous material integration and thus lower manufacturing cost.

As used herein, the terms "Germanium CMOS", "Germanium nMOS", "Germanium pMOS", and similar terms include devices having channel structures composed of Germanium or a Germanium alloy with a high Germanium content. In some embodiments, a Germanium alloy is an alloy including a majority (greater than 50%) of Germanium. An example of a Germanium alloy that may be utilized in a channel structure is Silicon Germanium (SiGe).

The MOSFET drive current (ID) can be expressed as the charge density (Q) times the carrier velocity (v). To achieve a large ID, it is important to improve both Q and v factors. To achieve a high v, a small carrier effective mass (m *) is desired. In order to maintain high Q in scaled devices, it is necessary to maintain high DOS (Density Of States - the number of states per interval of energy at each energy level that are available to be occupied) or quantum capacitance (CQ), and high overall capacitance, which is the series of the gate oxide capacitance (Cox) and CQ. The DOS depends on two quantities, m* and the valley degeneracy (g_v), with larger m* and g_v values resulting in a larger DOS. Thus, given that a small m* is desired for high v, an optimum process to increase both Q and v thus would be to increase g_v while keeping m* small.

In some embodiments, Germanium quantum structures are produced with certain optimum crystal orientations, i.e., ultra-thin bodies (UTBs) with (110) confinement and <110> transport orientation and nanowires (NWs) with <110> transport orientation. In some embodiments, such quantum structures may be implemented to provide desirable characteristics for both nMOS (where large electron DOS and electron effective mass (m_e*) are desired) and pMOS (where large hole DOS and hole effective mass (mh*) are desired). As described herein, nMOS and pMOS devices include devices without regard to the physical directionality of the device, thus including, but not limited to, lateral (in-plane) devices and vertical devices.

In some embodiments, a Germanium CMOS channel structure further enables modification of the threshold (Vth) of scaled Germanium nMOS and pMOS, Vth being changed by implementing different source/drain (S/D) designs (including tip doping densities and/or gate underlap lengths), thus enabling material-compatible, Germanium-based CMOS technology to support both high performance (high supply voltage (VDD), low Vth, high OFF-current (IOEF)) and low power (low VDD, high Vth, low IOEF) operations.

The known, conventional approach to deriving the current drivability in scaled CMOS is based on the carrier mobility model. For example, Table 1 illustrates electron and hole mobility of different materials, the materials being Silicon (Si), Indium Arsenide (InAs), and Germanium (Ge), measured for intrinsic bulk at 300 K.

Table 1

Electron and Hole Mobility of Materials - Intrinsic Bulk at 300K

For electrons, InAs shows the highest mobility of the materials, while for holes,

Germanium shows the best value for mobility. These mobility results may encourage efforts to implement InAs (or Indium Gallium Arsenide (InGaAs) with high percentage of Indium) for nMOS, while potentially utilizing Germanium for pMOS. However, such implementation of InAs (including, for example, InGaAs with a high percentage of Indium) for nMOS and

Germanium for pMOS may suffer from at least the following problems:

(a) For extremely scaled devices, a high (bulk) mobility of a material does not necessarily mean that the device made out of that material is capable of delivering high drive current in a device. Non-conventional effects such as quantum confinement and ballistic transport become increasingly important as a device is scaled to smaller dimensions. For this reason, rather than focusing on the simple, mobility-based model, it is critical to consider all relevant physical aspects to choose the correct material/structure/crystal orientations to address the current drivability issue.

(b) The implementation of inhomogeneous materials for n-type and p-type devices, such as InAs for nMOS and Germanium for pMOS, may create numerous process challenges. Given that the expected performance improvement itself may be questionable (such as the III-V nMOS as discussed above), the requirement for a high level of experimental efforts to address the process challenges may significantly detract from the value of this approach.

For example, III-V materials, while having high electron mobility due to their light m_e*, also have low electron DOS, which is another result of the light m_e*. For highly scaled nMOS, the low DOS of III-V materials may result in significant loss of channel charge, and thus the drive current improvement is less than would be predicted based on the mobility improvement. Stated in another manner, the material suffers from a "DOS bottleneck".

Another issue in short channel devices is the tunneling leakage (leakage across semiconductor junctions). For example, the light m_e* of III-V materials, which boosts the mobility and drive current in the classical long-channel picture, may result in increased tunneling leakage and high Vth in extremely short channel devices. This combination of factors makes it difficult to achieve high drive current for a given IOEF and VDD target, or in some instances it may be impossible to achieve the IOFF target due to the increased leakage floor.

Further, the conventional approach for achieving different power-performance targets with different transistor Vth options is to use different channel doping densities, or different gate work function (WF) metals. However, these approaches are generally costly and may increase unwanted transistor variation, which is an important issue for the state-of-the-art CMOS. The technology development may become even more challenging when inhomogeneous materials are used for nMOS and pMOS.

In some embodiments, an apparatus, system, or process includes Germanium nMOS and pMOS (including Germanium or Germanium alloy) with quantum confined channel structures, the quantum confined channel structures being ultra-thin bodies or nanowires with optimum crystal orientations, to provide sufficient drive current while also minimizing process challenges through the use of homogenous materials for nMOS and pMOS, and to allow multiple different threshold voltages by varying the source-drain structure. In some embodiments, a substrate of the Germanium nMOS and pMOS may be Germanium or a second material, wherein the second material may include, but is not limited to, Silicon.

For nMOS, although Germanium is not the material with the highest electron mobility at the bulk state (as seen in Table 1), in quantum-confined structures with optimum crystal orientations, Germanium provides the potential to deliver higher drive current in comparison with other materials, such as III-V materials and Silicon.

For pMOS, in addition to Germanium providing the highest hole bulk mobility in comparison with other possible materials, as shown in Table 1, the addition of optimum crystal orientations for scaled devices with quantum-confined structures provides enhanced

performance.

In some embodiments, different Vth and IOFF targets of Germanium nMOS and pMOS are achieved by implementing different Source/Drain designs (for example, tip doping and/or gate underlap, such as illustrated in Figures 8B and 8C). This approach to the parameter variation is implemented to provide a simpler process for Vth adjustment in comparison with conventional processes, and to further assist in alleviating the transistor variation issue. In some embodiments, an apparatus, system, or process is provided to enable Germanium CMOS devices with multiple Vth options to cover both high- and low-voltage operations delivering good drive currents and homogeneous material integration with lower manufacturing cost.

Figure 1 is an illustration of a CMOS device including Germanium nMOS and pMOS elements with quantum confined channel structures having optimum crystal orientations according to an embodiment. In some embodiments, a CMOS device 100 includes one or more Germanium pMOS 110, one or more Germanium nMOS 120 devices, or both. In some embodiments, the pMOS 110 and nMOS devices 120 utilize homogenous Germanium channel structures to reduce complications in fabrications of the scaled devices.

In some embodiments, the pMOS 110 and nMOS 120 devices include quantum confined channel structures, such as illustrated in Figure 2 for an ultra-thin body construction and Figure 4 for a nanowire construction, and optimized crystal orientations, such as illustrated in Figures 3 A and 3B for an ultra-thin body construction and Figures 5 A and 5B for a nanowire construction. In some embodiments, the MOSFET devices may include varying source/drain designs to vary the threshold voltages for devices as required in particular implementations.

Figures 2 through 5B illustrate device diagrams and describe the quantum confinement of L-valleys of the Germanium conduction band (CB) for nMOS operation. While the figures provided herein include certain implementations and views of devices for ease of illustration, embodiments are not limited to any particular physical directionality of a device, and include, but are not limited to, lateral (in-plane) devices and vertical devices. Further, the illustrations of devices with Germanium channel structures include both Germanium and Germanium alloys with a high Germanium content. In some embodiments, a Germanium alloy is an alloy including a majority (greater than 50%) of Germanium.

Figure 2 is an illustration of an ultra-thin body Germanium device according to an embodiment. Figure 2 illustrates an ultra-thin body structure that may be utilized for either nMOS or pMOS devices. In some embodiments, a Germanium CMOS transistor 200 is an ultra- thin body (UTB) structure with one-dimensional (ID) confinement, wherein the ID confinement is in the y-direction in Figure 2. As illustrated, the transistor includes gate 210, drain 220, source 230, and channel 240. As illustrated in Figure 2, LG is the gate length, t_s is the channel depth, and EOT is the equivalent oxide thickness.

As illustrated in Figure 2, the confinement is along the (110) surface and transport along <110> orientation between drain and source, as illustrated in the x direction. In some embodiments, the transistor 200 is quantum confined by the ultra-thin channel. In some embodiments, the transistor has an optimum crystal alignment.

Figures 3A and 3B are illustrations of quantum confinement of an ultra-thin body Germanium nMOS device according to an embodiment. As illustrated in Figure 3 A, for the ultrathin body structure with (110) confinement (y-direction) and <110> transport (x-direction), Germanium CB L-valleys providing lowest bands with g_v = 2 and light m_e* along the x-direction

(mex*).

Figure 4 is an illustration of nanowire Germanium device according to an embodiment. Figure 4 illustrates a nanowire structure that may be utilized for either nMOS or pMOS devices. In some embodiments, a Germanium nMOS or pMOS transistor 400 includes a nanowire (NW) channel structure with two-dimensional (2D) confinement, wherein the 2D confinement is in the y and z directions in Figure 4. As illustrated, the transistor 400 includes gate 410, drain 420, source 430, and channel 440. LG is the gate length, t_s is the channel depth, and EOT is the equivalent oxide thickness.

As illustrated in Figure 4, the transport is along the <110> direction (x-direction) between drain and source, the transistor being quantum confined along the 2D plane (defined by y and z directions) perpendicular to the transport direction.

Figures 5A and 5B are illustrations of quantum confinement of a nanowire Germanium nMOS device according to an embodiment. In the illustrated nanowire Germanium channel structure, the L-valleys providing lowest bands with g_v=2 and light m_e* at the zone center.

Figures 6A, 6B, and 6C illustrate simulation results for source-drain currents in ultra- thin body nMOS devices with varying materials. Figure 6A (InAs UTB nMOS), Figure 6B (Si UTB nMOS), and Figure 6C (Ge UTB nMOS) provide simulation results for the source-drain current (drive current ID) versus the drain voltage (VD) at certain gate voltages (VG), with IOEF = 10 nA/um, for the effective width (W_eff). For double gate (DG) UTB nMOS with (110)/[110] confinement/transport, t_s = 5 nm, equivalent oxide thickness (EOT) = 0.8 nm, and gate length (LG) = 13 nm.

For this highly scaled device (small t_s, thin EOT), InAs (illustrated in Figure 6A) does not significantly improve ID compared with Silicon (Figure 6B) due to the DOS bottleneck of the InAs material.

For Germanium (illustrated in Figure 6C), however, the drive current is significantly improved over InAs and Silicon due to the still high Vinj (as m_ex* being much lighter than in Si) with no Q degradation (because DOS is maintained sufficiently high). As shown in Figure 6A for the InAs UTB nMOS device, despite the light m_e* and high injection voltage (vinj), InAs does not improve drive current ID in comparison with the results for the Silicon UTB nMOS device (Figure 6B) because of the low electron DOS of InAs. In some embodiments, a Germanium UTB structure that is optimally quantum-confined may be utilized to deliver significantly improved I_D in comparison with the Silicon UTB due to the improved DOS (larger g_v) with still high Vinj (small m_ex*).

For nanowire implementations, there are similar results regarding the effects of g_v, m_e*, and DOS as in the UTB case. For InAs NW, there is a band with g_v=l and light m_e*, which provides high Vinj but much smaller DOS compared with Si (g_v=2, heavier m_e*). For Germanium NW with <110> transport, the L-valleys give bands with g_v=2 (higher than in InAs) and m_e* heavier than InAs but still much lighter than in Si, which result in DOS being improved over InAs with still high Vinj .

Figures 6D, 6E, and 6F illustrate simulation results for source-drain currents in nanowire nMOS devices with varying materials. Figure 6D (InAs NW nMOS), Figure 6E (Si NW nMOS), and Figure 6F (Ge NW nMOS) provide simulation results for the source-drain current (ID) versus the drain voltage (VD) at certain gate voltages (VG), with IOFF = 10 nA/um for the effective width (Wee), NW nMOS with <110> transport direction.

For the nanowire device, InAs (illustrated in Figure 6D) does not significantly improve ID compared with Silicon (Figure 6E) due to the low electron DOS. Germanium (illustrated in Figure 6F), when optimally quantum-confined, delivers a drive current that is significantly improved over InAs and Silicon due to the improved DOS (larger g_v) with still high Vinj (small m_e*).

Figures 7A and 7B illustrate the effect of the optimum crystal orientations for

Germanium UTB and NW nMOSFETs. Figure 7A illustrates simulation results for ID VS. VG (gate voltage) at VD = 0.6 V for Germanium UTB nMOS for different confinement/transport orientations along with Silicon reference. For Germanium UTB, (110)/[110]

confinement/transport provides the best current performance, while the performance may degrade significantly for other orientations. In Figure 7B for Germanium NW nMOS, it can again be seen that ID may degrade significantly for transport directions other than <110>. In summary, it can be seen that Germanium material per se would not guarantee the best nMOS performance for quantum-confined channel structures, but rather the choice of the optimum crystal orientations allows the realization of the best performance for the Germanium material.

Figures 8A, 8B, and 8C illustrate implementation of varying Vth transistors using different Source/Drain structures according to an embodiment. Specifically, Figure 8A illustrates a transistor with a highly doped source/drain (S/D) structure according to an embodiment. In Figure 8A, the transistor is illustrated with semiconductor material in a source region 810 adjacent to a source terminal, a gate region 820 adjacent to a gate terminal, and a drain region 830 adjacent to a drain terminal. In some embodiments, the transistor includes high doping of semiconductor material in the source region 810 and drain region 830 and no gate underlap, i.e., no underlap of lightly-doped or undoped material of the gate region 820 into either of the source region 810 and drain region 830 of the transistor.

Figure 8B illustrates a transistor with a gate underlap drain-source structure according to an embodiment. In some embodiments, the transistor includes a gate underlap (XUD), the gate underlap being an underlap of the lightly doped or undoped semiconductor material of the gate region 820 into the source region 810, drain region 830, or both.

Figure 8C illustrates a transistor with a low doped source or drain tip structure according to an embodiment. In some embodiments, the transistor includes a region of low doping semiconductor material (referred to as the "tip region") in the source region 810, the drain region 830, or both. Thus, the tip region (with low doped material) is between the highly doped material of the source or drain region, and the lightly doped or undoped material of the gate region, the tip region including less doping than the highly doped material of the source and drain regions and more doping than the lightly doped or undoped material of the gate region.

In some embodiments, the high S/D doping with no gate underlap structure as illustrated in Figure 8A is a construction providing for low Vth and high performance.

In some embodiments, to provide for lower power consumption in comparison with the high S/D doping device structure, a device channel construction including a gate underlap (XUD) as shown in Figure 8B, a low doped source/drain tip region as shown in Figure 8C, or both can produce a high Vth device with a smaller subthreshold swing (SS) and drain-induced barrier lowering (DIBL), which are characteristics required for a low-power device.

In some embodiments, by implementing low (or high) tip doping densities, a process will produce high Vth transistors suitable for low power operation, or low Vth transistors suitable for high performance operation. In some embodiments, a low Vth (high performance) device with high S/D doping may be produced by providing no gate underlap. In some embodiments, a high Vth (low power) device may be produced by having a gate underlap (XUD), low S/D tip doping densities, or both.

Figures 9A and 9B illustrate the effective inverter drive current (I_eff) versus VDD for ultra-thin body nMOS devices with different channel materials and high- and low IOEF operations. Figure 9A illustrates I_eff versus VDD for UTB nMOSFETs (with (1 10) confinement and <110> transport) for In As, Silicon, Germanium with low tip doping, and Germanium with high tip doping channel materials for high IOEF (100 ηΑ/μιη, for W_eff) target. Figure 9B provides the same information for low IOFF (0.1 ηΑ/μιη) target (excluding InAs UTB as this construction cannot satisfy the low IOFF target). S/D parasitic resistance (RSD) of 200 Ω-μιη is included in the simulation.

As shown in Figures 9A and 9B, Germanium UTB nMOS with optimum crystal orientations (with (110) confinement and <110> transport) provides the best results of the possible materials for both high performance and low power operations.

Figures 10A and 10B illustrate effective inverter drive current (I_eff) versus VDD for nanowire nMOS devices with different channel materials and high- and low IOFF operations. Figure 10A illustrates I_eff versus VDD for NW nMOSFETs (with <110> transport) for InAs, Silicon, Germanium with low tip doping, and Germanium with high tip doping channel materials for a high IOFF (100 ηΑ/μπι, for Wee) target. Figure 10B provides the same information for a low IOFF (0.1 ηΑ/μπι) target. S/D parasitic resistance (RSD) of 200 Ω-μπι is included in the simulation.

As shown in Figures 10A and 10B, Germanium NW nMOS with optimum crystal orientation (with <110> transport) provides the best results of the possible materials for both high performance and low power operations.

Thus, for both ultra-thin body and nanowire NMOS transistor devices with optimum crystal orientations and multiple Vth options (through XUD or tip doping), Germanium nMOS construction provides the best performance (in comparison with III-V (InAs) and Silicon) for both high performance (low Vth, high IOFF, high VDD) and low power (high Vth, low IOFF, low VDD) operations.

In addition to providing better performance in nMOS devices, Germanium pMOS construction with optimum crystal orientations also provides better performance in comparison with other materials. The structures illustrated in Figure 2 (ultra-thin body Germanium device) and Figure 4 (nanowire Germanium device) also apply to pMOS devices. For Silicon ultra-thin body devices, rrihx* (rrih* along the transport direction x) is higher than that of Germanium ultra- thin body devices. While the hole DOS is high for the possible materials due to the large number of bands in valence band (VB) (there being no DOS bottleneck for pMOS), rrihx* is the key parameter that determines the device performance. Therefore, it may be expected that an embodiment of a Germanium UTB pMOS will deliver better drive current than Silicon due to the small rrihx* and high hole Vmj . Figures 11A and 11B illustrate simulation results for source-drain currents in ultra-thin body pMOS devices with varying materials. Figure 11 A (Si UTB pMOS), and Figure 1 IB (Ge UTB pMOS) provide simulation results for the source-drain current (ID) versus the drain voltage (VD) at certain gate voltages (V_G) (IOFF = lOnA/um for W_eff), for UTB pMOS with (110)/[110] confinement/transport.

In some embodiments, the Germanium UTB channel structure, when optimally quantum-confined, delivers significantly improved ID in comparison with the Silicon UTB due to the high Vinj (small rrihx*).

For the nanowire case, while the hole DOS is high for all material (e.g. Silicon and Germanium) due to the large number of bands in VB (no DOS bottleneck for pMOS), the small mh* of Germanium thus may be implemented to provide better drive current performance in comparison with Silicon devices.

Figures 12A and 12B illustrate simulation results for source-drain currents in nanowire pMOS devices with varying materials. Figure 12A (Si NW pMOS), and Figure 12B (Ge NW pMOS) provide simulation results for the source-drain current (ID) versus the drain voltage (VD) at certain gate voltages (VG) (IOFF = lOnA/um for W_eff), for NW pMOS with <110> transport.

In some embodiments, a Germanium NW channel structure, when optimally quantum- confined, may be implemented to deliver significantly improved ID in comparison with the Silicon NW due to the high Vinj (small rrihx*).

Figures 13A and 13B illustrate the effect of the optimum crystal orientations for

Germanium UTB and NW pMOSFETs. Figure 13A illustrates simulation results for ID VS. VG (gate voltage) at VD = -0.6 V (IOFF = 1 nA/um, for Weff) for Germanium UTB pMOS for different confinement/transport orientations in comparison with the Silicon reference. For Germanium UTB, (110)/[110] confinement/transport provides the best current performance, while the performance may degrade significantly for other orientations.

In Figure 13B for Germanium NW pMOS, it can again be seen that ID may degrade significantly for transport directions other than <110>.

As in the nMOS case, pMOS with different Vth's can be realized by implementing varying source/drain designs, such as illustrated in Figures 8A, 8B, and 8C. By utilizing low (or high) tip doping densities, it is possible to realize high (or low) Vth transistors that are suitable for low power (or high performance) operation.

Figures 14A and 14B illustrate the effective inverter drive current (I_eff) versus VDD for ultra-thin body pMOS devices with different channel materials and high- and low IOFF operations. Figure 14A illustrates Ieff versus VDD for UTB pMOSFETs (with (110) confinement and <110> transport) for Silicon, Germanium with low tip doping, and Germanium with high tip doping channel materials for a high IOFF (100 ηΑ/μιη, for W_eff) target. Figure 14B provides the same information for a low IOFF (0.1 ηΑ/μιη) target. S/D parasitic resistance (RSD) of 200 Ω-μιη is included in the simulation.

As shown in Figures 14A and 14B, Germanium UTB pMOS with optimum crystal orientations provides the best results of the possible materials for both high performance and low power operations.

Figures 15 A and 15B illustrate the effective inverter drive current (I_eff) versus VDD for nanowire pMOS devices with different channel materials and high- and low IOFF operations. Figure 15A illustrates I_eff versus VDD for NW pMOSFETs (with <110> transport) for Silicon, Germanium with low tip doping, and Germanium with high tip doping channel materials for a high IOFF (100 ηΑ/μιη, for Weff) target. Figure 15B provides the same information (excluding Germanium high tip doping) for a low IOFF (0.1 ηΑ/μιη) target. S/D parasitic resistance (RSD) of 200 Ω-μπι is included in the simulation. As shown in Figures 15A and 15B, Germanium NW nMOS with optimum crystal orientation provides the best results of the possible materials for both high performance and low power operations.

Thus, for both ultra-thin body and nanowire pMOS transistor devices with optimum crystal orientations and multiple Vth options (through XUD or tip doping), Germanium PMOS construction provides the best results in comparison with Silicon for both high performance (low Vth, high IOFF, high VDD) and low power (high Vth, low IOFF, low VDD) operations.

Figure 16 is an illustration of a methodology for design and fabrication of a CMOS device including highly scaled Germanium nMOS and pMOS elements with quantum confined channel structures and multiple possible threshold voltages according to an embodiment. In some embodiments, a methodology for design and fabrication of a CMOS device with

Germanium nMOS and pMOS 1600 may include identification of operational needs for the devices 1605, wherein the operation needs include whether the devices are operating in a high performance or a low power implementation.

In some embodiments, the particular quantum confined transistor implementation is identified, including whether the transistors are implemented as ultra-thin-body devices or nanowire devices 1610. In some embodiments, identification of the transistor implementation includes identifying optimum (110) confinement and <110> transport for an ultra-thin body device, or <110> transport for a nanowire device.

In some embodiments, the methodology may further include identifying a source/drain structure for the desired operation 1615. In some embodiments, the source/drain structure may be as illustrated in Figure 8A (transistor with high doping in the source and drain and no gate underlap); Figure 8B (transistor with a gate underlap (XUD)); or Figure 8C (transistor with a low doped S/D tip) as required to provide a higher or lower threshold voltage.

In some embodiments, the methodology continues with the fabrication of the CMOS with Germanium nMOS and pMOS devices having the identified characteristics 1620.

Figure 17 is an illustration of a system on chip including a CMOS device including Germanium nMOS and pMOS elements with quantum confined structures according to an embodiment. In some embodiments, a system on chip (SoC) 1700 includes one or more active components within the elements, including one or more CMOS device including Germanium nMOS and pMOS elements with quantum confined channel structures having optimum crystal orientations and multiple possible threshold voltages 1780. In some embodiments, the

Germanium nMOS and pMOS elements include one or more of ultra-thin body devices or nanowire devices as illustrated in Figures 2 and 4 respectively.

In some embodiments, the SoC 1700 may further include, but is not limited to, the following:

(a) A central processing unit (CPU) or other processing element 1710 for the processing of data.

(b) A graphics processing unit (GPU) 1720 to create images for output to a display.

(c) Memory 1730, where memory may include random access memory (RAM) or other dynamic storage device or element as a main memory for storing information and instructions to be executed by the CPU 1710 and the GPU 1720. Main memory may include, but is not limited to, dynamic random access memory (DRAM). Memory 1730 may further include a non-volatile memory, such as flash memory, and a read only memory (ROM) or other static storage device for storing static information and instructions for the CPU 1710 and GPU 1720.

(d) A Northbridge 1740 to handle communications between the CPU and other component of the SoC. In some embodiments, the SoC 1700 may further include a Southbridge 1750 to handle I/O functions.

(e) A transmitter, receiver, or both 1760 for the transmission and reception of data via wireless communications, and one or more antennas for transmission or reception of wireless communication. Wireless communication includes, but is not limited to, Wi-Fi, Bluetooth™, near field communication, and other wireless communication standards. The one or more antennas include one or more dipole, monopole, or other antennas.

(f) One or more interfaces 1770, including USB (Universal Serial Bus), Firewire, Ethernet, or other interfaces. In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments. It will be apparent, however, to one skilled in the art that embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. There may be intermediate structure between illustrated components. The components described or illustrated herein may have additional inputs or outputs that are not illustrated or described.

Various embodiments may include various processes. These processes may be performed by hardware components or may be embodied in computer program or machine- executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the processes.

Alternatively, the processes may be performed by a combination of hardware and software.

Portions of various embodiments may be provided as a computer program product, which may include a computer-readable medium having stored thereon computer program instructions, which may be used to program a computer (or other electronic devices) for execution by one or more processors to perform a process according to certain embodiments. The computer-readable medium may include, but is not limited to, magnetic disks, optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or other type of computer-readable medium suitable for storing electronic instructions. Moreover, embodiments may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer.

Many of the methods are described in their most basic form, but processes can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present embodiments. It will be apparent to those skilled in the art that many further modifications and adaptations can be made. The particular embodiments are not provided to limit the concept but to illustrate it. The scope of the embodiments is not to be determined by the specific examples provided above but only by the claims below.

If it is said that an element "A" is coupled to or with element "B," element A may be directly coupled to element B or be indirectly coupled through, for example, element C. When the specification or claims state that a component, feature, structure, process, or characteristic A "causes" a component, feature, structure, process, or characteristic B, it means that "A" is at least a partial cause of "B" but that there may also be at least one other component, feature, structure, process, or characteristic that assists in causing "B." If the specification indicates that a component, feature, structure, process, or characteristic "may", "might", or "could" be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, this does not mean there is only one of the described elements.

An embodiment is an implementation or example. Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. It should be appreciated that in the foregoing description of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various novel aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed embodiments requires more features than are expressly recited in each claim. Rather, as the following claims reflect, novel aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims are hereby expressly incorporated into this description, with each claim standing on its own as a separate embodiment.

In some embodiments, a CMOS (Complementary Metal-Oxide Semiconductor) device includes one or both of: one or more nMOS devices (n-type MOSFETs (Metal-Oxide- Semiconductor Field-Effect Transistors)); or one or more pMOS devices (p-type MOSFETs). In some embodiments, each of the one or more nMOS devices or one or more pMOS devices includes the following: a Germanium or Germanium alloy channel, a quantum confined channel structure, an optimum crystal orientation for the quantum confined channel structure, and a plurality of threshold voltage options.

In some embodiments, the quantum confined channel structure of an nMOS or pMOS device is one of an ultra-thin body structure that is quantum confined in one dimension or a nanowire structure that is quantum confined in two dimensions.

In some embodiments, the device is an ultra-thin body device, and wherein the optimum crystal orientation for the device is a (110) orientation for confinement and a <110> orientation for transport. In some embodiments, the device is a nanowire, and wherein the optimum crystal orientation for the device is a <110> orientation for transport.

In some embodiments, the plurality of threshold voltage options for a device include a low threshold voltage option for high performance operation of the device and a high threshold voltage option for low power operation of the device.

In some embodiments, a threshold voltage option of the plurality of threshold voltage options is established by varying a source-drain structure for the device.

In some embodiments, selection of a source-drain structure for high performance operation includes selection of a source-drain structure with high doping of material in a source region and a drain region of the device without gate underlap of lightly doped or undoped material of a gate region of the device into the source region or drain region.

In some embodiments, selection of a source-drain structure for low power operation includes selection of one or both of the following: a structure with an underlap of lightly doped or undoped material of a gate region of the device into a source region, a drain region, or both of the device, the source region and drain region including highly doped material; or a structure with a tip region having low doped material in the source region, the drain region, or both, the tip region being between the highly doped material of the source region, drain region, or both, and the lightly doped or undoped material of the gate region.

In some embodiments, the Germanium alloy contains a majority of Germanium.

In some embodiments, a method of fabrication of a CMOS (Complementary Metal-Oxide

Semiconductor) device includes fabricating one or both of: one or more nMOS devices (n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors)), or fabricating one or more pMOS devices (p-type MOSFETs). In some embodiments, fabricating each of the one or more nMOS devices or one or more pMOS devices includes the following: implementation of a Germanium or Germanium alloy channel, formation of a quantum confined channel structure, the channel structure including an optimum crystal orientation for the structure, and fabrication of a structure of a source and drain of the device to select one of a plurality of threshold voltage options.

In some embodiments, the quantum confined channel structure of an nMOS or pMOS is one of an ultra-thin body structure that is quantum confined in one dimension or a nanowire structure that is quantum confined in two dimensions.

In some embodiments, the nMOS or pMOS device is an ultra-thin body device, and the optimum crystal orientation for the nMOS or pMOS device is a (110) orientation for

confinement and a <110> orientation for transport. In some embodiments, the nMOS or pMOS device is a nanowire, and wherein the optimum crystal orientation for the device is a <110> orientation for transport.

In some embodiments, fabrication of the source-drain structure for high performance operation includes fabrication of a source-drain structure with high doping of material in a source region and a drain region of the device without gate underlap of lightly doped or undoped material of a gate region of the device into the source region or drain region.

In some embodiments, fabrication of the source-drain structure for low power operation includes fabrication of a source-drain structure that includes fabrication of one or both of the following: a structure with an underlap of lightly doped or undoped material of a gate region of the device into a source region, a drain region, or both of the device, the source region and drain region including highly doped material; or a structure with a tip region having low doped material in the source region, the drain region, or both, the tip region being between the highly doped material of the source region, drain region, or both, and the lightly doped or undoped material of the gate region.

In some embodiments, the Germanium alloy contains a majority of Germanium.

In some embodiments, a system on chip (SoC) includes a processor for processing of data; a memory for storage of data, the memory including dynamic random access memory (DRAM) and non-volatile flash memory; and a transmitter or receiver for the transmission or reception of data. In some embodiments, the system on chip includes one or more CMOS (Complementary Metal-Oxide Semiconductor) device, a first CMOS device including one or both of: one or more nMOS devices (n-type MOSFETs (Metal-Oxide-Semiconductor Field- Effect Transistors)), or one or more pMOS devices (p-type MOSFETs); wherein each of the one or more nMOS devices and one or more pMOS devices includes the following: a Germanium or Germanium alloy channel, a quantum confined channel structure, an optimum crystal orientation for the quantum confined channel structure, and a plurality of threshold voltage options.

In some embodiments, the quantum confined channel structure of an nMOS or pMOS device of the first CMOS device is one of an ultra-thin body structure that is quantum confined in one dimension or a nanowire structure that is quantum confined in two dimensions.

In some embodiments, the nMOS or pMOS device is an ultra-thin body device, and wherein the optimum crystal orientation for the nMOS or pMOS device is a (110) orientation for confinement and a <110> orientation for transport. In some embodiments, the nMOS or pMOS device is a nanowire, and wherein the optimum crystal orientation for the nMOS or pMOS device is a <110> orientation for transport.

In some embodiments, the plurality of threshold voltage options for a nMOS or pMOS device include a low threshold voltage option for high performance operation of the device and a high threshold voltage option for low power operation of the device.

In some embodiments, the Germanium alloy contains a majority of Germanium.

Claims

CLAIMS What is claimed is:

1. A CMOS (Complementary Metal-Oxide Semiconductor) device comprising:

one or both of the following:

one or more nMOS devices (n-type MOSFETs (Metal-Oxide-Semiconductor

Field-Effect Transistors)); or

one or more pMOS devices (p-type MOSFETs);

wherein each of the one or more nMOS devices or one or more pMOS devices includes the following:

a Germanium or Germanium alloy channel,

a quantum confined channel structure,

an optimum crystal orientation for the quantum confined channel structure, and a plurality of threshold voltage options.

2. The device of claim 1, wherein the quantum confined channel structure of an nMOS or pMOS device is one of an ultra-thin body structure that is quantum confined in one dimension or a nanowire structure that is quantum confined in two dimensions.

3. The device of claim 2, wherein the device is an ultra-thin body device, and wherein the optimum crystal orientation for the device is a (110) orientation for confinement and a <110> orientation for transport.

4. The device of claim 2, wherein the device is a nanowire, and wherein the optimum crystal orientation for the device is a <110> orientation for transport.

5. The device of claim 1, wherein the plurality of threshold voltage options for a device include a low threshold voltage option for high performance operation of the device and a high threshold voltage option for low power operation of the device.

6. The device of claim 5, wherein a threshold voltage option of the plurality of threshold voltage options is established by varying a source-drain structure for the device.

7. The device of claim 6, wherein selection of a source-drain structure for high performance operation includes selection of a source-drain structure with high doping of material in a source region and a drain region of the device without gate underlap of lightly doped or undoped material of a gate region of the device into the source region or drain region.

8. The device of claim 6, wherein selection of a source-drain structure for low power operation includes selection of one or both of the following:

a structure with an underlap of lightly doped or undoped material of a gate region of the device into a source region, a drain region, or both of the device, the source region and drain region including highly doped material; or

a structure with a tip region having low doped material in the source region, the drain region, or both, the tip region being between the highly doped material of the source region, drain region, or both, and the lightly doped or undoped material of the gate region.

9. The device of claim 1, wherein the Germanium alloy contains a majority of Germanium.

10. A method of fabrication of a CMOS (Complementary Metal-Oxide Semiconductor) device comprising:

fabricating one or both of:

one or more nMOS devices (n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors)), or

fabricating one or more pMOS devices (p-type MOSFETs);

wherein fabricating each of the one or more nMOS devices or one or more pMOS devices includes the following:

implementation of a Germanium or Germanium alloy channel,

formation of a quantum confined channel structure, the channel structure including an optimum crystal orientation for the structure, and

fabrication of a structure of a source and drain of the device to select one of a plurality of threshold voltage options.

11. The method of claim 10, wherein the quantum confined channel structure of an nMOS or pMOS device is one of an ultra-thin body structure that is quantum confined in one dimension or a nanowire structure that is quantum confined in two dimensions.

12. The method of claim 11, wherein the nMOS or pMOS device is an ultra-thin body device, and wherein the optimum crystal orientation for the nMOS or pMOS device is a (110) orientation for confinement and a <110> orientation for transport.

13. The method of claim 11, wherein the nMOS or pMOS device is a nanowire, and wherein the optimum crystal orientation for the device is a <110> orientation for transport.

14. The method of claim 10, wherein the plurality of threshold voltage options for a device include a low threshold voltage option for high performance operation of the device and a high threshold voltage option for low power operation of the device.

15. The method of claim 14, wherein fabrication of the source-drain structure for high performance operation includes fabrication of a source-drain structure with high doping of material in a source region and a drain region of the device without gate underlap of lightly doped or undoped material of a gate region of the device into the source region or drain region.

16. The method of claim 14, wherein fabrication of the source-drain structure for low power operation includes fabrication of a source-drain structure that includes fabrication of one or both of the following:

17. The method of claim 10, wherein the Germanium alloy contains a majority of

Germanium.

18. A system on chip comprising:

a processor for processing of data;

a memory for storage of data, the memory including dynamic random access memory (DRAM) and non-volatile flash memory; and

a transmitter or receiver for the transmission or reception of data;

wherein the system on chip includes one or more CMOS (Complementary Metal-Oxide Semiconductor) devices, a first CMOS device including one or both of:

one or more pMOS devices (p-type MOSFETs);

a Germanium or Germanium alloy channel,

a quantum confined channel structure, an optimum crystal orientation for the quantum confined channel structure, and a plurality of threshold voltage options.

19. The system on chip of claim 18, wherein the quantum confined channel structure of an nMOS or pMOS device of the first CMOS device is one of an ultra-thin body structure that is quantum confined in one dimension or a nanowire structure that is quantum confined in two dimensions.

20. The system on chip of claim 19, wherein the nMOS or pMOS device is an ultra-thin body device, and wherein the optimum crystal orientation for the nMOS or pMOS device is a (110) orientation for confinement and a <110> orientation for transport.

21. The system on chip of claim 19, wherein the nMOS or pMOS device is a nanowire, and wherein the optimum crystal orientation for the nMOS or pMOS device is a <110> orientation for transport.

22. The system on chip of claim 18, wherein the plurality of threshold voltage options for a nMOS or pMOS device include a low threshold voltage option for high performance operation of the device and a high threshold voltage option for low power operation of the device.

23. The system on chip of claim 22, wherein a threshold voltage option of the plurality of threshold voltage options is established by varying a source-drain structure for the device.

24. The system on chip of claim 18, wherein the Germanium alloy contains a majority of Germanium.