TW548813B - Method for producing circuit device - Google Patents
Method for producing circuit device Download PDFInfo
- Publication number
- TW548813B TW548813B TW091111016A TW91111016A TW548813B TW 548813 B TW548813 B TW 548813B TW 091111016 A TW091111016 A TW 091111016A TW 91111016 A TW91111016 A TW 91111016A TW 548813 B TW548813 B TW 548813B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive
- circuit device
- manufacturing
- item
- patent application
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000011347 resin Substances 0.000 claims abstract description 106
- 229920005989 resin Polymers 0.000 claims abstract description 106
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims description 79
- 238000007789 sealing Methods 0.000 claims description 20
- 238000007747 plating Methods 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 238000001721 transfer moulding Methods 0.000 claims description 5
- 238000007772 electroless plating Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000012528 membrane Substances 0.000 claims description 4
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 3
- 239000001569 carbon dioxide Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 2
- 239000004332 silver Substances 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000010329 laser etching Methods 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000009719 polyimide resin Substances 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 229920006015 heat resistant resin Polymers 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- JYLNVJYYQQXNEK-UHFFFAOYSA-N 3-amino-2-(4-chlorophenyl)-1-propanesulfonic acid Chemical compound OS(=O)(=O)CC(CN)C1=CC=C(Cl)C=C1 JYLNVJYYQQXNEK-UHFFFAOYSA-N 0.000 description 1
- 201000004569 Blindness Diseases 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- -1 but can also use AU Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910001710 laterite Inorganic materials 0.000 description 1
- 239000011504 laterite Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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Description
548813 i、發明說明⑴ ' 【發明之詳細說明】 【發明所屬之技術領域】 本發明係關於一種電路裝置之製造方法,特別是有關 一種使用導電電鍍膜及導電膜之薄型且可實現多層配線之 電路裝置的製造方法。 【習知技術】 近年來,隨著可攜帶型機器、小型化·高密度安裝機 器的風行’習知I c封裝及其安裝概念有相當大的改變。例 如日本特開2 0 0 〇 - 1 3 3 6 7 8號公報中所述。公報中之發明, 係一種採用撓性層之聚醯亞胺樹脂層作為絕緣樹脂層之一 例,之半導體裝置之技術。 第13圖至第15圖為採用撓性層50作為插入式 (interposer)基板之圖面。此外,顯示於各圖上方的圖面 為俯視圖,顯示於各圖下方的圖面為A - A線的剖視圖。 首先在弟1 3圖所示之撓性層5 0的上方,藉由接合劑貼 合銅箔圖案51。該銅箔圖案51配合安裝的半導體元件為電 曰曰體或1C’而有不同的圖案,不過一般多形成接合焊塾 5 1 A、島部51 B。此外,符號5 2為用以從撓性層5 0的内部取 出電極的開口部,該開口部露出有前述的銅箔圖案5 i。 接著,該撓性層5 0係被搬送至晶粒接合裝置,如第!4 圖所示,安裝半導體元件5 3。之後,該撓性層5 0係被搬送 至引線搭接裝置,而接合焊塾51A及半導體元件53的悍塾 則藉由金屬細線5 4進行電性連接。 最後,如第15(A)圖所示,在撓性層50的表面,裝設
麵
313709.ptd 第7頁 548813
、此外,第1 5圖(C)所示之剖視圖,在撓性層5 〇的兩面 形成有電極51A及51D。一般而言,該撓性層5〇之兩面均形 成有圖案並由廠商所提供。 【發明所欲解決之課題】 使用上述之撓性層50之半導體裝置,由於未使用眾所 周知之金屬框架,因而具有實現小型化、薄型的封裝構造 之優點。然而,實際上因其僅利用裝設於撓性層50表面之 一層的銅fl圖案51進行配線,而無法實現多層配線構造。 此外,在製造方法上, 造裝置例如晶粒接合裝置、 置、回流爐等,並旦被安裝 分0 此外’為實現多層配線構造必須保持一定的支持強 度,因此撓性層50必須具有約2 0 0 // m充分的厚度,但如此 一來則導致無法達到薄型化之目的。 撓性層5 0係被搬送至前述之製 引線搭接裝置、移轉模塑裝 &所謂之載物台或工作台的部
548813 五 '發明說明⑶ 薄為9至35//m,如第16圖所不,會產生捲曲而導致搬 惡化’且大幅降低前述之載物台或工作台的安裝性。」 認為此問題是因絕緣樹脂本身過薄所引起的捲曲、或^ 簿圖案51與絕緣樹脂間熱膨脹係數的差異所造成之捲曲1 特別是未使用玻璃布纖維之怒材之堅硬的絕緣材料產 生第1 6圖所示之捲曲時,若再從上 的問題。 上方進订加壓將導致易碎 =外,在開口部52的部分,模塑時因從上方進行加 ^ ’因而造成接合焊墊51A的周邊向上 墊5 1 A的接合性惡化。 從按口坪 此外,構成撓性層5 0的樹脂枯祖士红土 θ ± 竣Α谱“ 材料本身未具有可撓性, A為k同熱傳導性而混入填料時, 態下利用引線搭接裝置進行接合日士 ==:硬。在此狀 縫。此外,在進行移轉模i時:二二接合的部分會產生裂 生裂缝。裂縫如發生在第丨6 a %在杈具抵接的部分亦會產 著。 生在弟16圖所示的捲曲的情況下更為顯 目前為止所說明的撓性層5 〇, 極,但如第1 5圖(C )所示,在接卜/、月面均未形成有電 電極5 1 D。此瞎,㊉’ 撓性層5 0之背面亦可形成 於該製造f置電極51D抵接於前述製造裝置,或抵接
的背面ϊίϊΞ 送裝置的搬送面,因而造成電極51D 因加纨而在if:視於該損傷而作成為電極時,之後會 ^ 牡电極51D本身產生裂縫。 模塑時,會於=11層5 0的背面裝設電極5 1 D,在進行移轉 無法面接觸載物台的問題。此時,如前所
548813 五、發明說明(4) 述撓性層5 0如以堅硬的材料而形成時,電極5 1 D將成為支 點,且對電極5 1 D的周圍朝下方加壓之故,因而使撓性層 5 0產生裂縫。 為解決上述之問題,本發明之發明者提出,使用藉由 絕緣樹脂將較薄的第1導電膜及較厚的第2導電膜加以貼合 之絕緣樹脂層的方案。 然而,為實現多層配線構造在較薄的第1導電膜上形 成有精細圖案,但在較厚的第2導電膜上卻有不適合形成 精細圖案的問題存在。 【用以解決課題之手段】 為解決上述之課題,本發明之電路裝置之製造方法, 係具備以下之步騾:以絕緣樹脂覆蓋導電膜表面的絕緣樹 脂層的準備步驟;於前述絕緣樹脂層的所希望位置的前述 絕緣樹脂形成貫穿孔,選擇性地露出前述導電膜之背面之 步驟;在前述貫穿孔及前述絕緣樹脂表面形成導電電鍍膜 之步驟;將前述導電電鍍膜蝕刻成所希望的圖案以形成第 1導電配線層之步驟,於前述第1導電配線層上進行電性絕 緣以固定半導體元件之步驟;以密封樹脂層覆盡前述第1 導電配線層及前述半導體元件之步驟;將前述導電膜進行 全面性的蝕刻使其變薄後,再將其蝕刻成所希望的圖案以 形成第2導電配線層之步驟;在前述第2導電配線層之所希 望位置形成外部電極之步驟。 因藉由導電膜形成較厚之厚度,因此即使絕緣樹脂的 厚度較薄亦可維持薄板狀的電路基板的平坦性。
313709.ptd 第10頁 548813 五、發明說明(5) 此外,在以密封樹脂層覆蓋第1導電配線層及半導體 元件的步驟完成之前,係以導電膜維持機械性強度,之後 則以密封樹脂層潍持機械性強度,因此利用導電膜即可輕 易形成第2導電配線層。結果,絕緣樹脂無需保持機械性 強度,而能夠使之變薄至足以保持電性絕緣的厚度即可。 此外,由於移轉模塑裝置的下模具可與導電膜整體呈 面接觸,因此可避免產生局部加壓,並且亦可抑制絕緣樹 脂的裂縫的發生。 此外,蝕刻導電膜使其變伯之後,再使第2導電配線 予以圖案化,如此即可一併實現第2導電配線層之精密圖 案化。 【發明之實施形態】 有關本發明之電路裝置製造方法,參照第1圖至第1 2 圖加以說明。 本發明之電路裝置製造方法,係具備以下之步驟:以 絕緣樹脂覆蓋導電膜表面的絕緣樹脂層的準備步驟;於前 述絕緣樹脂層的所希望位置的前述絕緣樹脂形成貫穿孔, 並選擇性地露出前述導電膜背面之步驟;在前述貫穿孔及 前述絕緣樹脂表面形成導電電鍍膜之步驟;將前述導電電 鍍膜蝕刻成所希望的圖案以形成第1導電配線層之步驟; 於前述第1導電配線層上進行電性絕緣以固定半導體元件 之步驟;以密封樹脂層覆蓋前述第1導電配線層及前述半 導體元件之步驟;將前述導電膜進行全面性的蝕刻使其變 薄後,再將其蝕刻成所希望之圖案以形成第2導電配線層
313709.ptd 第11頁 548813 五、發明說明(6) 之步驟;在前述第2導電配線層之所希望位置形成外部電 極之步騾。 本發明之第1步驟係如第1圖所示,在於準備利用絕緣 樹脂2覆蓋導電膜3的表面的絕緣樹脂層1。 絕緣樹脂層1是利用絕緣樹脂2覆蓋導電膜3整體的表 面領域而形成。絕緣樹脂2的材料是由聚醯亞胺樹脂、環 氧樹脂等高分子所組成的絕緣材料所構成。此外,導電膜 3最好使用以Cu為主的材料,或眾所周知的引線架的材 料。 此外,絕緣樹脂層1的形成,首先是在平膜狀的導電 膜3上塗布一層糊狀的聚醯亞胺樹脂,再使其呈半硬化狀 態。因此,絕緣樹脂層1具有不需要補強用的玻璃布纖維 之特徵。 本發明之特點,在於形成一層較厚的導電膜3。 導電膜3的厚度以70至2 0 0 // m的程度為佳,其必須具 有一定的支持強度。 如此’即可藉由導電膜3的厚度維持絕緣樹脂層1的平 坦性,並提升之後步驟的作業性,同時可防止絕緣樹脂2 產生缺陷以及裂鏠等。 絕緣樹脂2係以使用聚醯亞胺樹脂、環氧樹脂等為 佳。以塗漿狀加以塗布使其形成薄片狀之鑄模法,其膜厚 約為1 0 // m至1 0 0 # m的程度。此外,形成薄片狀的樹脂 等,市售的樹脂之最小膜厚多為25/zm的厚度。此外,考 慮到其熱傳導性,其中亦可混入填料。填料可為玻璃、氧
313709.ptd 第12頁 548813 五、發明說明(7) 化石夕 氧化紹、氮化銘、碳化秒、氮化棚等材料。 如上所述’絕緣樹脂2的材料,可從混入有填料之低 熱抵抗樹脂、超低熱抵抗樹脂或聚醯亞胺樹脂等中加以選 擇,並依所形成之電路裝置的性質加以區別使用。 本發明之第2步驟係如第2圖所示,於絕緣樹脂層1的 所希望位置的絕綠樹脂2形成貫穿孔2 1,並選擇性地露出 前述導電膜3的背面。 僅藤出形成有絕緣樹脂2的貫穿孔2 1的部分,並以光 阻劑覆蓋整面。此外,將該光阻劑作為遮罩,利用雷射去 除貫穿孔21正下方的絕緣樹脂2,在貫穿孔2 1的底部露出 導電膜3的背面。雷射的類型係以二氧化碳氣體激光器為 佳。此外,以雷射蒸發絕緣樹脂2之後,於開口部之底部 如留有殘渣時,可以過锰酸鈉驗或過硫酸銨等進行濕式蚀 刻’以去除殘潰。貫穿孔2 1的開口徑,會隨著微影的解像 度而有所變化,在此其開口徑約為5 0至1 〇 〇 // m的程度。 本發明之第3步驟係如第3圖所示,在貫穿孔2 1及絕緣 樹脂2的表面形成有導電電鍍膜4。 在無遮罩的情況下,於包含有貫穿孔2 1的絕緣樹脂2 的整面形成導電電鍍膜4。該導電電鍍膜4係以無電解電鍍 及電解電鍍所形成,在此,則是利用無電解電鍍於至少包 含有貫穿孔2 1的絕緣樹脂2的整面形成2 // m的Cu。如此, 由於導電電鍍膜4及導電膜3為電性導通,因此可再度以導 電膜3作為電極而進行電解電鍍,並電鍍約20/z m的Cu。藉 此,以Cu的導電電鍍膜4埋入貫穿孔21。此外,導電電鍍
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313709.ptd 第13頁 548813 五、發明說明(8) _. :4。或在使此用:採為材料,但亦可採用AU、Ag、Pd等材 才叶&使用遮罩來進行部分電鍍。 二發二 太遒带厅市 固案’以形成第1導電配線層5。 並利用彳ΐΐί鍍膜4上以所希望圖案之光阻劑加以覆蓋, ί中餘刻,形成接合銲塾10以及從接合桿墊10延伸 材料,、1*1«· ^電配線層5。由於導電電鍍膜4是以Cu為主 因蝕刻液以使用氯化第2鐵或氣化第2銅為佳。 導電配電可鑛开膜成之為形成為5至2〇㈣程度,故第1 /日3 了开^成為20//m以下的精細圖案。 10霪^後丄如第5圖所示,使第1導電配線層5的接合銲塾 、::以外層樹脂8覆蓋其他的部分。外層樹脂8是將 =溶解的環氧樹脂等利用網版印刷加以附著,並= 此,,在接合銲墊丨〇上,基於考慮其接合性,而 遮罝U: 的電鍍膜22。該電鑛膜22係以外層樹脂8作為 以導電膜合銲墊1〇上選擇性地施以無電解電鍍,或是 、3為電極而利用電解電鍍使之附著。 之第5步驟係如第6圖所示,於第1導電配線芦5 上進二=性絕緣以固定半導體元件7。 嗥層5 樹脂Γδ 2 Ϊ : 7係直接以裸晶片之狀態利用絕緣性接合 於外層樹脂8上。半導體元件7與在复下面 =弟1 ^電配線層5因利用外層樹脂8而形成緣 第1導電配線層5即使在半導體元件7之下亦可自由^線故
313709.ptd 第14頁 548813 五、發明說明(9) 實現多層配線構造之目的。 此外,半導體元件7的各電極銲墊9係利用接合引線1 1 連接於配設於週邊之第1導電配線層5的其中一部份之接合 銲墊10上。半導體元件7亦可以面朝下的方式來安裝(參 考第12圖)。此時,於半導體元件7的各電極銲墊9的表面 裝設有銲球或泵,而在絕緣樹脂層1的表面,與銲球位置 相對應的部分則装設有與接合銲墊1 0相同的電極。 以下說明有關在引線接合時,使用絕緣樹脂層1的優 點。一般而言,在進行Au線的引線接合時,係將溫度加熱 至200。<3至300 QC 。此時,如果導電膜的膜厚較薄,將導致 絕緣樹脂層1產生捲曲的現象,在此狀況下,透過壓接頭 對絕緣樹脂層1進行加壓時,絕緣樹脂層1有可能會產生龜 裂的現象。此外,於絕緣樹脂2中混入填料時,將使材料 本身變得更為堅實而喪失柔軟性,並且使龜裂的現象更為 顯著。 本發明之第6步驟係如第7圖所示,以密封樹脂層1 3覆 蓋第1導電配線層5及半導體元件7。 絕緣樹脂層1係安裝於模塑裝置以進行樹脂模塑。模 塑的方法可採用移轉模塑法、射出成形、塗布、浸潰等方 法。但若考量其量產性,則以移轉模塑法及射出成形較為 理想。 在本步驟中,絕緣樹脂層1必須以面抵接於模塑槽的 下模具,而較厚的導電膜3會發揮該項功能。此外,從模 塑槽取出後,到密封樹脂層1 3的收縮完全結束為止,係利
313709.ptd 第15頁 548813
用導電膜3來維持封裝的平坦性。 與匕亦即’到本步驟為止導電膜3擔負了機械性支持絕緣 樹脂層1的角色。 本發明之第7步驟係如第8圖及第9圖所示,整面蝕刻 ¥電膜3使其變薄後’蝕刻成所希望的圖案以形成第2導電 配線層6。 如第8圖所π ’在無遮罩的情況下將導電膜4整面蝕刻 使其變薄。餘刻的方式可採用使用氯化第2鐵或氯化第2銅 的化學钱刻法’而第2導電膜4的厚度會由原先的7〇至200 # m程度變薄為約一半厚度的35 # ^左右。此時,即可去除 在先前的步驟中附著於第2導電膜4的刮痕。
以下如第9圖所示,導電膜3係由具有所希望之圖案合 光阻劑所覆蓋’並利用化學蝕刻形成第2導電配線層6。_ 2導電配線層6與第1導電配線層5透過貫穿孔2 1進行電性每 接以實現多層齡線構造。此外,必要時可在空白的部分开 成用以交差第1導電配線層5的第2導電配線層6。 衣發明之第8步驟係如第1 〇圖所示,於第2導電配線^ 6的所希望位f形成外部電極1 4。 、' 第2導電酞線層6係將形成有外部電極1 4的部分露出, 並以網版印刷羼理以溶劑溶解後的環氧樹脂等,^ ’ 外層樹脂1 5覆篸其大部分。接著藉由銲錫回流或^ ^ 以 網版印刷,在讀藤出部分同時形成外部電極1 4。干;,的 最後,由於在絕緣樹脂層1中之電路裝置係形成 數矩陣狀,因冰可將密封樹脂層13及絕緣樹脂層丄加二二
548813 五、發明說明⑴) 割,並將其分散於各個電路裝置。 裝置參ϊΠϊ:月將本發明之製造方法具體化之電路 顯示的圖案為第;導線線顯:線 的/6案,f導1 :線配線層5,虛線 半…件7之方式接係:〜繞 應。接合鋒塾1 * 墊的半導體元件7相對 =電極銲墊9相連由接合引線11與半導體元件7所對應 、登相連接,精細圖案的第1導 …Η多數延伸至半導體元件二導方電配上= 所示,貫穿孔21與第2導電配線層6相連接。並藉由以黑點 /彼藉述之構造,即使具有200以上的銲墊的半導體 2 12用苐1導電配線層5的精細圖案以多層配線構 ^ 希望之第2導電配線層6,俾從裝設於第2導電 龄線層—6之'部電極14連接至外部電路。 f y 2圖係顯示半導體元件7以面朝下的方式安裝的構 遠φ、第j 〇圖共通的構成要素標示相同的符號。半導體元 件i裝叹有凸起電極3 1,該凸起電極3 1係與接合焊墊1 0 1 q接〔外層樹脂8與半導體元件7之間的縫隙係以充填樹 如加以充填。此構造可省去接合引線,同時可使密封樹 月0曰的、厚度隻知更溥。此外,外部電極1 4亦可藉由餘刻導 €膜3並以金或把電鍍膜33覆蓋其表面的凸起電極來達 成。 【發明之效果】 本發明具有以下之優點。
548813
五、發明說明(12) 第1,在利用密封樹脂層進行模塑之前,可利用導電 膜消除絕緣樹月曰層之捲曲’並提升搬送性。 第2 ’由於利用二氧化碳氣體激光器於絕緣樹脂上形 成貫穿孔後’再形成用以形成第1導電配線層的導電電錢 膜,因此可實現與第2導電配線層間的多層連接,並使歩 驟變得更為簡單。 ^ 第3,可溥層地开> 成用以形成第1導電配線層之導電 鍍膜,並且可使第1導電配線層形成更為精細的圖案。
第4,至形成密封樹脂層為止,利用導電膜進行絕緣 樹脂層的機械性支持,而在第2導電配線層形成後,利用 密封樹脂層進行絕緣樹脂層的機械性支持,因此不論絕 樹脂的機械性強度,均可實現薄型的安裝方法。 # 第5,即使絕緣樹脂本身為堅硬的物質,或因混入 料而成為堅硬的物質,由於其係利用導電膜加以支撐,、 此在製造步驟中可提高絕緣樹脂層本身 裂縫的發生。 丁一丨王亚防i 展刹第爾6 a由於導電膜形成較厚之膜厚,因此可將絕緣樹 一曰利用為進行晶片的晶粒接合、引線接合、及密封 =件時的支撐基板。同時,即使絕緣樹脂材料
能夠提升進行引線接合時的能量搬移,同時也 夠挺升引線的接合性。 传盆Ϊ L’/、2導電膜係於利用密封樹脂層進行模塑後, 的f二二^半而進行餘刻,因此即可實現第2導電配線^ 、月、、回”化,使其與第1導電配線層同時實現極精細围
313709.ptd 第18頁 548813 五、發明說明(13) 案的電路裝置。 B· 313709.ptd 第19頁 548813 圖式簡單說明 【圖面之簡單說明】 第1圖為說明本發明之電路裝置之製造方法之剖視 圖。 第2圖為說明本發明之電路裝置之製造方法之剖視 圖。 第3圖為說明本發明之電路裝置之製造方法之剖視 圖。 第4圖為說明本發明之電路裝置之製造方法之剖視 圖。 第5圖為說明本發明之電路裝置之製造方法之剖視 圖。 第6圖為說明本發明之電路裝置之製造方法之剖視 圖。 第7圖為說明本發明之電路裝置之製造方法之剖視 圖。 第8圖為說明本發明之電路裝置之製造方法之剖視 圖。 第9圖為說明本發明之電路裝置之製造方法之剖視 圖。 第1 0圖為說明本發明之電路裝置之製造方法之剖視 圖。 第11圖為說明本發明所製造之電路裝置之俯視圖。 第1 2圖為說明本發明之電路裝置之製造方法之剖視 圖0 11^ 313709.ptd 第20頁 548813 圖式簡單說明 第13圖為習知之半導體裝置之製造方法之說明圖。 第14圖為習知之半導體裝置之製造方法之說明圖。 第1 5(A)至(c)圖為習知之半導體裝置之製造方法之說 明圖。 第1 6圖為習知之撓性層之說明圖。 【元件符號說明】 1 絕 緣 樹 脂層 2 絕 緣 樹 脂 3 導 電 膜 4 導 電 電 鍍 膜 5 第 1導電配線層 6 第 2導電配線層 7 半 導 體 元件 8 外 層 樹 脂 9 電 極 銲 塾 10 接 合 銲 墊 11 接 合 引 線 13 密 封 樹 脂 層 14 外 部 電 極 15 外 層 樹 脂 21 穿 孔 22 電 鍍 膜 31 凸 塊 電 才虽 32 充 填 樹 脂 33 電 鍍 膜 50 撓 性 層 51 銅 箔 圖 案 51 A 接 合 焊 塾 51B 島 部 51D 電 極 52 開 Π 部 53 半 導 體 元 件 54 金 屬 細 線 55 密 封 樹 脂 56 連 接 裝 置
313709.ptd 第21頁
Claims (1)
- 548813 六、申請專利範圍 1. 一種電路裝置之製造方法,係具備··以絕緣樹脂覆蓋 導電膜表面的絕緣樹脂層的準備步驟; 於前述邑緣樹脂層的所希望位置的前述絕緣樹脂 上形成貫穿孑L,並選擇性地露出前述導電膜背面之步 驟 ; 在前述貫穿孔及前述絕緣樹脂表面形成導電電鍍 膜之步驟; 將前述導電電鍍膜蝕刻成所希望的圖案以形成第1 導電配線層之步驟; 於前述第1導電配線層上進行電性絕緣以固定半導 體元件之步驟; 以密封樹脂層覆蓋前述第1導電配線層及前述半導 體元件之步驟; 將前述導電膜進行全面性的蝕刻使其變薄後,再 將其蝕刻成所希望的圖案以形成第2導電配線層之步 驟 ; 在前述第2導電配線層之所希望的位置形成外部電 極之步驟。 2. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述導電膜及前述導電電鍍膜係由銅所形成。 3. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述導電電鑛膜係形成為較薄之膜厚,並將前述第1導 電配線層予以微細圖案化。 4. 如申請專利範圍第1項之電路裝置之製造方法,其中,313709.ptd 第22頁 548813 六、申請專利範圍 前述導電電鑛膜係形成為較厚之膜厚,並且在以前述 密封樹脂層加以覆蓋的步驟之前,利用前述導電膜以 機械式方式支撐。 5. 如申請專利範圍第1項之電路裝置之製造方法,其中, 在以前述密封樹脂層加以覆蓋的步驟完成後,利用前 述密封樹脂層以機械式方式支撐。 6. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述貫穿孔雷射蝕刻前述絕緣樹脂。 7. 如申請專利範圍第6項之電路裝置之製造方法,其中, 前述雷射蝕亥U係使用二氧化碳氣體激光器。 8. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述導電電鑛膜係利用前述導電金屬的無電解電鍍及 電解電鍍形成於前述貫穿孔及前述絕緣樹脂的表面。 9. 如申請專利範圍第1項之電路裝置之製造方法,其中, 在形成前述第1導電配線層後,留下所希望的部分並以 外層樹脂加以覆蓋。 1 0.如申請專利範圍第9項之電路裝置之製造方法,其中, 在從前述第1導電配線層的前述外層樹脂露出之部分形 成金或銀的電鑛層。 1 1 .如申請專利範圍第9項之電路裝置之製造方法,其中, 前述半導體元件固定於前述外層樹脂上。 1 2.如申請專利範圍第1項之電路裝置之製造方法,其中, 利用接合引線將前述半導體元件的電極與前述金或銀 的電鍍層予以連接。313709.ptd 第23頁 548813 六、申請專利範圍 13. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述密封樹脂層係以移轉模塑法而形成。 14. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述導電膜在沒有遮罩的情況下進行全面均勻蝕刻使 其變薄。 15. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述第2導電配線層的大部分係由外層樹脂所覆蓋。 16. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述外部電極係利用銲錫的網版印刷附著銲錫,並進 行加熱熔融而形成。 17. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述外部電極係利用銲錫的回流而形成。 18. 如申請專利範圍第1項之電路裝置之製造方法,其中, 前述外部電極係將前述導電膜蝕刻為所希望的圖案並 在其表面進行金或把電鍍而形成。313709.ptd 第24頁
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JP2001185423A JP2003007917A (ja) | 2001-06-19 | 2001-06-19 | 回路装置の製造方法 |
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KR100642194B1 (ko) * | 2001-06-19 | 2006-11-03 | 산요덴키가부시키가이샤 | 회로 장치의 제조 방법 |
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DE10250621B4 (de) * | 2002-10-30 | 2004-09-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Erzeugen verkapselter Chips und zum Erzeugen eines Stapels aus den verkapselten Chips |
DE102004005586B3 (de) * | 2004-02-04 | 2005-09-29 | Infineon Technologies Ag | Halbleiterbauteil mit einem Halbleiterchipstapel auf einer Umverdrahtungsplatte und Herstellung desselben |
JP2006059992A (ja) * | 2004-08-19 | 2006-03-02 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
JP2007087975A (ja) * | 2005-09-16 | 2007-04-05 | Ricoh Co Ltd | 半導体装置 |
KR100744146B1 (ko) | 2006-08-08 | 2007-08-01 | 삼성전자주식회사 | 연성 접속판을 이용하여 배선 기판과 칩을 연결하는 반도체패키지 |
US20090223700A1 (en) * | 2008-03-05 | 2009-09-10 | Honeywell International Inc. | Thin flexible circuits |
JP5042297B2 (ja) * | 2009-12-10 | 2012-10-03 | 日東電工株式会社 | 半導体装置の製造方法 |
TWI392066B (zh) * | 2009-12-28 | 2013-04-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
KR101350435B1 (ko) | 2012-04-26 | 2014-01-16 | 하나 마이크론(주) | 집적회로 소자 패키지 및 이의 제조 방법 |
BR112014026170A2 (pt) | 2012-04-26 | 2017-07-18 | Hana Micron Co Ltd | pacotes de dispositivo de circuito integrado e métodos de fabrico de pacotes de dispositivo de circuito integrado |
JP6923299B2 (ja) * | 2016-09-26 | 2021-08-18 | 株式会社アムコー・テクノロジー・ジャパン | 半導体装置及び半導体装置の製造方法 |
US20200395272A1 (en) | 2019-06-11 | 2020-12-17 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and method of manufacturing a semiconductor device |
KR20230019650A (ko) * | 2021-08-02 | 2023-02-09 | 엘지이노텍 주식회사 | 회로기판 |
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JP2003007917A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
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CN1186808C (zh) | 2005-01-26 |
US7141509B2 (en) | 2006-11-28 |
KR20020096971A (ko) | 2002-12-31 |
US20020192857A1 (en) | 2002-12-19 |
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US20040198050A1 (en) | 2004-10-07 |
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