TW543173B - Lead frame, semiconductor device using the same and method of producing the semiconductor device - Google Patents
Lead frame, semiconductor device using the same and method of producing the semiconductor device Download PDFInfo
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- TW543173B TW543173B TW091111605A TW91111605A TW543173B TW 543173 B TW543173 B TW 543173B TW 091111605 A TW091111605 A TW 091111605A TW 91111605 A TW91111605 A TW 91111605A TW 543173 B TW543173 B TW 543173B
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Description
543173 五、發明說明(1) 【發明背景】 1 · 發明領域 本餐明係關於一種引線框架、使用此弓丨線框架之半導 體裝置、及半導體裝置之製造方法。 2.相關技藝之說明 _ 使半導體裝置緻密安裝於電路板中之半導體裝置之微 小化需求與曰倶增。為了降低半導體裝置之尺寸,時常使 用QFN(Quad Flat Non-leaded Package ,四方平坦無引線 封裝)、S0N(Small 〇utline Non_leaded Package^、,,、小輪 廓無引線封裝)、以及其他所謂的無引線封裝。雖然益 線封裝如同習知的半導體裝置使用引線框架,但1使… 框架從半導體料之底面突出,藉以降低安裝面積使引線 诊從電路板上方看不見外界電極之無引線封裝令人& :二:而’當引線框架需要從半導體封裝之二 應该儘可能地抑制突出程度。 大出¥, 對於使用無引線封裝之半導體裝置而古,每 在製造中藉由樹脂片保護外部電極。具俨古之,乂通常 樹月旨密封承載有半導體晶片並遭受配線‘二的二,片於 m ^止樹脂漏出,藉以確保後續之電鍍。因而,樹浐^架時 半導體裝置或產品之構成元件。因$ pi曰片益非 曰加丰導體哀置之製造成本,使得降乂其 加啟切。 $低製&成本之需要更 再者,纟習知的半導體裝置中,弓丨線權架中構成電極
第4頁 543173 五、發明說明(2) 部之部分露出於封步 y τ Τ衣之側面上。因此杏*、皆 側之方式安裝至雷跋士士 田半導體裝皆 Λ Μ μ 4 >電路板守,必須保證足夠置以侧對 甶於例如相鄰丰寡鲈 幻見的空戸弓 半導_ # # 2 ί 置間之焊料所w起之銪^間以避免 牛導體衣置緻雄、安裝至電路板。 丑路。此阻礙 【發明概述】 本發明之一目的在於提供一 成本降低與緻密安裝、使用此引 半導體裝置之製造方法。 依據本發明,本發明之引線 一實質上平坦的底面;以及一島 該基部之頂面一體成形。 且,依 裝有一 配線連 電極。該島部 每一個係部分 更且,依 以使一引線框 上,其開始於 線框架 半導體 樹脂密 括該島 據本發明, 半導體晶片 接至形成於 與該複數個 地從該密封 據本發明, 架之表面部 一安裝步驟 中之一島部 晶片之表面 封該引線框 部、該半導 一種半 ;以及 該半導 電極部 樹脂之 一種半 分地露 ,用以 上。藉 上之複 架之頂 體晶片 種引線框架,徐 線框架之半著: 框架包括··一其 部與-電極部T 具有 W分地和 導體裝置包括·— 複數個電極部,it部* 表面上之複數個t由街封樹脂所密封同時 底面突出。 導體裝置之製造方法,用 出於該半導體裝置之底面 ,裝一半導體晶片至包括 著複數條接合配線連接形 數個電極與一電極部。藉 面之一部分與底面之一部 、该電極部、以及該接合 曝 第5頁 543173 五、發明說明(3) 配線。繼而,以平行該引線框架之該底面之方式研磨該密 封樹脂之位於該引線框架下方之整個表面。最後,使該引 線框架之該底面之一部分露出於該密封樹脂之底面上。 【較佳實施例之詳細說明】 本發明之前述與其他目的、特徵、以及優點將因下文 附有圖示之詳細說明而更加明顯。 為更佳地瞭解本發明,將說明習知的使用引線框架之 _ 半‘體I置及其製造方法。圖1係顯示習知的具有無引線 封裝組態之半導體裝置5。如圖所示,半導體裝置5包括構 成引線框架1之島部1 3與電極部1 2。島部1 3與電極部1 2皆 部份地露出至密封樹脂3之外,形成外部電極4。半導體晶 片2經由例如銀膠或Au-Si共熔合金所進行之接合而安裝於 島部13之頂面。藉由密封樹脂3使半導體晶芊 1密封在一起。 ,、Ή踝I木 金配線或類似的接合配線21連接著排列於半導 Λ頂面上之電極與形成電極部12之引線框架。「頂面曰」 :“密封樹脂3所密封之半導體裝置5 、 同樣地,下文將出現的「底面」係指半導:表一面 面,其中外部電極4於該表面處露出至'^ 义 半導體裝置5安裝至未圖示的電路 成者忒表面於 面。如前所述,外部電極“== =電路板之表 部12之底面上。島部13與電極部12因卩&面上與電極 茲將參照圖2A至2F說明圖i所大'f裝之外。 所不之丰導體裝置5之製造
第6頁 五、發明說明(4) 。首先,如圖2A所示,包括有島部13與 ^框架1藉著使預計將形成外部電極 ^ 頂面。如圖2Β所示,樹脂片6黏附至外二至島广3之 侍經由安置樹脂片使之成為黏附表 4之底面。此 框架1至樹月旨片6们寻㈣寸表面與朝’然後黏附引線 對,隨後經由接合使半導體晶片之底面彼此面 完成。繼而,如圖2C所示,在半至島部^之頂面而 極與電極邱】2之頂而Μ丄社人 隨曰日片2之頂面上之電 电枉412之頂面猎由接合配線2 ^ 如圖2D所示,在配線接合步驟 連接 之引線框架1與半導體晶片2由宓後,位於樹脂片6上 時’樹脂片6 P方止密封樹脂3漏:外:::3 :封在-起。此 而,如圖2E所示’樹脂片6從封繁。電極4之底面。繼 示,除了外部電極4向下突出之Γ剝離。最後,如圖2F所 ^。此後接著切割密封樹脂3:::二裝之底面气 +導體裝置5。 辦引線框架1,藉以完成 如前所述,在半導體裝置5 部電極4。具體言之,當承載1造中,樹脂片6保護外 由密封樹脂3所密封時,樹脂片6導體晶片2之引線框架1 保電鍍步驟。然而,樹脂片1曰主方止樹脂3漏出,藉以確 造成本。 Φ貝且増加半導體裝置5之製 3Β係 視圖 參照圖3Α與3Β, 分別顯示專用以 與側剖面圖。下 說明實施本發明 闡明實施例之單 文中所出現的「 之引線框架。圖3Α與 位引線框架1之頂面 頂面」與「底面」係 543173 五、發明說明(5) 分別指面對著其上將安裝引線框架與使用引線框架之半、曾 體裝置的電路板之表面以及對向於前述表面之表面。 ^ 如圖3 A與3 B所示’引線框架包括一對基部1 1與延伸於 一個基部1 1上方之一島部1 3。引線框架1係由金屬所形; 成。電極部12係形成於基部11上。具體言之,電極部^與 島部1 3應該最好形成於基部1 1之頂面上和基部丨丨一體成 型。
在圖3 A所示之引線框架1中,未圖示的半導體晶片將 安置於每一島部1 3上。因而,引線框架1通常係建構成同 ^製造二個半導體裝置。具體言之,基部U突出至引線框 架1之外部。因而,如圖3 B所示,電極部丨2與島部i 3之側 剖面通常為L形。 、雖然在圖3 A與3 B中每一島部1 3被顯示成從基部11突出 或:么吊路出其底面’但此一組態僅為闡示用。關鍵點係 基f 11之頂面露出於引線框架1外部與島部丨3間以及引線 框架1外部與電極部12間。「外部」係指預計將形成單一 半導體封裝之引線框架之末端方向,亦即,有關將被密封 之引,框架中之得形成半導體封裝之表面之末端。
制i兹將參照圖4至11說明使用引線框架1之半導體裝置之 衣& 1寺定程序。圖4 A係顯示具有圖3 A所示之組態之二個引 線框架1,以側對側方式配置於一對基部11之相對側。圖 係底面視圖,而圖4C與4D係侧剖面圖。如圖4 A所示,該 、 狂序猎由將圖3A之引線框架1作為一單元來處理而製 造半導體裝置。
第8頁 543173 五、發明說明(6) --- 首先,如圖5A至5C所示,半導體晶片2藉著銀膠、 Au-Si共晶合金、或類似的接合之媒介而安裝至每一島部 13。繼而,形成於半導體晶片2之表面上之電極與引線框 架1之電極部1 2藉由接合配線而連接。 如圖6 A至6D所示,如前所述,承載有半導體晶片2之 引線框架1由密封樹脂3所密封。本發明之程序之特徵之一 係藉著密封樹脂3密封包括其底面之整個引線框架1。 如圖7A至7C所示,完全由密封樹脂3所密封之引線框 架1 (下文稱為半導體封裝)從底面處開始研磨。當引線框 架1已路出至外界時停止研磨。繼而,在涵蓋圖8 A中之粗 體點虛線所指示之區域上方進行半導體封裝之半切切割 (half-cut dicing)。圖 8B 與 8(:係沿著圖 8A 之線 A —A,與 B-B之剖面,係顯示切割而成的半導體封裝。如圖8β所 示’以島部1 3之底面受保護之方式切割封裝之底面上之密 封樹脂3。亦且,如圖8C所示,島部丨3係建構成連接一對 基部11 ’使得密封樹脂3係以島部1 3之底面受保護之方式 被切割,如同圖8 β 一般。 如圖9Α所示,藉由半切切割步驟而露出於封裝之底面 上之基部丨丨之表面遭受電鍍。此時,如圖9Β與9C所示,島 部1 3之底面未受到電鍍。 在電鑛步驟之後,再次在涵蓋圖1 〇 Α之粗體點虛線所 指示之區域上方進行該封裝之半切切割。具體言之,形成 有電極部1 2之基部11與形成有電極部丨2與島部丨3之基部 11 ( %纟繫部分)被半切切割。結果,密封樹脂3依據電極部
第9頁 543173 五、發明說明(7) 12存在之區域而露出於封裝之底面上。以此方式,本發明 之程序使引線框架1之將露出於封裝之侧面之突出部形成 於封裝之底面上。此允許在用於形成外部電極且用於移除 前述突出部時之蝕刻作用於相同之方向。 μ 圖10Β與10C係分別沿著圖1(U之線Α_Α,與Β —Β,之剖 面。如圖所示,前述程序可形成外部電極4於封裝之底面 上,無須擔心露出於封裝之側面上之引線框架丨。此係因 為將依據電極部1 2之組態而切割之基部丨丨之突出部在 電極4形成之前即形成。 口 最後,如圖1 1 Α至1 1 D所示,密封樹脂3受到全切切判 (一fuU-cut dicing),藉以製造半導體裝置5。圖ΐΐβ係顯 不將被全切切割之區域,亦即,由粗體點虛線之,、, 域之底視圖。圖11A係顯示封裝中之切割分 視圖。圖11B與11C係分別沿著圖11A之線a_a,與B — B刀
面。 乂^口 J 如圖11C^1D所不,相較於外部電極 雨述程序提供邊劑部份給僅有密封樹脂3 伤, 而可基於例如全切切割位置而提供且隹夂邛伤。因 之封裝。倘若密封樹脂3之全切切割*译可所期望之尺寸 半切切割寬度,則引線框架1之—部:;二於引線框架1之 的半導體裝置之側Φ;倘若前者寬度m在最^產生 引線框架1之一部分可露出於半導體裝置、曼者見度,則 前述的研磨、半切切割、半切與之伽I面。 互替換,以配合於所期望的半導體裝置。、刀割技術得相
543173 五、發明說明(8) 綜上所 架之半導體 所未見之優 (1 )應 可用來防止 迄今為止用 著地降低製 (2) 引 相鄰半導體 (3) 電 具有足夠大 半切切割係 研磨密封樹 然後研磨密 間。全切切 (4) 每 極部之部份 接在一起之 底面間之位 (5) 由 脂片之需要 (6) 不 基於半切切 (7) 電 述’本發明提 裝置、及半導 點’列舉如下 用至引線框架 引線框架露出 來保護外部電 造成本。 線框架並未部 裝置間之距離 極部與島部係 的強度來抵抗 指設定一預先 脂,例如:藉 封樹脂之底面 割係指切割密 一基部係由下 、一其上形成 部分。此連接 置關係。 切割或研磨所 ,因而降低製 僅半導體裝置 割寬度而自由 鑛係於半切切 供一種 體裝置 〇 之底面 於半導 極之昂 分地從 ,藉以 與基部 半切切 選擇的 著密封 以形成 封樹脂 列元件 有島部 部分確 引線框架 之製造方 用以形成 體裝置之 貴樹脂片 封裝之側 促進緻密 一體成型 吾! J、磨 深度然後 樹脂密封 一間距於 、N使用此引線框 具有各種前 h #電極之钱刻 側面上。此消除 之需要,藉以顯 面突出。此降低 安裝。 W線框架因而 或類似製程。 士刀割引線框架或 整個引線框架, 露:出的外部電極 所組成:一其上形成有電 之部份、以及一將他們連 保電極部之底面與島部之 形成的外部電極亦消除了昂貴樹 造成本。 可緻密地排列於電路板上,亦可 選擇間距。 割之後應用至基部,因而僅應用 543173
第12頁
543173 圖式簡單說明 圖1係顯示習知的引線框架與使用習知的引線框架之 半導體裝置之剖面圖; 圖2A至2F係顯示製造習知的半導體裝置之各順序之步 驟; 圖3A與3B係顯示實施本發明之引線框架之圖;以及 圖4A 至4D 、5A 至5C 、6A 至6D 、7A 至7C 、8A 至8C 、9A 至 9C、10A至10C、以及11A至1 1D係顯示使用圖3A與3B之引線 框架之半導體裝置之製造之特定程序。 【符號說明】 1 引線框架 2 半導體晶片 3 樹脂 4 外部電極 5 半導體裝置 6 樹脂片 11 基部 12 電極部 13 島部 21 接合配線
Claims (1)
- 543173 六、申請專利範圍 1. 一種引線框架,包含: 一基部,具有一實質上平坦的底面;以及 一島部與一電極部,部分地和該基部之一頂面一體形 成。 2. —種引線框架,包含: 一對基部,其中每一個具有一實質上平坦的底面; 一對電極部,其中每一個至少部分地和該對基部中之 一個之一頂面一體成形;以及 馨 一島部,至少部分地和該對基部之二頂面一體成形, 使該二頂面彼此連接。 3. 如申請專利範圍第1項之引線框架,其中該對基部之每 一個係由下列元件所組成:一位於該島部下方之部份;一 位於該對電極部中相關連之一個之下方之部份;以及一連 接前述二部分之部份。 4. 一種半導體裝置,包含: Φ 一島部,其上安裝有一半導體晶片;以及 複數個電極部,藉由複數條接合配線連接至形成於該 半導體晶片之一表面上之複數個電極; 其中該島部與該複數個電極部係由密封樹脂所密封, 同時每一個係部分地從該密封樹脂之一底面突出。第14頁 543173 六、申請專利範圍 5. 一種半導體裝置之製造方法,用以使一引線框架之一 表面部分地露出於該半導體裝置之一底面上,該方法包含 下列步驟: 安裝一半導體晶片至包括於該引線框架中之一島部 上; 藉著複數條接合配線連接形成於該半導體晶片之一表 面上之複數個電極與一電極部; 藉著密封樹脂密封該引線框架之一頂面之一部分與一 底面之一部分,包括該島部、該半導體晶片、該電極部、 以及該接合配線; 以平行於該引線框架之該底面之方式研磨該密封樹脂 之位於該引線框架下方之整個表面;以及 使該引線框架之該底面之一部分露出於該密封樹脂之 一底面上。 6. 如申請專利範圍第5項之半導體裝置之製造方法,其中 該引線框架包含:一基部,具有一實質上平坦的底面,並且 該島部與該電極部係部分地和該基部之一頂面一體成 形。 7. 如申請專利範圍第5項之半導體裝置之製造方法,其中 該引線框架包含: 一對基部,其中每一個具有一實質上平坦的底面;第15頁 543173 六、申請專利範圍 一對電極部,其中每一個至少部分地和該對基部中之 一個之一頂面一體成形;並且 該島部至少部分地和該對基部之二頂面一體成形,使 該二頂面彼此連接。 8. 一種半導體裝置之製造方法,用以使一引線框架之一 表面部分地露出於該半導體裝置之一底面上,該方法包含 下列步驟: 安裝一半導體晶片至包括於該引線框架中之一島部 上; 藉著複數條接合配線連接形成於該半導體晶片之一表 面上之複數個電極與一電極部; 藉著密封樹脂密封該引線框架之一頂面之一部分與一 底面之一部分,包括該島部、該半導體晶片、該電極部、 以及該接合配線; 以平行於該引線框架之該底面之方式研磨該密封樹脂 之位於該引線框架下方之整個表面;以及 使該引線框架之該底面之一部分露出於該密封樹脂之 一底面上; 半切切割該島部之一底面; 電鍍露出於該半導體裝置之該底面上之該引線框架之 該底面與該島部之該底面;以及 藉由半切切割方式切割一連接部分,該連接部分係形 成該引線框架之一基部之一部分。第16頁 543173 六、申請專利範圍 9. 如申請專利範圍第8項之半導體裝置之製造方法,其中 該引線框架包含: 一基部,具有一實質上平坦的底面,並且 該島部與該電極部係部份地和該基部之一頂面一體成 形。 10. 如申請專利範圍第8項之半導體裝置之製造方法,其 中該引線框架包含: 一對基部,其中每一個具有一實質上平坦的底面; 一對電極部,其中每一個至少部分地和該對基部之一 頂面一體成形;並且 該島部至少部分地和該對基部之二頂面一體成形,使 該二頂面彼此連接。第17頁
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JP4611569B2 (ja) * | 2001-05-30 | 2011-01-12 | ルネサスエレクトロニクス株式会社 | リードフレーム及び半導体装置の製造方法 |
KR20030093774A (ko) * | 2002-06-05 | 2003-12-11 | 광전자 주식회사 | 리드프레임, 상기 리드프레임을 이용한 칩 스케일 반도체패키지 및 그 제조방법 |
JP3942500B2 (ja) * | 2002-07-02 | 2007-07-11 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
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KR101041199B1 (ko) * | 2007-07-27 | 2011-06-13 | 엔지케이 인슐레이터 엘티디 | 세라믹 성형체, 세라믹 부품, 세라믹 성형체의 제조 방법및 세라믹 부품의 제조 방법 |
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- 2002-05-30 US US10/156,812 patent/US20020180011A1/en not_active Abandoned
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KR100491657B1 (ko) | 2005-05-27 |
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JP2002359338A (ja) | 2002-12-13 |
US20050032271A1 (en) | 2005-02-10 |
US20020180011A1 (en) | 2002-12-05 |
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