TW535272B - Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board - Google Patents
Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board Download PDFInfo
- Publication number
- TW535272B TW535272B TW091105169A TW91105169A TW535272B TW 535272 B TW535272 B TW 535272B TW 091105169 A TW091105169 A TW 091105169A TW 91105169 A TW91105169 A TW 91105169A TW 535272 B TW535272 B TW 535272B
- Authority
- TW
- Taiwan
- Prior art keywords
- redistribution
- substrate
- board
- plate
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 150
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 59
- 239000000758 substrate Substances 0.000 claims description 92
- 238000000034 method Methods 0.000 claims description 59
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 239000010949 copper Substances 0.000 claims description 35
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 33
- 229910052802 copper Inorganic materials 0.000 claims description 32
- 229920005989 resin Polymers 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 23
- 238000004806 packaging method and process Methods 0.000 claims description 19
- 238000007747 plating Methods 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 14
- 238000000926 separation method Methods 0.000 claims description 13
- 239000000919 ceramic Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- IOLCXVTUBQKXJR-UHFFFAOYSA-M potassium bromide Chemical compound [K+].[Br-] IOLCXVTUBQKXJR-UHFFFAOYSA-M 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- 239000007921 spray Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 229910000831 Steel Inorganic materials 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 229910052700 potassium Inorganic materials 0.000 claims 1
- 239000011591 potassium Substances 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 239000010959 steel Substances 0.000 claims 1
- 239000004575 stone Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 229910052697 platinum Inorganic materials 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000004299 exfoliation Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910015363 Au—Sn Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011532 electronic conductor Substances 0.000 description 2
- 239000012776 electronic material Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002241 glass-ceramic Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 241000238631 Hexapoda Species 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000003504 photosensitizing agent Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002195 soluble material Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
535272 五、發明説明(!) L發明領域 乂本尽明一般係有關安裝一邏輯元件與需要高速處理 之一似物的半導體裝置’且更特別在於封裝中併有一被動 元件(諸如一電容器)之半導體裝置。 2 ·相關技藝之說明 通*,在安裝高速運作之LSI(大規模積體電路)的一半 導體裝置中,一旁路電容器係併入一封裝板之中,以防止 f於高頻雜訊所引起電力供應電壓之變化與故障,並確保 高速運作區域中的穩定運作。 a旁路電容器係安置於該封裝板之上,成為與藉由覆晶 女裝(FC安裝)安裝在該封裝板上之半導體元件不同的晶 片。為了使該旁路電容器有效率地運作,其需要將該旁路 電容器放置在接近半導體元件之處。在許多案财,該旁 路電容器係放置在㈣於封m分的相反側,半導體 元件係安置於該部件之上。 源 然而,當放置供許多信號使用的安置終端與用於電你 =及接地的安置終端,或是複數個半導體元件係安置於封 裝板上,成為-系統内建式封裝(system_inpMka⑽時,其 係難以獲得用以將該旁路電容器安置在封裝板上、且接^ 安置該半導體元件之邱公的 仟之#刀的—面積。因此係提出-種構 造’其中該旁路電容㈣放置於封裝板之内部。 一例如,曾.經試圖將旁路電容器併人封裝板(諸如—坡璃 pm)中。然而,與現有的情況相比,由於佈線層之數目 535272 A7 --------B7 —__ 五、發明説明(2 ) 增加,其可能降低產量並增加成本,且其需要引入一特殊 的材料與程序。 至於解決此一問題的方法方面,其設想使用一習用板 作為該封裝板,且僅將需要該旁路電容器之半導體元件藉 由一併有該電容器的重分配板安置在該封裝板上。 然而,其需要能夠配合該半導體之一精密電極襯墊以 及該等襯墊間的間距的板技術(佈線、多層,通道成形技 術)。此外,其需要形成通道,以便使重分配板上的電路通 到該重分配板之背侧。因此,其大體上難以進一步降低成 本同時達成一裝置的性能。當然,其需要儘可能簡單構造 該重分配板,以便滿足該半導體元件所需要的電子性能, 並降低成本。 然而,由於簡化重分配板之構造而使該重分配板的厚 度變薄時,該重分配板之剛性會降低。因此,在該半導體 元件的製造程序中,該重分配板可能會輕易地變形或損壞。 本發明之一般目的係在於提供一種改良且有用的半 導體裝置與重分配板之製造方法,其中以上所述之問題能 夠加以消除。 本發明之一更為特別之目的係在於提供一種封裝該 半導體元件之半導體裝置、併有一被動元件(諸如旁路電容 器)之重分配板,以及用於此一半導體裝置之較佳重分配板 的製造方法,其中以上所述之問題能夠加以消除。 為了達成上述之目的,根據本發明之一觀點提供一種 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁)
、可I 535272 A7 __B7_ 五、發明説明(3 ) 併有一被動元件之半導體裝置的製造方法,該方法之步驟 包含:形成一重分配板之一重分配板形成步驟,其將該被 動元件併入一基板上、一半導體元件安置步驟,其將至少 一個半導體元件安置在相對於基板形成在該基板上的重分 配板之相反側表面上、一基板分離步驟,其使該基板與重 分配板分離,並暴露該重分配板之其他表面,以及一重分 配板安置步驟,其經由露出該重分配板之其他表面的電極 襯墊,將該重分配板安置在一封裝板上。 根據本發明之上述觀點,該重分配板係固定到基板, 直到半導體元件安置在該重分配板上為止,基板因而補強 該重分配板。另外,該半導體元件在基板移除之後用來補 強重分配板。因此,由於該重分配板隨時係藉由基板或半 導體元件補強,且並非獨自處理,故能夠防止該重分配板 產生變形或破壞。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 所述之半導體裝置的製造方法加以達成,其中該半導體安 置步驟包括在重分配板與半導體元件之間以一底部充填材 料充填的步驟。 根據本發明之上述觀點,該重分配板係進一步藉由該 底部充填材料補強。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 所速之併有一被動元件之半導體裝置的製造方法加以達 成,該方法包含之步驟為:一重分配板形成步驟,其形成 一將该被動元件併在一基板上之重分配板、一重分配板安 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 6 (請先閲讀背面之注意事項再填寫本頁)
535272 五、發明説明(4 置步驟’其經由鉻出该重分配板之其他表面的電極觀墊, 將形成在該基板上之重分配板安置於一封裝板上、一基板 分離步驟,其使該基板與重分配板分離,並暴露該重分配 板之其他表面,以及一半導體元件安置步驟,其經由露出 该重分配板之其他表面的電極襯墊,將至少一個半導體元 件安置在該重分配板上。 根據本發明之上述觀點,該重分配板係固定到基板, 直到该重分配板安置在封裝板上為止,基板因而補強該重 分配板。另外,該封裝板在基板移除之後用來補強重分配 板。因此,由於該重分配板隨時係藉由基板或封裝板補強, 且並非獨自處理,故能夠防止該重分配板產生變形或破壞。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 所述之半導體裝置的製造方法加以達成,其中該半導體安 置步驟包括在重分配板與半導體元件之間以一底部充填材 料充填的步驟。 根據本發明之上述觀點,該重分配板係進一步的補 強。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 所述之半導體裝置的製造方法加以達成,其中該基板係由 夕曰B圓所成’且该重分配板在基板移除步驟之後係加 以個別處理。 根據本發明之上述觀點,其能夠整體地處理複數個重 分配板,並簡化該半導體製造程序。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公贊) (請先閲讀背面之注意事項再填寫本頁) 訂_ 535272 A7 B7 五、發明説明(5 ) 所述之併有一被動元件之半導體裝置的製造方法加以達 成,·該方法包含:一重分配板形成步驟,其在基板上形成 一併有該被動元件之重分配板、一基板分離步驟,其使該 基板與重分配板分離、一半導體元件安置步驟,其經由形 成在該重分配板之一表面上的電極襯墊,將至少一個半導 體元件女置在重分配板上,以及一重分配板安置步驟,其 由开》成在該重分配板之其他表面上的電極襯墊,將該重 分配板安置在一封裝板上。 根據本發明之上述觀點,由於能夠在該重分配板之任 一側開始進行安置程序,故其增加了該半導體製造程序的 彈性。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 所述之半導體裝置的製造方法加以達成,其中該重分配板 形成步驟包括:在形成於該基板之一相反側上的重分配板 之電極襯墊上形成圓柱金屬構件的一步驟,以及在該等圓 柱金屬構件之間以絕緣樹脂加以充填的一步驟。 根據本發明之上述觀點,由於重分配板係藉由該絕緣 樹脂加以補強,故其能夠防止該重分配板產生變形或破壞。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 所述之半導體裝置的製造方法加以達成,其中該重分配板 形成步驟包括:在形成於該基板之一相反側上的重分配板 之電極襯塾上形成圓柱金屬構件的一步驟,以及在該等圓 柱至屬構件之間以絕緣樹脂加以充填的一步驟。 根據本發明之上述觀點,由於該絕緣樹脂補強重分配
535272 五、發明説明(6 ) 板,故其能夠防止該重分配板在半導體之製造程序中產生 變形或破壞。 、根據本發明之另-觀點,上述之目的亦能夠藉著以上 所速之重分配板加以達成,其中該等圓柱金屬構件係由一 沉積於一圓柱構造中之銅電鍍層所製造。 根據本發明之上述觀點,其能夠利用抗感光之一微影 攝影技術,將該銅鏡層沉積於一圓柱構造之中,以便容易 地在該等電極襯墊上形成圓柱金屬構件。 根據本發明之另一觀點,上述之目的亦能夠藉著以上 所述之重分配板加以達成,其中該等圓柱金屬構件係由金 線所製造,並藉由-電線結合方法與該等電極襯墊相連接。 根據本發明之上述觀點,纟能夠#著結合該金線與該 等電極襯墊,容易地形成該等圓柱金屬構件。 根據本發明之另一觀點,上述之目的亦能夠藉著併有 -被動元件之重分配板的製造方法加以達成,該方法包含 之步驟為:在一陶究板上形成一銅喷錢薄膜的步驟、一重 分配板形成步驟,其在該銅喷濺薄膜上形成併有該被動元 件的重分配板、-基板分離步驟,其使該陶兗板剝落且與 銅賀錢薄膜分離,卩及藉著餘刻移除該銅喷賤薄膜的步 驟’並露出該重分配板之電極。 根據本發明之上述觀點,由於該銅噴濺薄膜與陶瓷板 之間的黏著相當脆弱,故其能夠容易地使作為基板之該陶 瓷板剝離包括該銅喷濺薄膜的重分配板。在陶瓷板剝落之 後,该重分配板能夠藉著移除銅噴濺薄膜所形成。 五、發明説明(7 ) 、特性與優點將從以下的詳細說 研讀變得更為顯而易見。 本發明之其他的目的 明.,並結合所附圖式加以 圖式之說明_ 一半導體裝 第1圖係為根據本發明之一第一實施例 置之橫剖面圖; 第2A圖與2B圖係為橫剖面圖,用以說明一重分配板 構造與製造程序; 第3A、3B與3C圖係為横剖面圖,用以說明第i圖中所 示之該半導體裝置的製造程序; 第4圖係為第1圖中所示之該半導體裝置的製造程序 之流程圖; 第5圖係為根據本發明之一第二實施 一 置之橫剖面圖; 衣 第6A、6B與6C圖係為橫剖面圖,用以說明第5圖中所 示之該半導體裝置的製造程序; 第7圖係為第5/1#所示之該半導體裝置的製造程序 之流程圖; 丨约 零: 第8八、86與__係為橫剖面圖,用以說明根據本發 明之一第三實施食|參:/一半導體裝置之製造方法; 弟9圖係為根據本發明之一第四實施例,一半導體事 置之橫剖面圖; 弟10A、1 〇B、10C與10D圖係為橫剖面圖,用已說明 第9圖中所示之該重分配板的製造程序; 第11圖係為藉由第9圖中之斷線圍繞的部份之放大圖; 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 10 535272 A7 —- _ B7_ _ 五、發明説明(8 ) 第12圖係為根據本發明之一第五實施例,一半導體裝 置之橫剖面圖; 弟13圖係為根據本發明之一第六實施例,一半導體裝 置之橫剖面圖; 第14A與14B圖係為橫剖面圖,用以說明第13圖中所示 之該重分配板的製造程序;及 第15圖係為根據本發明之一第七實施例,一半導體裝 置之橫剖面圖。 較佳實施例之詳細說明 接著將說明本發明之實施例。 弟1圖係為根據本發明之一第一實施例,一半導體裝 置之檢剖面圖。根據本發明之第一實施例,該半導體裝置 包括一封裝板2、一與該封裝板2相連的重分配板4、一第一 半導體兀件6以及一第二半導體元件8,該第一與第二半導 體元件6、8係安置在重分配板4之上。此外,安置在該重分 配板4上之半導體元件的數目可為一個、三個或更多。另 外,在此實施例中,一熱撒播器1〇係藉著一黏著劑以固定 到該第一與第二半導體元件之背部表面,該熱撒播器⑺用 以加速來自於该等半導體元件6、8之熱消散。然而,若有 需要’該熱撒播器10並不一定需要。 該封裝板2係藉由一玻璃陶瓷板、一鋁板或組合板加 以構le。與知料突塊i 4連接之電極襯墊係形成於該封裝板2 之頂表面2a上’在該封裝板2之下表面上,電極襯塾係形成 於焊料球16形成之處,成為外部終端。該封裝板係為一多 本紙張尺度適用中關家標準(CNS) M規格(2ωχ297公幻 (請先閱讀背面之注意事項再填寫本頁) 0, .訂| 11 535272 五、發明説明(9 層構造’位於頂表面2a上之該等電極襯墊係藉著穿過數個 層的通這或類似物’與位於下表面2b上對應電極襯墊電子 連接。 如第1圖中所示,該重分配板4具有一多層構造,作為 方路笔谷為之内建電容器18係形成於該重分配板4之内 側。藉由一第一電子傳導層所形成之電極襯墊係露出該重 分配板4之下表面4b,並經由該焊料突塊14與封裝板2之對 應電極襯墊相連接。另外,藉由一第四電子導體所形成的 電極襯墊係露出該重分配板4之頂部表面4 a,且利用這些電 極襯墊,忒第一與第二半導體元件6、8係藉著覆晶安置安 裝到該重分配板4上。 第2 A與2B圖分別係為橫剖面圖,用以說明該重分配板 4之構造與製造程序。首先,如第2八圖中所示,電極襯墊 係藉著形成-白金薄膜之圖案所形成,成為—基板2〇(諸如 一矽板或類似物)上之第一電子導體22。接著,一具有高電 介質常數之BST薄膜(鋇/锶/鈦過濾器)係形成一第一絕緣 層24。接著,在需要之位置形成第—通⑽以後,電極概 塾係藉著形成-白金薄膜之㈣所形成,成為該第一絕 層24上之第二電介質層28。在形成於第_絕緣層24兩側上 之該等電極襯墊之中,藉由該等第一通道26連接之成對的 電極襯墊係作為電子傳導部件。另一方面,由於具有高電 介值常數之該BST薄膜座落其間,&沒有面對一 =道 26之成對的電極襯墊係作為電容器。這些電容哭成為人併 電容器18’且當併人該半導體裝置中時料該旁路電容°器併 緣 (請先閲讀背面之注意事項再填寫本頁) -螓- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 12 五、發明説明(10 ) 接著’如第2B圖中所示,-第二絕緣層3〇係形成在第 二電—介質層28之上。一銅佈線圖案係形成於該第二絕緣層 3〇之上]成為—第三電子傳導層32。該第二絕緣層30係由 聚琉亞氨、BCB薄膜或類似物所形成,通道孔係形成於第 二電子傳導層28之該等電極襯墊的對應位置中。一第三電 子傳導層32係由例如銅(Cu)鍍層所形成,且第二通 形成於該等通道孔之中。因此,形成於該第二絕緣層30上 之銅佈線圖案32、以及形成該第二電子傳導層_白金薄 膜佈線圖㈣藉由該m道34電子連接。作為該第三 電子傳導層32之銅佈線圖案成為用於重分配板之_佈線圖 案0 接著,一第三絕緣層36係形成於該第三電子傳導層% 之上。-銅佈線圖㈣形成於該第三絕緣層36之上,絲 -第:電介質傳導層40,該第三絕緣層36係由聚硫亞氨、 BCB薄膜或類似物所形成,通道孔係形成於該第三電子傳 導層32之銅佈線圖案的對應位置中。—第四電子傳導層仙 係由例如__層所形成’且第三通㈣係形成於料 通運孔之巾。因此,形成於該第二絕緣㈣上之銅佈線圖 =、以及形成該第三'絕緣層36上的銅佈線圖案係藉由該等 弟二通道38電子連接。料該第四電子料層40之銅佈線 圖案係絲料電極絲。上述之第_與第三半導體元件 6、8係藉由覆晶安置安裝於這些電極概塾上。 當藉著銅鑛層形成上述之第三與第四電子傳導層 535272 、發明説明(u) 似物之噴濺薄膜,以便加強與分別位於第三與第四電子傳 導層32、40下方的絕緣層的黏著,並使其能夠進行;解電 鍍。此外,該第二與第三絕緣層30與36之厚度係為2微米= W微米,該銅佈線圖案32與40之厚度約為數微米。另外, 作為該第四電子傳導層40之佈線圖案係對應於藉由覆晶封 裝來安置半導體元件6與8之該等電極襯墊。因此,其較佳 係實施阻擋金屬鍍層(諸如Ni鍍層或類似物),且將諸如 Au、Pd、Sn或類似物電鍍到該第四電子傳導層。 如第2B圖中所示,該重分配板4係形成於基板⑼之 上。然而,當使用該重分配板4製造半導體元件時會移除該 基板20。由於該重分配板4係為薄板,當與基板汕分離時, 其容易產生變形或損壞。 此外,上述之重分配板4能夠以日本早期公開申請案 第2001-274036號中所提出的方法加以製造。 接著將參考第3A、3B、3C與第4圖,說明根據本發明 之該半導體裝置的製造程序。 首先,如第4圖之流程圖中所示準備該重分配板4。在 步驟si中,藉由一白金薄膜所形成之該第一電子傳導層22 係形成在一矽晶圓上,該矽晶圓稱為基板2〇。接著,在步 驟S2中,作為第一絕緣層24之BST薄膜係形成於該第一電 子傳導層22之上。接著,在步驟S3中,藉由白金薄膜所形 成的該第二電子傳導層28係形成在該BST薄膜之上。 接著,在步驟S4中,一作為該第二絕緣層3〇之聚硫亞 氨薄膜係形成在該第二電子傳導層28之上。在步驟§5中, 本紙張尺度適用中國國家標準(CNS) A4規格(21〇><297公釐) (請先閲讀背面之注意事項再填寫本頁) 舞 、τ· 535272
五、發明説明( 12 由銅锻層所構成的該第三電子傳導層3 2係形成在該聚硫亞 氨薄膜之上。在步驟S6中,作為該第三絕緣層36之聚硫亞 氨薄膜係形成於該第三電子傳導層32之上。在步驟S7中, 由銅鍛層所構成之第四電子傳導層40係形成於該聚硫亞氨 薄膜之上。 步驟S1到S7係為用以準備該重分配板4之程序,另 外,藉著重複步驟S5與S6,能夠進一步增加該重分配板4 之層數。 當该重分配板4準備完成時,其實行一程序,用以藉 著覆晶封裝,將該半導體元件6與8安置在重分配板4之上。 也就是說,在步驟88之中,實行Ni鍍層成為該重分配板4 之第四電子傳導層40的電極襯墊上之阻擋金屬,且隨後 行諸如Au、Pd、Sn或類似物之其他鍍層。接著,在步驟 中,半導體元件6與8(焊料突塊係事先形成於該處)係藉 復晶女置安裝於該重分配板4之第四電子傳導層4〇上。可 著形成Au螺栓突塊使用Au-Sn結合到該半導體元件6與8 來取代焊料結合,且在該重分配板4側上實行錫鍍層。 接著,在步驟sio中,一底部充填材料44係分別充填 於該重分配板4與半導體元件6、8之間,以便確保覆晶安 之可靠性。在此實施例中,該半導體元件6與8係藉由覆 安置安裝在重分配板4上。然而,安置之半導體元件的數 可為一個、三個或更多。 如第3 A圖中所示,該重分配板4假設第一與第二半 體元件6與8係在上述程序之後加以安置。步驟81到§1〇係 實 S9著藉 置 曰曰 § 導 (請先閱讀背面之注意事項再填寫本頁) 、^τ— 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公#) 15 535272 五、發明説明(l3 ) A7 B7 在該重分配板4形成在基板20上之同時加以實行,因此,該 基板20係用以補強薄的重分配板4。所以,其能夠容易地實 行該半導體元件6與8之覆晶安置,並防止該重分配板4產生 變形或損壞。 在步驟11中,由一矽板所構成的該基板2〇係在半導體 元件6、8安置於重分配板4之上,且藉由底部充填材料料 固定以後方加以移除。該基板20能夠藉著蝕刻或背部研磨 加以移除,該蝕刻與背部研磨能夠一起使用。由於移除該 基板20,該第一電子傳導層4〇係露出該重分配板4之一表 面,如第3B圖中所示。 另外,儘管移除該基板20,由於該半導體元件6與8係 藉著底部充填材料44固定在重分配板4之相反側上,故該半 導體元件6與8係用來補強重分配板4,以便防止該重分配板 4產生變形或損壞。 接著,在步驟12中,焊料突塊係形成於該等電極襯墊 之上,該等電極襯墊係由重分配板4之第一電子傳導層22 所構成。重分配板4係安置於封裝板2之上,該封裝板係由 諸如玻璃陶瓷板、組合板或類似物所構成。接著,藉著在 該重分配板4與封裝板2之間以一底部充填材料仏加以充 填丄加強該安置之可靠性。接著’在步驟su之中,熱撒 播器係藉著黏著劑I2分別固定到半導體元件⑻。最 後,在步㈣钟,作料料端Μ㈣16係形成於該 等,極襯塾5其係設置於該封裝板2面對底部之側上,且完 成第3C圖中所示之半導體裝置。 本紙張尺度適用巾關家檩準(_ Α4規格(21GX297公楚) (請先閲讀背面之注意事項再填窝本頁;}
16 535272 A7 P五、發明説明(~" 在步驟S13之中,當不需設置該熱撒播器1〇之時,其 能夠略過步驟13而進到步驟S14。另外,對於步驟su與si4 而5,其能夠先實行其中任一步驟。 此外,在上述實施例中,該矽晶圓係用來作為基板 20然而當基板20係為一晶圓的情形中,其亦能夠在該 晶圓上形成複數個重分配板4。在此案例中,諸如切塊或類 似之單獨化程序較佳係在步驟S7之程序以後加以實行,或 是在步驟S9或S10結束以後加以實行。 接著將參考第5圖說明本發明之一第二實施例。第5圖 係為根據本發明之第二實施例,一半導體裝置之橫剖面 圖。在第5圖中,那些與第丨圖中之對應組件相同的組件係 以相同的參考數字代表,且其說明將加以省略。 根據本發明之第二實施例,該半導體裝置使用之組件 與根據本發明之第一實施例的半導體裝置之組件相同。然 @,根據本發明之第二實施例的半導體裝置與根據本發明 之第-實_的+導體裝置之間的不同之處為該重分配板 4係上下顛倒放置。也就是說,由該重分配板*之第四電子 料層4G所構成的該等電極襯塾係與封裝板2之電極觀塾 相連接。半導體元件6與8係安置於由第一電子傳導層Μ所 I 構成的该等電極觀塾之上。 | 第6A、6B與6C圖係為橫剖面圖,用以說明第5圖中所 不之該半導體裝置的製造程序。第7圖係為第5圖中所示之 | 该半導體裝置的製造程序之流程圖。 在第7圖中,步驟S21到步驟S27係用來形成重分配板4 (CNS) (210x297^) --- -17 -
•訂| (請先閲讀背面之注意事項再填寫本頁) 舞 535272 A7 B7 五、發明説明(IS ) 之程序,其與第4圖中之步驟S1到S7之程序相同。在此實 施例中,於重分配板4形成在基板20以後,在步驟S28之中 實行一預處理,用以將該重分配板4安置於封裝板上。也就 是說,當重分配板4係藉著焊料結合加以安置時,該等焊料 突塊係形成到封裝板。或者,當該重分配板4係藉著Au-Sn 結合加以安置時,Au螺栓突塊係形成到封裝板2之該等電 極襯墊,並對於重分配板4之該等電極襯墊實行錫鍍層程 接著在步驟S29之中,如第6A圖中所示,該重分配板4 係安置在封裝板2之上。在步驟S30中,該底部充填材料46 係注入重分配板4與封裝板2之間。之後,在步驟S31之中, 如第6B圖中所示,基板20係加以移除,該基板20係藉著與 上述之第一實施例相同的方法移除。 如上述,在此實施例中,其係在從重分配板4移除基 板20以前將重分配板4安置於封裝板2上。所以,該重分配 板4係隨時藉著基板20或封裝板2加以補強。因此,其能夠 防止由於重分配板4本身沒有任何的補強,而使該重分配板 4產生變形或破壞。 當在步驟S31中移除基板20時,該第一電子傳導層22 係露出該重分配板4之一表面。接著,在步驟S32中,該半 導體元件6與8係藉著覆晶安置安裝在重分配板4之上,且底 部充填材料44係分別充填於該半導體元件6與8以及重分配 板4之間。在步驟S33之中,與第一實施例相同,該熱撒播 器10係藉由黏著劑12與半導體元件6、8相連接。在步驟S34 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 18 (請先閲讀背面之注意事項再填寫本頁) 訂- ^5272 A7 Τ'-—---— Β7__
五、發明説明(16 ) ' ---~S 中丨干料球16係形成在電極襯墊之上,該等電極襯墊係 4於封衣板2上,且完成第5圖與第6C圖中所示之半導體元 件。 一/著’將參考第8A、8B、叱與扣圖,說明本發明之 …貝化例本叙明之第二實施例的半導體裝置具有與 上述之第一或第二實施例的半導體裝置相同之構造。然 而本發明之該第三實施例的半導體裝置與第一及第二實 施例之半導體裝置的製造程序不同。 、 在本發明之第三實施例中,如第8八圖中所示,重分配 板4係形成在基板2〇之上。之後,如第⑽圖中所示,該基 ^20係自重分配板4分離或移除。之後,該f分配板罐結 口到半導體it件6、8死封裝板2。如第8C圖中所示,半導 體元件6、8可在安裝到封裝板2之前安置於重分配板2。或 者如第8D圖中所示,該封裝板2可在安裝到半導體元件6、 8之前安置於重分配板4上。在此案财,㈣分配板4係形 成具有一厚度,以便即使當分離或移除該基板2〇之時具有 足夠的強度。或者,選擇一具有足夠強度之材料來形成該 重分配板4。 接著將苓考第9圖,說明本發明之一第四實施例。第9 圖係為根據本發明之該第四實施例,一半導體裝置之橫剖 面圖。在第9圖中,那些與第丨圖中之對應組件相同的組件 係以相同之參考數字加以表示,並省略其說明。 根據本發明之半導體裝置具有與上述第一實施例的 半‘體裝置相同之構造。然而,一重分配板4 A之構造係不 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁)
19 535272 A7 五、發明説明(Π) 同於上述的重分配板4。也就是說,如第9圖中所示,此實 施例之重分配板4A在構成該等電極襯墊之第四電子傳導 層40上進一步包括一圓柱金屬構件5〇(亦稱為金屬支柱或 金屬柱)。接著,藉著將絕緣樹脂52充填入該等金屬支柱5〇 之間,使該等鄰接的之支柱5〇絕緣,且彼此保持分離。 金屬支柱之高度為例如100微米,絕緣樹脂層之厚度 為70到80微米。藉著該絕緣樹脂層52之補強效果,使重分 配板4A具有足夠的剛性,以便防止對該重分配板產生變形 與破壞。 第l〇A、10B、10C與1〇D係為橫剖面圖,用以說明重 分配板4A之製造程序。為了在第四電子傳導層糾上形成該 等至屬支柱50,在重分配板4形成之後,一諸如丁丨、Cr或類 似物之阻擋金屬層(其說明係加以省略)係藉著一噴濺裝置 形成在該第四電子傳導層4〇上。接著,如第i〇A圖中所示, 由一抗感光劑所製造的乾燥薄膜係附接到該阻擋金屬層, 對應該等金屬支柱50之圖案的穿透孔係使用一微影攝影技 術形成到該薄膜,所使用之薄膜厚度係與欲形成之該等金 屬支柱的南度相同。接著,如第10B圖中所示,該等金屬 支柱係根據Cu電解電鍍方法,藉著將銅沉積於薄膜之該等 穿透孔中所形成。 在形成金屬支柱50之後,電鍍層54係形成在絕緣層52 的突出部件之上,如第n圖中所示,以便使該等金屬支柱 5〇作為電極襯墊,用以安置半導體元件6與8。該電鍍層54 較佳具有一雙層構造,以致於使由一 Ni電鍍層所構成的阻 準(“M規格⑵。X29^------ (請先閲讀背面之注意事項再填窝本頁) .訂丨 A7
發明説明 擋金屬層係形成在一連接該金屬支柱5〇之一表面的部件 上’且用來改進焊料結合效率之_Pd電鍍層或_Au電鍵層 係形成於其上。亦可使用一三層構造,以致於使pd電鍍層 形成於Ni電鍍層上,且八〇電鍍層係形成於其上。 在電鍍層54形成以後,該乾燥薄膜係加以移除,如第 i〇c圖中所示。之後,如第10D圖中所示,絕緣樹脂層% 係藉著在该等金屬支柱50之間充填絕緣樹脂所形成。在充 填絕緣樹脂方面,其能夠使用以液體形式注入一環氧樹脂 的方法,或是藉著轉移模製充填該環氧樹脂的方法。 半導體元件6與8係藉著覆晶安置,以與上述之第一實 施例相同的方法安置在如以上說明所形成的重分配板々A 之上。此外,該重分配板4A係安置於封裝板2上,且併入 第9圖中所示的該半導體裝置之中。 如以上所述,根據本發明之重分配板藉由該絕緣樹脂 層52而增加其剛性。因此,其能夠防止該重分配板4a在半 導體裝置之製造程序中產生變形或損壞,並增進該半導體 裝置之製造良率。 接著將參考第12圖,說明本發明之一第五實施例。第 12圖係為根據本發明之第五實施例,一半導體裝置之橫剖 面圖。在第12圖中,那些與第9圖中之對應組件相同的組件 係以相同之參考數字加以表示,並省略其說明。 除了重分配板4A上下顛倒放置以外,根據此實施例之 半導體裝置與根據上述第四實施例的半導體裝置具有相同 的組件。也就是說,重分配板4A之該等金屬支柱5〇係與封
21 535272 A7 --------—----B7 _ 五、發明説明(19 ) 裝板2的該等電極襯墊相連接。半導體元件6與8係安置在由 電子傳導層22所構成的該等電極襯墊之上。 (請先閲讀背面之注意事項再填寫本頁) 除了以重分配板4A取代重分配板4之外,根據此實施 例之半導體裝置的製造方法係與根據上述第二實施例之半 導體的製造方法相同。也就是說,其詳細說明將加以省略。 與上述之第四實施例相同,此實施例之重分配板4八係 藉由絕緣樹脂層52增加其剛性。因此,其能夠防止該重分 配板4A在半導體裝置的製造程序中產生變形或損壞,並增 進該半導體裝置之製造良率。 接著將參考第13圖,說明本發明之一第六實施例。第 13圖係為根據本發明之該第六實施例,一半導體裝置之橫 剖面圖。在第13圖中,那些與第丨圖中之對應組件相同的組 件係以相同之參考數字加以表示,並省略其說明。 除了重分配板4B之構造與該重分配板4的構造不同以 外,根據此實施例之半導體裝置基本上與根據上述第一實 施例的半導體裝置具有相同的構造。也就是說,如第13圖 中所示,此貫施例之重分配板4B在構成該等電極襯墊的第 四電子傳導層40上進一步具有作為圓柱金屬構件的微插銷 60。接著,絕緣樹脂62係充填於該等微插銷6〇之間,以便 隔鄰接的微插銷’並使其彼此分離。 一微插銷之兩度為例如100微米,該絕緣樹脂層62之 厚度係為70到80微米。藉著該絕緣樹脂層62之補強效果, 使重分配板4B具有足夠的剛性,以便防止對該重分配板產 生變形與破壞。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 22 如第14圖中所示,形成該等微插銷6〇,以致於使金屬 線(諸如金線或類似物)結合到第四電子傳導層。接著, 切除金屬線之線頭,以便在重分配板4之厚度方向獲得例如 1 〇〇M米之長度(高度)。各個微插銷6〇係設置到該第四電子 傳V層40 ’以便從該處幾乎垂直延伸,且不會彼此接觸。 當該等微插銷60形成時,該等微插銷6〇之表面係藉著 一非電鍍方法加以鍍鎳與鍍金。該Ni鍍層作為阻擋金屬, 且金鍍層係用來改良焊料結合效率。接著,如第14B圖中 所不,將絕緣樹脂(諸如一環氧樹脂或類似物)充填於該等 微插銷60之間,以便形成絕緣樹脂層62。 半導體元件6與8係藉著覆晶安裝,以與第一實施例相 同的方法安置於如上述所形成之重分配板4B上。此外,該 重分配板4B係安置於封裝板2之上,且併入第丨3圖中所示 的半導體裝置之中。 如以上所述,根據此實施例之重分配板4B藉著該絕緣 樹脂層62增加其剛性。因此,其能夠防止該重分配板仙在 半導體裝置的製造程序中產生變形或損壞,並增加該半導 體裝置之製造良率。 接著將參考第15圖,說明本發明之一第七實施例。第 15圖係為根據本發明之一第七實施例,一半導體裝置的橫 剖面圖。在第15圖中,那些與第13圖中之對應組件相同的 組件係以相同的參考數字代表,且其說明將加以省略。 除了重分配板4B上下顛倒放置以外,根據此實施例之 半導體裝置具有與根據上述第四實施例的半導體裝置相同 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 23 535272 A7 B7 五、發明説明(21 ) 之組件。也就是說,重分配板4B之該等金屬支柱5 0係與封 -裝板2之電極概塾相連接’半導體元件6與8係安置在由第一 電子傳導層22所構成的該等電極襯墊上。 除了以重分配板4B取代重分配板4以外,根據此實施 例之半導體裝置的製造方法係與根據上述第二實施例之半 導體裝置的製造方法相同。因此,其詳細說明係加以省略。 然而,應注意的是,絕緣樹脂62並非對於重分配板4B 加以設置。各微插銷獨立垂直豎立,因此,當該等微插銷 60之間沒有以絕緣樹脂加以充填時,微插銷60並不會與鄰 接的微插銷60相接觸。因此,在形成於基板20上之重分配 板4B藉著焊接經由該等微插銷60安置於封裝板2上以後, 底部充填材料46充填於該等微插銷60之間。 另外,當設置絕緣樹脂層62時,底部充填材料46可能 並不需要。此外,由於該等微插銷具有彈簧特性,故當該 等微插銷與突塊接觸時,該等微插銷能夠承受一熱循環、 衝擊或類似情形。 在各上述之實施例中,一矽酮板係用來作為基板20。 然而,其亦可使用其他材料所構成的板子。 例如,當使用一藍寶石板作為基板20時,該基板20能 夠藉由照射一雷射光束與重分配板分離。也就是說,一有 機薄膜係形成在該藍寶石板上,以便在其上形成重分配 板。接著,藍寶石板係藉著雷射光束照射在該藍寶石板上, 並蒸發該有機薄膜而與重分配板分離。 另外,當藉著銅或銅合金形成基板20時,其能夠藉著 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 24 (請先閲讀背面之注意事項再填寫本頁)
535272 五、發明説明( 22 僅將基板20浸泡於蝕刻劑中,並溶解該銅或銅合金移除該 基板20。在此案例中,較佳係預先實行樹脂塗佈,以便使 銅不會路出佈線層,一電路元件或是半導體裝置之組件的 封裝板。 另外’至於分離基板之方法方面,其具有一種方法, 该方法使重分配板形成在_水溶性剝落層上,該水溶性剝 洛層係預先形成於基板2〇之上。至於該水溶性剝落層之材 料方面’其能夠使㈣化_ ΚΒι>。藉著使重分配板形成在 水溶性剝落層上,該水溶性㈣層形成在基板2G之上,並 Μ㈣Μ基板2G浸泡在水中’來溶解該水溶性剝落 層’並使基板20與重分配板分離。 另外’藉著由一水溶性材料(諸如溴化鉀KBr)形成基板 2〇本體,能夠在水中溶解基板2〇而加以移除。 另外,為了使基板容易與重分配板(佈線層)分離,該 重刀配板%夠藉著在一陶瓷板(諸如氮化鋁或類似物)上形 成一銅㈣«薄料形成,並藉著微影攝影在該&喷錢 層上形成佈線層或類似物。由於〜喷_與陶曼板之間 的黏著相當脆弱,故該Cu喷濺層係容易與陶莞板剝離。在 使包糾u錢薄膜之陶£板與重分配㈣離以後,該& 貝錢缚版係猎由名虫刻加以德w 』加以私除,且露出與封裝板以及半導 體元件相連接之該等電極。該重分配板之形成方法係與上 述的貫施例相同,且其說明係加以省略。 本發明並非受限於所揭露的特定實施例’且能夠進行 改變與修正,而不脫離本發明之範畛。 (請先閱讀背面之注意事項再填寫本頁) 、可| 本紙張尺細咖辦(2歌^ 25 535272 A7 B7 五、發明説明(23 ) 本發明係基於2001年10月31曰申請之日本優先申請 案第2001-33 5413號,其完整内容係以參考方式併入本文之 中 〇 元件標號對照 2…封裝板 22···第一電子傳導層 2a…頂表面 24···第一絕緣層 2b…下表面 26…第一通道 4···重分配板 28…第二電子傳導層 4a…頂表面 30…第二絕緣層 4b···下表面 32···第三電子傳導層 4A···重分配板 34…第二通道 4B···重分配板 36…第三絕緣層 6···半導體元件 38···第三通道 8···半導體元件 40···第四電子傳導層 10…熱撒播器 44…底部充填材料 12…黏著劑 46…底部充填材料 14…焊料突塊 50…金屬支柱 16…焊料球 52···絕緣樹脂層 18…電容器 54…電鍍層 20…基板 60…微插銷 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 26 (請先閲讀背面之注意事項再填寫本頁)
Claims (1)
- 535272 A8 B8 C8 _______ D8 六、申請專利範圍 1. 一種併有一被動元件之半導體裝置的製造方法,該方法 包含: 一重分配板形成步驟,其在基板上形成一併有該被 動元件之重分配板; 一半導體元件安置步驟,其安置至少一個半導體元 件在重分配板的相反側表面上,該重分配板對於基板形 成在該基板之上; 一基板分離步驟,其使基板與重分配板分離,並 露出該重分配板之其他表面;及 一重分配板安置步驟,其經由露出該重分配板之 其他表面的電極襯墊,將該重分配板安置於一封裝板 上。 2·如申請專利範圍第1項之半導體裝置的製造方法,其中 该半導體元件安置步驟包括在該重分配板與半導體元 件之間以一底部充填材料加以充填的步驟。 3· —種併有一被動元件之半導體裝置的製造方法,該方法 包含: 一重分配板形成步驟,其在基板上形成一併有該被 動元件之重分配板; 一重分配板安置步驟,其經由露出該重分配板之一 表面的電極襯墊,將形成在該基板上之該重分配板安置 於一封裝板上; 基板分離步驟,其使基板與重分配板分離,並露 出該重分配板之其他表面;及 中國國家A4規格----一 (請先閲讀背面之注意事項再填寫本頁) 、可| .舞 27 功272一半導體安置步驟,其經由露出該重分配板之其他 (請先閲讀背面之注意事項再填寫本頁) 表面的電極襯墊,將至少一個半導體元件安置在該重分 配板上。 4·如申請專利範圍第;3項之半導體裝置的製造方法,其中 該重分配板安置步驟包括以底部充填材料充填重分配 板與封裝板之間的一步驟。 5.如申請專利範圍第丨項之半導體裝置的製造方法,其中 该基板係由一矽晶圓所製造,複數個重分配板係整體地 形成在該矽晶圓上,且該等重分配板在基板移除步驟以 後係加以單獨化。 ’訂· 6· —種併有一被動元件之半導體裝置的製造方法,該方法 包含: 一重分配板形成步驟,其在基板上形成一併有該被 動元件之重分配板; Mm, 一基板分離步驟,其使該基板與重分配板分離; 一半導體安置步驟,其經由形成在該重分配板之一 表面上的電極襯墊,將至少一個半導體元件安置於該重 分配板上; 一重分配板安置步驟,其經由形成在該重分配板之 其他表面上的電極襯墊,將重分配板安置在一封裝板 上。 7·如申請專利範圍第1項之半導體裝置的製造方法,其中 該重分配板形成步驟包括一步驟,其在重分配板之該等 電極襯墊上形成圓柱金屬構件,其對於基板形成於該重 \ 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 28 •板之其他側面上、以及以絕緣樹脂充填該等圓柱金 屬構件之間的一步驟。 • 7申請專利範圍第1項之半導體裝置的製造方法,其 該基板係由矽g同所製造;及 、該基板分離步驟包括藉著—起使用银刻與研磨, 以移除該石夕_的一步驟。 t申請專利範圍第Ϊ項之半導體裝置的製造方法,其 該基板係由-藍寶石板所構成,其在形成該重分配 板之一表面上包括一有機薄膜;及 該基板分離步驟包括以一雷射光束經過藍寶石板 照射到該有機薄膜’並蒸發該有機薄膜。 ^申請專利範圍第i項之半導體裝置的製造方法,其 該基板係由一銅或銅合金所構成;及 該基板分離步驟包括將該基板浸泡於-钱刻劑 中’以便僅溶解該基板。 •如申請專利範圍第i項之半導體裝置的製造方法,其 中: 該基板包括-水溶性剝離層,其形成在形成該重 分配板之一表面上;及 該基板分離步驟包括將該基板浸泡於水中,以便 使該剝離層溶解在水中的一步驟。 申請專利範園 12. 如申請專利範圍第 項之+導體裝置的製造方法 中該水溶性剝離層係由漠化钾所構成。 13. 如申請專利範圍第彳g 固弟1項之+導體裝置的製造方法, 中: 其 其 該基板係由-水溶性板所構成;及 j該基板分離步驟包括將該基板™水中,以便使 該剝離層溶解在水中的一步驟。 14·如申請專利範圍第13項之半導體裝置的製造方法,其 中該水溶性板係由溴化鉀所構成。 15·如申請專利範圍第7項之半導體裝置的製造方法,其中 該圓柱金屬構件形成步驟包括-步驟,《著銅鑛層將 鋼沉積於一圓柱構造中的該等電極襯墊上。 16.如申請專㈣圍第7項之半導體裝置的製造方法,其中 該圓柱金屬構件形成步驟包括一步驟’其藉著一電線結 合方法使金線與電極襯墊相結合。 Π.—種併有一被動元件之重分配板,其包含: 圓柱金屬構件,其形成在該等電極襯墊上,該等電 極襯墊係形成在重分配板之正表面或背表面上,並以該 重分配板之厚度方向延伸一預定的長度;及 一絕緣樹脂,其由充填於該等圓柱金屬構件之間的 絕緣樹脂所構成。 18·如申請專利範圍第17項之重分配板,其中各圓柱金屬 構件係由一沉積於一圓柱構造中的銅鍍層所構成。 19·如申請專利範圍第17項之重分配板,其中各圓柱金屬 本紙張尺度適用中國國家標準(_) A4規格(21〇><297公爱) 535272 A8 B8 C8 D8 六、申請專利範圍 構件係由一金線所構成,並藉由一電線結合方法結合到 電極襯墊。 (請先閲讀背面之注意事項再填窝本頁) 20. —種併有一被動元件之重分配板的製造方法,該方法包 含·· 在一陶瓷板上形成一銅喷濺薄膜的步驟; 一重分配板形成步驟,其在該銅喷濺薄膜上形成併 有該被動元件之重分配板; 一基板分離步驟,其使陶兗板剝落,並與銅喷濺薄 膜分離;及 一藉著蝕刻移除該銅喷濺薄膜,並露出該重分配板 之電極的步驟。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001335413A JP3583396B2 (ja) | 2001-10-31 | 2001-10-31 | 半導体装置の製造方法、薄膜多層基板及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW535272B true TW535272B (en) | 2003-06-01 |
Family
ID=19150407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091105169A TW535272B (en) | 2001-10-31 | 2002-03-19 | Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board |
Country Status (3)
Country | Link |
---|---|
US (2) | US6875638B2 (zh) |
JP (1) | JP3583396B2 (zh) |
TW (1) | TW535272B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI639835B (zh) * | 2015-11-03 | 2018-11-01 | 日商日本特殊陶業股份有限公司 | 檢查用配線基板 |
CN109411419A (zh) * | 2017-08-18 | 2019-03-01 | 财团法人工业技术研究院 | 芯片封装结构 |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
TWI313507B (en) | 2002-10-25 | 2009-08-11 | Megica Corporatio | Method for assembling chips |
JP2003007921A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
JP2005039243A (ja) | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 中間基板 |
US7495179B2 (en) | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
US8641913B2 (en) | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
US7394161B2 (en) | 2003-12-08 | 2008-07-01 | Megica Corporation | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto |
US7709968B2 (en) | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
JP3999759B2 (ja) * | 2004-04-02 | 2007-10-31 | 富士通株式会社 | 基板及び電子機器 |
JP2005327932A (ja) * | 2004-05-14 | 2005-11-24 | Shinko Electric Ind Co Ltd | 多層配線基板及びその製造方法 |
US7230334B2 (en) * | 2004-11-12 | 2007-06-12 | International Business Machines Corporation | Semiconductor integrated circuit chip packages having integrated microchannel cooling modules |
TWI295089B (en) | 2004-12-28 | 2008-03-21 | Ngk Spark Plug Co | Wiring substrate and the manufacturing method of the same |
KR100914552B1 (ko) | 2005-07-25 | 2009-09-02 | 삼성전자주식회사 | 반도체 메모리 장치 및 이를 구비하는 메모리 모듈 |
US7566591B2 (en) * | 2005-08-22 | 2009-07-28 | Broadcom Corporation | Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features |
CN101233614A (zh) | 2005-09-06 | 2008-07-30 | 松下电器产业株式会社 | 电容器装载型半导体器件 |
JP5103724B2 (ja) | 2005-09-30 | 2012-12-19 | 富士通株式会社 | インターポーザの製造方法 |
JP4899406B2 (ja) * | 2005-10-12 | 2012-03-21 | 日本電気株式会社 | フリップチップ型半導体装置 |
TWI285424B (en) * | 2005-12-22 | 2007-08-11 | Princo Corp | Substrate including a multi-layer interconnection structure, methods of manufacturing and recycling the same, method of packaging electronic devices by using the same, and method of manufacturing an interconnection device |
EP1801870A1 (en) * | 2005-12-22 | 2007-06-27 | Princo Corp. | Partial adherent temporary substrate and method of using the same |
JP4738228B2 (ja) * | 2006-03-28 | 2011-08-03 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2007324557A (ja) * | 2006-06-05 | 2007-12-13 | Taiyo Yuden Co Ltd | 高周波回路モジュール |
TWI317996B (en) * | 2006-09-06 | 2009-12-01 | Advanced Semiconductor Eng | Chip package structure and heat sink for chip package |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
TWI339883B (en) * | 2007-02-02 | 2011-04-01 | Unimicron Technology Corp | Substrate structure for semiconductor package and manufacturing method thereof |
JP5179856B2 (ja) * | 2007-06-21 | 2013-04-10 | 日本特殊陶業株式会社 | 配線基板内蔵用部品及びその製造方法、配線基板 |
WO2009013708A2 (en) * | 2007-07-26 | 2009-01-29 | Koninklijke Philips Electronics N.V. | System and method for automatic sensor position recognition |
CN101874296B (zh) | 2007-09-28 | 2015-08-26 | 泰塞拉公司 | 利用成对凸柱进行倒装芯片互连 |
US7750459B2 (en) * | 2008-02-01 | 2010-07-06 | International Business Machines Corporation | Integrated module for data processing system |
US20100044860A1 (en) * | 2008-08-21 | 2010-02-25 | Tessera Interconnect Materials, Inc. | Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer |
US8048794B2 (en) * | 2009-08-18 | 2011-11-01 | International Business Machines Corporation | 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
US8344512B2 (en) * | 2009-08-20 | 2013-01-01 | International Business Machines Corporation | Three-dimensional silicon interposer for low voltage low power systems |
US8178970B2 (en) * | 2009-09-18 | 2012-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strong interconnection post geometry |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8410604B2 (en) | 2010-10-26 | 2013-04-02 | Xilinx, Inc. | Lead-free structures in a semiconductor device |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
US8867219B2 (en) | 2011-01-14 | 2014-10-21 | Harris Corporation | Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices |
CN103563072B (zh) * | 2011-05-24 | 2017-09-26 | 三菱电机株式会社 | 高频封装 |
US8772058B2 (en) * | 2012-02-02 | 2014-07-08 | Harris Corporation | Method for making a redistributed wafer using transferrable redistribution layers |
KR102027246B1 (ko) * | 2013-03-14 | 2019-10-01 | 삼성전자주식회사 | 디지타이저 및 그 제조 방법 |
US8975735B2 (en) * | 2013-08-08 | 2015-03-10 | Infineon Technologies Ag | Redistribution board, electronic component and module |
JP6261354B2 (ja) | 2014-01-27 | 2018-01-17 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | チップ実装構造体およびその製造方法 |
JP6398264B2 (ja) * | 2014-03-31 | 2018-10-03 | 富士通株式会社 | インターポーザ構造体及び半導体装置の製造方法 |
JP6484490B2 (ja) * | 2015-04-10 | 2019-03-13 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
TW202414634A (zh) | 2016-10-27 | 2024-04-01 | 美商艾德亞半導體科技有限責任公司 | 用於低溫接合的結構和方法 |
US10622326B2 (en) * | 2017-08-18 | 2020-04-14 | Industrial Technology Research Institute | Chip package structure |
WO2019066950A1 (en) * | 2017-09-29 | 2019-04-04 | Intel IP Corporation | PRINTED CIRCUIT BOARD ISLANDS FOR CONNECTING PAVERS AND METHODS OF ASSEMBLING THE SAME |
CN109729639B (zh) * | 2018-12-24 | 2020-11-20 | 奥特斯科技(重庆)有限公司 | 在无芯基板上包括柱体的部件承载件 |
JP7006843B2 (ja) | 2019-05-23 | 2022-01-24 | 凸版印刷株式会社 | 配線基板の製造方法 |
JP7423907B2 (ja) * | 2019-05-24 | 2024-01-30 | Toppanホールディングス株式会社 | 配線基板の製造方法 |
US20210217707A1 (en) * | 2020-01-10 | 2021-07-15 | Mediatek Inc. | Semiconductor package having re-distribution layer structure on substrate component |
US11605600B2 (en) * | 2020-08-06 | 2023-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure with reinforced element and formation method thereof |
CN117936510A (zh) * | 2022-10-17 | 2024-04-26 | 长鑫存储技术有限公司 | 半导体结构及其制造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5055907A (en) * | 1989-01-25 | 1991-10-08 | Mosaic, Inc. | Extended integration semiconductor structure with wiring layers |
US5192716A (en) | 1989-01-25 | 1993-03-09 | Polylithics, Inc. | Method of making a extended integration semiconductor structure |
JP2510747B2 (ja) * | 1990-02-26 | 1996-06-26 | 株式会社日立製作所 | 実装基板 |
JPH04291993A (ja) * | 1991-03-20 | 1992-10-16 | Hitachi Ltd | 薄膜ユニットの接合方法 |
JPH05259639A (ja) * | 1992-03-13 | 1993-10-08 | Toshiba Corp | プリント配線板の製造方法 |
JPH07193184A (ja) * | 1993-12-27 | 1995-07-28 | Fujitsu Ltd | マルチチップモジュールの製造方法及びマルチチップモジュール |
JPH07321490A (ja) * | 1994-05-26 | 1995-12-08 | Shinano Polymer Kk | 電気コネクタ |
US6294407B1 (en) * | 1998-05-06 | 2001-09-25 | Virtual Integration, Inc. | Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same |
US6281452B1 (en) * | 1998-12-03 | 2001-08-28 | International Business Machines Corporation | Multi-level thin-film electronic packaging structure and related method |
JP2001036236A (ja) * | 1999-02-16 | 2001-02-09 | Soshin Electric Co Ltd | 多層基板の製造方法 |
JP3701138B2 (ja) | 1999-04-23 | 2005-09-28 | 松下電器産業株式会社 | 電子部品の製造方法 |
JP2001274036A (ja) * | 2000-03-28 | 2001-10-05 | Fujitsu Ltd | フィルム状コンデンサ及びその製造方法 |
JP4701506B2 (ja) * | 2000-09-14 | 2011-06-15 | ソニー株式会社 | 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法 |
US6878608B2 (en) * | 2001-05-31 | 2005-04-12 | International Business Machines Corporation | Method of manufacture of silicon based package |
-
2001
- 2001-10-31 JP JP2001335413A patent/JP3583396B2/ja not_active Expired - Fee Related
-
2002
- 2002-03-19 US US10/100,011 patent/US6875638B2/en not_active Expired - Lifetime
- 2002-03-19 TW TW091105169A patent/TW535272B/zh not_active IP Right Cessation
-
2003
- 2003-08-29 US US10/650,692 patent/US6995044B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI639835B (zh) * | 2015-11-03 | 2018-11-01 | 日商日本特殊陶業股份有限公司 | 檢查用配線基板 |
CN109411419A (zh) * | 2017-08-18 | 2019-03-01 | 财团法人工业技术研究院 | 芯片封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US20030082846A1 (en) | 2003-05-01 |
US6995044B2 (en) | 2006-02-07 |
JP2003142624A (ja) | 2003-05-16 |
US20040053444A1 (en) | 2004-03-18 |
US6875638B2 (en) | 2005-04-05 |
JP3583396B2 (ja) | 2004-11-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW535272B (en) | Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board | |
US9837372B1 (en) | Wafer-level die to package and die to die interconnects suspended over integrated heat sinks | |
JP2003142624A5 (zh) | ||
TWI436717B (zh) | 可內設功能元件之電路板及其製造方法 | |
US8786070B2 (en) | Microelectronic package with stacked microelectronic elements and method for manufacture thereof | |
CN104851842B (zh) | 包括嵌入式表面安装器件的半导体器件及其形成方法 | |
KR101690549B1 (ko) | 내장 칩 패키지 | |
US7217888B2 (en) | Electronic parts packaging structure and method of manufacturing the same | |
JP4400802B2 (ja) | リードフレーム及びその製造方法並びに半導体装置 | |
TWI331797B (en) | Surface structure of a packaging substrate and a fabricating method thereof | |
US20020149118A1 (en) | Semiconductor device and bump formation method | |
US20040099960A1 (en) | Economical high density chip carrier | |
JP5588620B2 (ja) | ウェーハ・レベル・パッケージ及びその形成方法 | |
TWI344199B (en) | Inter-connecting structure for semiconductor device package and method of the same | |
TW200828564A (en) | Multi-chip package structure and method of forming the same | |
JP5942823B2 (ja) | 電子部品装置の製造方法、電子部品装置及び電子装置 | |
TW200416997A (en) | Electronic parts packaging structure and method of manufacturing the same | |
TW201110309A (en) | Stacking package structure with chip embedded inside and die having through silicon via and method of the same | |
JP2017017300A (ja) | チップパッケージ | |
US20030173678A1 (en) | Semiconductor device and method for fabricating the same | |
US20040195669A1 (en) | Integrated circuit packaging apparatus and method | |
US20140263582A1 (en) | Low cost interposer and method of fabrication | |
KR20200035197A (ko) | 반도체 장치 및 그 제조 방법 | |
KR101143635B1 (ko) | 적층 패키지 및 그 제조방법 | |
JP4260672B2 (ja) | 半導体装置の製造方法及び中継基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |