TW526564B - Method of fabricating semiconductor side wall fin - Google Patents

Method of fabricating semiconductor side wall fin Download PDF

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TW526564B
TW526564B TW090125391A TW90125391A TW526564B TW 526564 B TW526564 B TW 526564B TW 090125391 A TW090125391 A TW 090125391A TW 90125391 A TW90125391 A TW 90125391A TW 526564 B TW526564 B TW 526564B
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James W Adkisson
Paul D Agnello
Arne W Ballantine
Rama Divakaruni
Erin C Jones
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Description

526564 A7 B7 五、發明説明（1 ) 發明背景 發明領域 本發明主要係關於製備雙閘極金屬氧化物半導體場效應 電晶體（MOSFET)，更具體地，係關於製備具有較薄磊晶 生長的通道的雙閘極MOSFET。 背景描述 、 場效應電晶體（FET)的結構可以包括單個閘極（單通道） 或一對閘極，雙閘極的形式的優點為具有更短的通道並因 而產生更快的元件。當閘極長度縮減至50nm以下時，FET 的尺寸（scaling)受到閘極控制的有限深度的限制。研究已 顯示，將閘極設置在FET通道的多個側部將導致涉及短通 道特性和截止電流特性的改良的FET性能。假設碎足夠薄 以至於被完全空乏，那麼將閘極設置在FET通道的多個側 部上就比標準FET更加緊密地限制電場和電荷，在標準 FET中，電場無約束地深深穿透有效無限大之矽基板中。 完全空乏型雙閘極結構的可能約束使得具有20- 30nm的閘 極長度的改良的短通道效應和元件成為可能。反向感應通 道（inversion induced channel)將在碎的兩個側部上形成，且 可能越過整個通道，此通道可以增加飽和電流。其他所報 導的優點包括接近理想的次臨限值斜率、增加的飽和電流 以及減小的短通道和漂移體效應。要求主要是5 - 50nm範 圍内的薄擴散區和低至20- 100nm的閘極長度，閘極長度 較佳為擴散長度的2至4倍。 許多水平雙閘極FET結構，尤其是SOI (絕緣體上矽） -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
裝 訂
線一 526564 A7 B7 五、發明説明（2 ) 雙閘極FET結構已經被提出。除傳統的頂部閘極外，這些 結構通常尚要求形成在薄的矽主體之下的底部閘極。因為 頂部和底部閘極必須對齊至一超出當前微影蝕刻設備與方 法的精度以外的容差，且因為自對準技術受到頂部和底部 閘極間層的阻礙，所以這種結構的製造是困難的。 在菲利普洪森（Hon Sum Philip)等人在 IEDM97-427， IEEE1997中的“具有25nm厚矽通道的自對準（頂部和底部） 雙閘極 MOSFET (Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel) ” 中，雙 閘極MOSFET被認為是縮減至20- 30nm閘極長度的極限的 互補型金屬氧化物半導體（CMOS)的最有希望的候選者。 假設矽通道厚度可以減小至10- 25nm且閘極氧化物的厚度 減小至2 - 3nm，精確之蒙特卡洛（Monte Carlo)元件模擬和 分析計算預測了縮減至20- 30nm閘極長度元件性能的連續 改善。然而，因為失準將導致額外的閘極對源極/汲極的 重疊電容和電流驅動損耗，所以頂部和底部的對準對於高 性能非常關鍵。 下述專利係關於FET，且具體地係有關於雙閘極FET。 褚（Chu)等人的名稱為“垂直雙閘極場效應電晶體 (Vertical Double- Gate Field Effect Transistor) 的第 5，780, 327號美國專利描述了垂直雙閘極場效應電晶體， 其包括排列在主體或SOI基板上的堆疊内的磊晶通道層和 汲極層。利用不同的氧化速率將閘極氧化物熱生長在堆疊 的側部上，以使輸入電容的問題減至最小。閘極圍繞在堆 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 526564 A7 _________ 五、發明説明（3 ) 疊一端的周圍，而接觸部形成在第二端。内礙在堆疊第二 端内的蚀刻終止層使得接觸部可以直接製造到通道層上。 索羅門（Solomon)等人的名稱為“製造具有側壁源極一 汲極接觸部的單和雙閘極場效應電晶體的方法（Method for Making Single and Double Gate Field Effect Transistors with Sidewall Source-Drain Contacts)的第 5，773, 331 號美國專 利描述了用於製造具有側壁汲極接觸部的單閘極和雙閘極 場效應電晶體的方法。相對於下面的支撐結構提升FET通 道’並且源極和閘極區形成為通道的組成部分。 特沃瑞（Tiwad)等人的名稱為“具有超窄通道的自對準 雙閘極 MOSFET (Self-Aligned Dural Gate MOSFET with an Ultranarrow Channel) ”的第5，757, 03 8號美國專利係有關 於藉由自對準製程形成的具有充分一致寬度的超薄通道的 自對準雙閘極FET。在不同的材料之間利用選擇性蝕刻或 受控氧化，以形成在源極和汲極區間延伸的垂直通道，其 具有從2 · 5nm到100nm範圍内的厚度。 梅耶（Mayer)等人的名稱為“絕緣體上矽閘極全環繞 MOSFET 的製造方法（Silicon-on-Insulator Gate-All-Around MOSFET Fabrication Methods) ” 的第 5，580, 802 號美國專利 描述了 SOI閘極全環繞（GAA) MOSFET，該MOSFET包括被 頂部閘極包圍的源極、通道和汲極，此頂部閘極還用於其 他的掩埋結構，並且在形成在SOI晶片的源極、通道和汲 極半導體層上的底部閘極電介質上形成。 哥圖（Gotou)等人的名稱為“具有薄膜SOI結構的 -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 526564 A7 B7 五、發明説明（4 ) MOSFET (MOSFET Having a Thin Film SOI Structure)，， 的第5，308, 999號美國專利描述了具有薄膜SOI結構的 MOSFET，其中藉由在SOI層的通道區的頂表面和兩個側 表面上形成閘極電極，並藉由將閘極電極部分地延伸至通 道區底部下方内使得閘極電極不完全連接，而使具有SOI 結構的MIS(金屬絕緣材料半導體）FET的崩潰電壓得以提 南。 褚（Chu)等人的名稱為“垂直雙閘極場效應電晶體 (Vertical Double- Gate Field Effect Transistor) ” 的 第 5，689, 127號美國專利描述了垂直雙閘極FET，該FET包括 在主體或SOI基板上排列的源極層、磊晶通道層和汲極 層。使用不同的氧化速率在堆疊的側部上熱生長閘極氧化 物，以將輸入電容的問題減至最小。閘極圍繞在堆疊一端 周圍，同時接觸部形成在第二端上。内嵌在堆疊第二端内 的蝕刻終止層使接觸部可以直接形成在通道層上。 目前，微影蝕刻定義的閘極是最簡單的，但卻有許多缺 點。首先，閘極的定義可能在擴散區的側部上留下多晶矽 隔離襯，或可能在擴散區的側部上產生一所需的斜面，因 而導致較差的品質和/或較難控制的元件。其次，多晶矽 的斜面本質上導致難以形成矽化物閘極，這導致較慢的元 件特性。最後，多晶矽的階躍高度引起微影蝕刻定義的難 題，因為在50nm的設計規則技術中，我們希望階躍大約 為100nm-200nm的大小。 製造雙閘極FET的關鍵困難是實現薄擴散的矽化作用或 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 裝 訂
咸- 526564 A7 _B7_ · 五、發明説明（5 ) 具有可接受的接觸電阻的多晶矽，這使得兩個閘極沒有失 準的環繞閘極的製造和窄擴散區（理想上比閘極長度小2 -4倍）的製造成為可能。 用於製造雙閘極電晶體的其他技術包括微影蝕刻定義具 有高階躍高度的閘極（見史拉斯基（Shirasaki)的名稱為“增 加源極和汲極區之間電導率的MIS電晶體結構（MIS Transistor Structure for Increasing Conductance between Source and Dmin Reigions) ”的第4，996, 574號美國專利）、形成提 供“空氣橋（air bridge) ”矽結構的選擇性磊晶生長（見 1997年國際電子元件會議（IEDM)第427頁洪森菲利浦王 (Hon- Sum Philip Wong)的文章），以及形成具有垂直載子 傳輸的環繞閘極（見1988年IEDM第222頁H.特卡托（Η · Takato)的文章）。 總之，先前的製造方案取決於微影蝕刻定義的矽通道’ 以及耗時且受限的橫向磊晶生長。然而，在上述方法中’ 微影蝕刻定義的通道不能以足夠小的容差形成，甚至可用 的容差也不能得以充分維持以支撐接近最佳的雙閘極電晶 體的特性。另外，即使能夠嚴格控制矽的厚度，使用橫向 電流的具有橫向定義的FET寬度的技術也難以對準頂部和 底部閘極。 假設通道寬度可以製造得足夠小，詹姆斯· W ·埃迪克松 (James W. Adkisson)，約翰·Α·布拉赫塔（John Α· Bracchitta) 5 約韓· J ·埃利絲-莫娜甘（John J · Ellis-Monaghan)，傑羅姆· b ·拉斯基（Jerome B · Lasky)，克拉克 -8 - 本紙張尺度適用中國國家榡準(CNS) A4規格(210X297公釐） 526564 A7 B7 五、發明説明（6 ) • D ·彼得森（Kirk D · Peterson)和傑德· Η .蘭金（Jed H Rankin) 的在2000年3月16日申請且與上文以引用的方式併入本 文中的名稱為“雙平板閘極 SOI MOSFET結構（Double Planar Gated SOI MOSFET Structure) ” 的美國專利申請號第 0 9 / 526, 857號描述了形成雙閘極電晶體的方法。 發明簡述 因此，本發明的一個目的是提供具有較薄磊晶生長通道 的雙閘極電晶體。 根據本發明，提供一種形成場效應電晶體（FET)的方 法，包括在基板上形成碎層的步驟。其次，在碎層的側表 面上形成磊晶通道，因而顯露通道的一個側壁。然後除去 矽層，因而顯露磊晶通道的第二側壁。然後形成與磊晶通 道端部聯接的源極和汲極區。最後，在磊晶通道上方形成 閘極。 本發明試圖利用用於生長磊晶區的已知技術提供非常薄 的擴散區以形成非常薄的通道，且具有在通道厚度上提供 比微影蝕刻定義的通道更小的容差的優點，該微影蝕刻定 義的通道可以藉由選擇性i虫刻來保持，且由於薄限制層的 出現，蟲晶生長也不會複雜。 圖式簡單說明 從以下結合附圖的本發明較佳實施例的詳細說明中，本 發明之前述及其他目的、特徵和優點將得以更好地理解， 其中： 圖1A係示出矽線的元件的頂視圖； -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 裝 訂
526564 A7 B7
圖1时、沿圖1A所示的線卜1剖開的橫截面圖. 圖iC係沿圖⑽示的線2_2刻開的橫截面圖. 圖2A係示出圖⑽基板在蚀刻终止層和通道層羞晶生 長之後的視圖； ^ 圖則、沿圖2續示的線卜1剖開的橫截面圖； 圖2C係沿圖2A所示的線2_2剖開的橫截面圖； 圖3A係示出圖2A具有用於去除矽線的光罩開口的視 圖； 的橫截面圖； 餘刻終止層的所有殘 圖3B係沿圖3A所示的線2 - 2剖開 圖4A係示出圖3A在去除矽線和 留部分之後的視圖； 圖4B係沿圖4A所示的線2_2剖開的橫截面圖； 圖5係圖4A的元件在形成第二通道之後的視圖； 圖6係沿圖5所示的線2·2剖開的示意性橫截面圖； 圖7係示出圖6的基板在淺槽隔離（STi)填充和拋光之 後的視圖； 圖8A係沿圖11B所示的線2 - 2剖開的在塗覆多晶矽導 體（PC)抗姓光罩並姓刻之後的示意性橫截面圖； 圖8B係沿圖11B所示的線2 - 2剖開的在塗覆pC抗蝕光 罩之後的示意性橫截面； 圖9A係tf出圖8A的基板在閘極電介質生長或沈積和閘 極導體沈積之後的視圖； 圖9B係示出圖8B的基板在pC抗蝕光罩去除之後的視 Γ^Τ · 圖， -10- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公爱) 526564
圖1〇A不出圖9A的基板中STI和隔離佈植物的去除； 圖1〇Β π出圖9B的基板中的延伸佈植物； 圖11A係不出圖1〇A的成品元件在接觸部前的視圖； 固11B係示出成品元件的頂視圖；以及 圖12祝明去除因過多蝕刻導致的有缺陷材料的技術。 發明詳細說明
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k- 現在參^目1 A ’其示出了起始絕緣體上碎（SOI)基板 100的頂視圖。如分別與圖1A中所示的截面和2-2 對應的圖1B和1C所示，基板100包括主體基板106、掩 埋氧化物（BOX)層108和主動層11〇。圖⑴和1€還示出了 主動層U〇上的氧化物緩衝膜（pad film) 102和氮化物緩衝 月吴104。熟習於本領域者將意識到較佳係具有設置在氮化 物緩衝膜104頂部上的氧化物緩衝膜1〇2。緩衝氧化物1〇2 使用標準氧化技術生長，且典型地將在3至14nm的範圍 内’較佳為8nm。緩衝膜104設置在緩衝氧化物ι〇2上。 較佳的是氮化物膜被用作緩衝膜1〇4，雖然也可使用其他 材料。氮化物（上）緩衝膜1〇4 一般在30至12〇11111的範圍之 間，較佳為80nm，且定義用於淺槽隔離（STI)成型的蝕刻 區域。 主動元件層110係被圖案化以形成矽通道將形成在其上 的邊緣112。用於形成將要成為通道區的主動層11〇的寬 度113不是關鍵的，然而其必須足夠寬以用於掩蔽並且足 夠窄以限制過度蝕刻，因而提供了適當且實用的製造容 差。較佳係在此階段根據熟習於本領域者所公知的傳統加 -11-
526564 A7 B7 ____ 五、發明説明（9 ) 工技術形成矽區域，此區域將成為源極114和汲極116區 域和接觸區域118、120。 在蝕刻終止層202的磊晶生長和通道204後續的磊晶生 長之後，圖2A、2B和2C分別相應於圖1A、1B和1 C。 較佳係蝕刻終止層包括S i( 0.3 ) Ge( 0 · 7 )，且磊晶生長通 道包括矽或具有鍺和/或碳的矽合金。藉由將應變添加到 通道和/或改變穿過通道的導帶和價帶以改變元件的臨限 值（threshold)或提高載子輸運，矽與其他IV族元素的合金 (尤其是鍺和碳）也可用於最佳化FET的特性。對於熟習於 本領域者顯而易見的是，在形成蝕刻終止層202和通道 204前，使用適當的清潔處理以去除氧化物緩衝膜104下 方的矽110的一部分。被去除的矽的寬度應當大致等於蝕 刻終止層202和通道204的總寬度。 雖然選擇性沈積是較佳的，但是如果蝕刻過度了，可以 要求蝕刻終止層202和通道204的非選擇性磊晶沈積。較 隹的是，層202的厚度大約是5nm。平面化（faceting)將極 其依賴於磊晶生長的細節。尤其是使用選擇性磊晶生長， 當抵達開口邊緣時，平面化可以改變磊晶區域的厚度。因 為相對於生長高度通道凸出得非常薄，所以通道將受到影 響的區域可能較小。引發錯位（dislocation)前的允許厚度對 Ge的百分率是敏感的，並隨Ge百分率的增加迅速減小（見 Phys· Stat. Sol· (a)雜誌 1996 年第 155 卷第 14 1 頁 A.菲謝 爾（A · Fischer)和Η ·庫勒（Η · Kuhne)的“應變層結構的臨 界劑量（Critical Dose for Strained Layer Configuration) ”）o -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 526564 A7 B7 五、發明説明（11 ) 内暴露的矽no。 然後蝕刻光罩開口 304内暴露的矽110。因為在此蝕刻 過程中不是所有的矽110被去除，所以矽層110也被橫向 蝕刻，在蝕刻終止層202上終止（見1988年10月《IEEE國 際絕緣體上矽（SOI)會議論文集（Proc. IEEE International Silicon on Insulator (SOI) Conference)》第 145- 146 頁 K.D· 赫伯特（K. D. Hobart)，F.J·庫伯（F. J. Kub)，Μ·Ε·特維 戈（Μ · E · Twigg)，G.G.傑尼耿（G. G. Jemigan)，P . E ·湯 普森（P . E · Thompson)的“超切口：用於具有超薄（< 5nm) 石夕膜的 SOI基板的製造的簡單技術（Ultra-cut: a Simple Technique for the Fabrication of SOI Substrates with Ultra-Thin (< 5nm) Silicon Films) ”）。KOH 可以用作姓刻劑，其 對Si_.Si(0.3)Ge(0.7)具有大約20:1的選擇性，然而公開 了 NH4〇H對25% Ge膜具有比100:1更好的選擇性（見《電 化學學會學報（J. Electrochem. Soc·)》1997年3月第144 卷第3期第L37頁G·王（G. Wang)等人的“使用NH4OH 溶液的 Si對Si( 1 -x)G(x)的高選擇性化學蝕刻（Highly Selective Chemical Etching of Si vs. Si(l-x)G(x) Using NH4OH Solution)，，）。 因而，由於具有約70nm的重疊和約20nm的邊緣容差， 故所希望厚度約為85nm。假設20%的過度蝕刻，將需要 100nm的蝕刻。於是，當KOH用作蝕刻劑時，最差情況的 SiGe侵蝕將是約5nm，且當NH4OH用作姓刻劑時，約為 lnm 〇 -14 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐）
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線 526564 A7 B7 五、發明説明（12 ) 接著，對蝕刻終止層202進行選擇性蝕刻至通道204。 對於70%的 Ge膜，HF: Η 2 Ο 2 : CH3COOH的選擇性約為 1000: 1。假設 10nm的蝕刻，則因而矽侵蝕可忽略。對於 50% 的 Ge 膜，HN〇3:H20:HF(40:20:5)的選擇性約為 25: 1。有效的HF稀釋液約為12: 1。氧化物的侵姓將是顯 著的，但根據熟習於本領域者所公知的傳統處理步驟則是 可控制的。HN〇3: H20: HF的钱刻速率約為40nm/min，建議 非常短的曝光且為了控制可能允許進一步的稀釋。（見 1992年《電化學學會學報（J · Electrochem. Soc.)》第139 卷第10期第2943頁D· J·戈德貝（D· J· Godbey)等人的 “使用 HN〇3和HF的Si( 1-x)Ge(x)從< 100>矽上的選擇 性去除（Selective Removal of Si( 1 - X ) Ge( X ) from Si Using HN03 and HF) ”）。如果需要，可以根據熟習於本領域者 所公知的傳統處理步驟除去隔離襯302。 在主動層10和蝕刻終止層202的蝕刻後，圖4A和4B分 別對應圖3 A和3B。如果需要，可以根據熟習於本領域者 所公知的傳統處理步驟塗覆修整光罩以去除不需要的翼片 402。圖5示出第二通道502形成後的圖4A的元件，如同 熟習於本領域者將容易認識到的那樣，該通道可以藉由使 用與對第一通道204的先前描述相同處理步驟形成。 在形成第一通道204和第二通道502區域後，完成雙閘 極電晶體所需的最終處理步驟的第一序列將描述如下。 現在參照圖6，圖5中的通道204和502與可用於形成 另一閘極結構的延伸通道602 —起得以顯示。於是，熟習 -15- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐）
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春- 526564 A7 B7 ，五、發明説明（13 ) 於本領域者應當理解，除所示通道204、502和602外，基 板100可以包括多個通道。此處，基板100因而包括主體 基板102、BOX層104和通道204、502及602。 裝 於是，在圖7中，提供了標準STI填充物702，較佳係 約300至5OOnm厚的二氧化碎層。然而，熟習於本領域者 所公知的其他適宜材料也可用作犧牲膜。較佳係藉由掘光 使STI表面平坦化。
線。 圖8A是圖11B的沿1 - 1截面的代表性橫截面圖。圖8 A 因為多晶矽導體（PC)抗蝕光罩802和STI填充物702在圖 8A中的製造過程中出現，卻未出現在圖11B的對應區141 中而具有代表性。在STI填充物702的所選區域上設置PC 抗蝕光罩802後，相對於緩衝膜104選擇性蝕刻STI填充 物702並往下至BOX層108。較佳的但不是必須的是，蝕 刻也可以相對於BOX層108是選擇性的。然後，相對於 STI填充層702和BOX層108選擇性地去除緩衝膜104。圖 9A和10A示出了，如果需要，緩衝層104可以留下以使得 薄閘極電介質904僅在通道204、502和602的側壁上。較 佳的是，在每次蝕刻中約10: 1的選擇度，這可用具現有 技術水準的蝕刻完成。如果需要，可以選擇性地在此點引 入阱佈植。這些佈植物將使用高角度佈植完成，較佳地在 10至45度的範圍内，每次佈植相互之間旋轉約90度以充 分摻雜擴散區的側壁。為了避免比側部更多地摻雜擴散區 的表面層，佈植可以在去除PC抗蝕光罩802暴露區内的 缓衝膜104之前進行。 -16- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 526564 A7 B7 五、發明説明（14 ) 圖8B是圖11B所示截面2 - 2的代表性橫截面圖。圖8B 因為PC抗蝕光罩802和STI填充物702在圖8B中的製造 過程中出現，卻未示出在圖11B中源極114、汲極116和 閘極902之間的區域内而具有代表性。圖8B於是示出製 造過程中PC光罩802的選擇性設置。這可以利用使用較 佳地包括光阻或硬光罩的PC光罩的標準圖案化微影蝕刻 技術完成。 圖9A示出了閘極電介質904(例如Si〇2)生長和閘極導體 902沈積之後的圖8A的基板。應當被理解的是氮氧化物、 氮化物/氧化物的複合物、金屬氧化物（例如 Al2〇3、 ZrSi04、Ti〇2、Ta205、Zr02 等）、鈣鈦礦（例如（Ba， Sr) Ti03、La203)及其混合物也可用作電介質。在每個通道 204、502和602上的閘極電介質的生長可以是根據傳統方 法的標準爐或單晶片室氧化。如果需要，氮化物（如 N20、NO或N2佈植）可以在氧化之前、之中或之後引入。 在每個通道204、502和602上的閘極電介質的沈積可以藉 由例如化學氣相沈積（CVD)或熟習於本領域者公知的其他 技術來完成。 在蝕刻後，沈積閘極9 02。閘極導體的沈積可以使用傳 統CVD或直接濺射技術完成。應當理解的是，可以使用 非多晶矽的閘極導體。例如，可以使用SiGe混合物、高 熔點金屬（例如 W)、金屬（例如Ir、A卜Ru、Pt)和TiN。 總體上，可以使用能拋光的並具有高電導率和合理功函數 (workfunction)的任何材料替代多晶矽。在沈積後，根據傳 -17- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
裝 訂

Claims (1)

  1. A B c D 526564 六、申請專利範圍 位、孩源極區和汲極區之間的中心部，並實質與該 極區及該汲極區平行。 5.如申請專利範圍第2項的場效應電晶體，另包括接觸 該閘極頂表面的石夕化物層。 6·如申請專利範圍第2項的場效應電晶體，另包括接觸 忒閘極的第一侧端部和第二侧端部的電介質層。 7 .如申請專利範圍第2項的場效應電晶體，另包括接觸 該通道侧表面的電介質。 8 ·如申請專利範圍第2項的場效應電晶體，其中該閘極 包括多晶;^。 9 .如申請專利範圍第2項的場效應電晶體，其中該通道 大致為該場效應電晶體長度的四分之一。 10·如申請專利範圍第2項的場效應電晶體，另包括用於 將閘極電隔離成兩個電絕緣部分的電介質材料，每個 部分具有共面的頂表面和在每個各自共面的頂表面上 的接觸緩衝層。 11·如申請專利範圍第2項的場效應電晶體，其中該系晶 通道由第IV族元素的組合物形成。 12·如申請專利範圍第2項的場效應電晶體，其中該系晶 通道由石夕和第IV族元素的合金形成。 13.如申請專利範圍第2項的場效應電晶體，其中該系晶 通道由矽與鍺和碳中的至少一個的合金形成。 14· 種形成雙閘極場效應電晶體的方法，包括·· 在基板上形成第一和第二系晶生長通道； -2- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 〜 ' ---
    526564 、申請專利範圍 蝕刻矽層中的區域以形成源極和汲極，其中源 極的一侧表面接觸第一和第-4 及 部表m 一長通通的相對端 形成閘極，其接觸第一和第二暴晶生長通道的 和兩個侧表面以及基板的頂表面。a如申請專利範圍第14項的方法，其巾㈣成步费 括： 形成第一和第二矽線，矽線的每個端部接觸源極和 極的一端； 在第一和第二矽線各自的被暴露的侧表面上形成蝕 終止層； 在各蝕刻終止層上磊晶生長第一和第二矽層； 蝕刻掉第一和第二矽線及蝕刻終止層； 用氧化物填充物填充圍繞第一和第二磊晶生長矽層 區域以及在源極和汲極之間的區域； 蝕刻氧化物填充物的一部分以形成定義閘極的區域 其中足義間極的區域位於源極和汲極之間的中心部 與該源極及汲極實質平行；以及 沈積材料以形成閘極。 16.如申請專利範圍第15項的方法，另包括下列步驟： 銀刻閘極和源極之間的氧化物填充物以曝露第一和 二羞晶生長碎層；以及 蝕刻閘極和汲極之間的氧化物填充物以曝露第一和 —系晶生長碎層。 包 的 並 第 第 本纸張尺度適财g ®家標芈(⑽）A4規格(210x297公i) 526564
    17·如申請專利範圍第16項的方法， 磊晶生長矽層上形成氧化物的步驟。匕括在第一和第二 18·如申請專利範圍第1?項的方法，龙 化矽。 V、疼氧化物為二氧 19·如申請專利範圍第16項的方 盤石曰丄P 包括下列步驟· 广生切層在問極和源極間的部分進行体植;以 對磊晶生長矽層在閘極和汲極間的部分進行佈植 2〇·如申請專利範圍第19項的方法，其中該伟丁植步驟係在 相對於垂直於磊晶生長矽層頂表面的向量的1〇至“度 的範圍内進行。 21·如申請專利範圍第19項的方法，其中該等佈植係以相 互間隔90度系列地進行。 22.如申請專利範圍第14項的方法，另包括在閘極、源極 和汲極上各形成接觸部的步騾。 23·如申請專利範圍第14項的方法，其中該閘極材料為多 晶石夕0 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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