FR2995720B1 - Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes - Google Patents

Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes

Info

Publication number
FR2995720B1
FR2995720B1 FR1202479A FR1202479A FR2995720B1 FR 2995720 B1 FR2995720 B1 FR 2995720B1 FR 1202479 A FR1202479 A FR 1202479A FR 1202479 A FR1202479 A FR 1202479A FR 2995720 B1 FR2995720 B1 FR 2995720B1
Authority
FR
France
Prior art keywords
field
effect device
independent grid
field effect
making independent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1202479A
Other languages
English (en)
Other versions
FR2995720A1 (fr
Inventor
Philippe Coronel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1202479A priority Critical patent/FR2995720B1/fr
Priority to PCT/FR2013/000246 priority patent/WO2014044929A1/fr
Priority to US14/429,153 priority patent/US9236262B2/en
Publication of FR2995720A1 publication Critical patent/FR2995720A1/fr
Application granted granted Critical
Publication of FR2995720B1 publication Critical patent/FR2995720B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR1202479A 2012-09-18 2012-09-18 Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes Expired - Fee Related FR2995720B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1202479A FR2995720B1 (fr) 2012-09-18 2012-09-18 Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes
PCT/FR2013/000246 WO2014044929A1 (fr) 2012-09-18 2013-09-18 Procédé de réalisation d'un dispositif à effet de champ à double grille à grilles indépendantes
US14/429,153 US9236262B2 (en) 2012-09-18 2013-09-18 Process for producing a double-gate field-effect device having independent gates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1202479A FR2995720B1 (fr) 2012-09-18 2012-09-18 Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes

Publications (2)

Publication Number Publication Date
FR2995720A1 FR2995720A1 (fr) 2014-03-21
FR2995720B1 true FR2995720B1 (fr) 2014-10-24

Family

ID=47080594

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1202479A Expired - Fee Related FR2995720B1 (fr) 2012-09-18 2012-09-18 Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes

Country Status (3)

Country Link
US (1) US9236262B2 (fr)
FR (1) FR2995720B1 (fr)
WO (1) WO2014044929A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9601513B1 (en) 2015-12-22 2017-03-21 Globalfoundries Inc. Subsurface wires of integrated chip and methods of forming

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689127A (en) * 1996-03-05 1997-11-18 International Business Machines Corporation Vertical double-gate field effect transistor
US6483156B1 (en) * 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
US6642115B1 (en) * 2000-05-15 2003-11-04 International Business Machines Corporation Double-gate FET with planarized surfaces and self-aligned silicides
US7163864B1 (en) * 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6580132B1 (en) * 2002-04-10 2003-06-17 International Business Machines Corporation Damascene double-gate FET
US6946696B2 (en) * 2002-12-23 2005-09-20 International Business Machines Corporation Self-aligned isolation double-gate FET
WO2004088757A1 (fr) * 2003-03-28 2004-10-14 Fujitsu Limited Dispositif a semi-conducteurs et procede de fabrication associe
US7056773B2 (en) * 2004-04-28 2006-06-06 International Business Machines Corporation Backgated FinFET having different oxide thicknesses
US7202117B2 (en) * 2005-01-31 2007-04-10 Freescale Semiconductor, Inc. Method of making a planar double-gated transistor
US7087966B1 (en) * 2005-05-18 2006-08-08 International Business Machines Corporation Double-Gate FETs (field effect transistors)
JP4940797B2 (ja) * 2005-10-03 2012-05-30 セイコーエプソン株式会社 半導体装置の製造方法
JP2007134366A (ja) * 2005-11-08 2007-05-31 Seiko Epson Corp 半導体装置および半導体装置の製造方法
US7659579B2 (en) * 2006-10-06 2010-02-09 International Business Machines Corporation FETS with self-aligned bodies and backgate holes
US7888742B2 (en) * 2007-01-10 2011-02-15 International Business Machines Corporation Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts
EP2235745A1 (fr) * 2007-12-21 2010-10-06 Nxp B.V. Procédé de fabrication amélioré pour des transistors à grille indépendante ou à grille enveloppante
FR2951028B1 (fr) * 2009-10-05 2012-08-03 Commissariat Energie Atomique Memoire organique a double grille et procede de realisation
FR2952472B1 (fr) * 2009-11-12 2012-09-28 Commissariat Energie Atomique Procede de realisation de transistors a effet de champs avec une contre-electrode et dispositif semi-conducteur
EP2325873A1 (fr) * 2009-11-23 2011-05-25 STMicroelectronics (Crolles 2) SAS Procédé de fabrication d'une membrane suspendue et transistor MOS à double grille

Also Published As

Publication number Publication date
WO2014044929A1 (fr) 2014-03-27
US9236262B2 (en) 2016-01-12
US20150249014A1 (en) 2015-09-03
FR2995720A1 (fr) 2014-03-21

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