TW463272B - Resin-encapsulated semiconductor device - Google Patents
Resin-encapsulated semiconductor device Download PDFInfo
- Publication number
- TW463272B TW463272B TW89118927A TW89118927A TW463272B TW 463272 B TW463272 B TW 463272B TW 89118927 A TW89118927 A TW 89118927A TW 89118927 A TW89118927 A TW 89118927A TW 463272 B TW463272 B TW 463272B
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- metal
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 133
- 239000002184 metal Substances 0.000 claims description 133
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- 229920005989 resin Polymers 0.000 claims description 30
- 239000011347 resin Substances 0.000 claims description 30
- 230000002079 cooperative effect Effects 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 11
- 238000009713 electroplating Methods 0.000 claims description 10
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- 238000007747 plating Methods 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 3
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- 230000008018 melting Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 2
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- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
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- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
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- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
經濟部智慧財產局員工消費合作社印製 4 6327 2 A7 ____ B7 五、發明說明(1 ) 發_..明之範圍 本發明係關於樹脂密封的半導體裝置,特別係關於適合 於球狀柵極陣列封裝體(BGA )半導體裝置之樹脂密封的半 導體裝置結構。本發明亦關於用於製造該半導體裝置方法 〇 發明之相關技術 爲了降低半導體裝置之尺寸,近來已增加BGA半導體裝 置之使用。第1圖顯示傳統之BGA半導體裝置結構,其中 固定半導體晶片31於插入基板32之中央區域上,以及以 黏著於其上之半導體晶片31之底部表面,固定於插入基板 32上。該插入基板32是由如聚醯亞胺 '玻璃環氧樹脂、;BT 樹脂等之有機絕緣體所製成,並於其上提供例如由銅製成 之金屬互連圖案34。 插入基板32在其外部周圍之附近,即在用於安裝半導體 晶片31之外部區域具有複數個接合腳位34。該接合腳位 34之內側35被稱爲縫合區域,並被利用爲與接合線4〇之 連接;反之,該接合腳位34之外側36被稱爲紋間表面區 域,於其上形成錫球38。插入基板32之有機絕緣體37具 有用於紋間表面36之開口’並於其底層表面上形成錫球38 。該錫球38被終端使用者利用作爲外部接頭來安裝半導體 裝置於印刷電路板上》 如下所述來進行安裝半導體晶片31至插入基板32上。 首先,由多噴嘴塗佈機滴落特定量之接著劑33至插入基板 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -,J 裝 ------訂-------- 經濟部智慧財產局員工消費合作社印製 在 6 327 2 A7 ____B7___ 五、發明說明(J ) 32之特定位置上,然後安裝半導體晶片31於其上,並加熱 接著劑3 3以固定半導體晶片3 1於插入基板3 2上。接著* 以使用由金或銅製成之接合線4 0的連線焊接技術來電通連 鋁晶片電極39與接合腳位34之縫合區域35在一起成爲31 。之後,以使用於其中含有環氧樹脂爲主要成分之模具樹 脂41的轉移成型技術,將插入基板32之頂層表面與半導 體晶片31密封在一起,因而保護半導體晶片31避免機械 性的損害及濕氣侵入。 接著,在插入基板32上之接合腳位34的紋間表面區域 36之底層表面上,形成包括外部接頭的錫球38。於此步驟 中,預先應用助熔劑至紋間表面區域3 6上,然後將錫球3 8 置於該紋間表面區域3 6上,接著以錫球3 8之熱回流來形 成外部接頭3 S。該外部接頭3 8由例如包含錫及鉛作爲主要 成分之焊劑所製成。 在如前述之傳統BGA半導體裝置中’包含有機絕緣體及 金屬互連圖案之插入基板雙層結構,則避免具有該插入基 板之BGA半導體裝置的厚度降低。 專利發表 IP-A-2-240940 ' -10-116935 及-11-195733 個 別描述用於以在底層表面硏磨由樹脂製成的插入基板’來 降低半導體裝置厚度之技術。 於所描述之技術中,其中有一個缺點爲使具有較高不純 度之金屬互連層形成之電鍍技術’難以使用於樹脂之插入 基板上。雖然其中某個技術以提供電極膜於樹脂基板上’ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---------裝 ----1Ϊ— 訂··------線 〈請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 46327 2 A7 ___B7__ 五、發明說明) 可使用電鍍技術於樹脂基板上,但是該電極膜必須延伸至 該樹脂基板之外部周圍’並因而在該不需要金屬互連圖案 之外部周圍形成金屬互連圖案。 此外,在傳統之半導體裝置中,於決定用於接合線之縫 合區域之排列後,因而在縫合區域之外側決定了用於接合 腳位之紋間表面區域的位置,其強制一個大的限制於外部 接頭之配置上,並導致對於安裝在半導體裝置上之電子裝 置或電子零件之平面尺寸減小的障礙。 特別地,隨著近來之電子裝置及零件的尺寸減小’而需 求半導體裝置中的外部接頭之節距減小。在此方面,雖然 由於微影成像技術的發展,而對於接合腳位已經達成金屬 互連圖案中之節距減小至某程度,但是由於必須有大的空 間來形成錫球,而使得對於外部接頭之節距減小尙未成功 0 發明之說明 因此本發明之目的爲以改善傳統之BGA半導體裝置之結 構因而減小整體尺寸,並在所希望之位置形成具有優異之 連接能力,來解決上述之問題以及降低成本與BGA半導體 裝置之尺寸。 關於第一方面,本發明提供包含於其上具有晶片電極之 半導體晶片、具有連接晶片電極及支撐半導體晶片之頂層 表面的金屬互連圖案、以電鍍技術至少形成金屬互連圓案 之頂層表面、覆蓋金屬互連圖案之底層表面及於其中具有 本纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ·1—--訂------- - - (請先閱讀背面之注意事項再填寫本頁) 463272 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(4 ) 有穿孔之絕緣膜、於穿孔中形成複數個外部接頭於互連圖 案之底層表面上、以及密封半導體晶片於金屬互連圖案與 絕緣膜上之模具樹脂。 根據本發明之半導體裝置’以應用其中僅形成薄絕緣膜 及電鍍之互連圖案於半導體晶片之底層表面上之結構,相 對於具有插入基板之傳統半導體裝置,可降低半導體裝置 之整體厚度。 此外,該已電鍍之互連圖案具有已改善之信賴度,因而 使得對於安裝於半導體裝置上之電子裝置與零件的品質改 善,並降低尺寸與成本。 關於第二方面,本發明亦提供用於形成包含形成具有形 成於金屬板之頂層表面的圖框基板之步驟的半導體裝置、 安裝半導體晶片於互連圖案、以模具樹脂密封半導體晶片 於圓框基板上、及除去至少一部份在底層表面之金屬板以 曝光至少一部份金屬互連圖案之方法。 根據本發明之方法,以模具樹脂密封半導體晶片後除去 圖框基板之金屬板以曝光互連圓案之製程1確保在密封前 之半導體裝置的優異剛性,並降低於密封後之半導體裝置 的整體厚度。 簡厘之圖面說明 第1圖爲具有插入基板之傳統BGA半導體裝置之剖面圖^ 第2圓爲依據本發明實例的半導體裝置之剖面圖。 第3A至3D圖爲展示於第2圖之圖框基板的剖面圖,其 本紙張尺度適用中固國家標準(CNS)A4規格(210 X 297公釐) I -----------1 r _ I-----I ^--I------ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 463272 ΚΙ __Β7____ 五、發明說明(r ) 展示關於製造方法之連續步驟。 第4A至4D圖爲展示於第2圖之圖框基板之剖面圖,其 展示關於製造之其他方法的連續步驟。 第5A至爲第1圖之半導體裝置之剖面圖,其展示 關於依據本之第一實例之製造方法的連續步驟。 第6A至爲半導體裝置之剖面圖,其展示關於依據 本.發明之第例之製造方法的連續步驟。 第7A至7F^i爲半導體裝置之剖面圖,其展示關於依據 本發明之第三實例之製造方法的連續步驟 第8A至SF圖爲半導體裝置之剖面圖,其展示關於依據 本發明之第四實例之製造方法的連續步驟。 第9A至9F圖爲半導體裝置之剖面圖,其展示關於依據 本發明之第五實例之製造方法的連續步驟。 第10A至1 OF圖爲半導體裝置之剖面圖,其展示關於依 據本發明之第六實例之製造方法的連續步驟》 第11A至11D圖爲半導體裝置之剖面圖,其展示關於依 據本發明之第七實例之製造方法的連續步驟。 第12A至1 2D圖爲半導體裝置之剖面圖,其展示關於依 據本發明之第八實例之製造方法的連續步驟。 第13圖爲關於依據本發明之其他實例之半導體裝置之剖 面圖。 第14圖爲關於依據本發明之其他實例之半導體裝置之剖 面圖。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --- I -----— II i --------«— — — — —lit > (請先閱讀背面之注意事項再填寫本頁) 463272 經濟部智慧財產局員工消費合作杜印製 Α7 Β7 五、發明說明(士) 第15圖爲關於依據本發明之其他實例之半導體裝置之剖 面圖。 之較佳實例 現在,以參考附帶之圖示來更爲明確地說明本發明,其 中以相同之數字設定相同組成元件至某程度。 參考第2圖,依據本發明之實例的半導體裝置,包含以 使用模具樹脂1 7之轉移成型技術所密封之半導體晶片1 5 。以使用一絕緣接著劑層20來固定半導體晶片15的底層 於中央區域來固定該半導體晶片丨5於金屬噶圓案14上, 或晶片接腳上。 連接各個形成於半導體晶片15上之晶片電極26於配置 在半導體晶片外側之金屬膜圖案1 4的縫合區域;配置複數 個紋間表面圖案13於金屬膜圓案14之底層表面上。以使 金屬板形成圖案來形成紋間表面圓案1 3,並於各個紋間表 面圖案13之底層形成錫球18。以塗佈於除了紋間表面圖案 13之整個半導體裝置之底層表面上,來形成絕緣接著層19 =以使用其中以金屬互連圖案14支撐半導體晶片15之結 構,可顯著降低最後半導體裝置之整體厚度。 於另一情況,可忽略紋間表面圖案1 3而直接配置錫球1 8 於金屬互連圖案14上’其可進一步降低最後半導體裝置之 整體厚度。 配匱某些錫球(第一錫球)1 8於恰低於半導體晶片1 5之 金屬互連圖案14之內側上’反之’如見於半導體裝置之底 本紙張尺度適用中國國家標準<CNS)A4規格(210 x 297公愛) — —ΙΙΙΙΙΙΙΙΙΊ — - I ---I I — * I I I--I i I (請先閱讀背面之注^項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 463272 A7 _____B7_ 五、發明說明) 層表面,配置其他錫球(第二錫球)18於位於半導體晶片15 之外側的金屬互連圖案1 4之外側上。 交替地以彼此來配置第一錫球18與第二錫球1S。第一錫 球1 8被配置恰低於半導體晶片1 5之外部周圍;第二錫球 1 8則被配置恰低於連接於壓接線1 6之縫合區域。第一錫球 1 8與第二錫球1 8之交替配置,使錫球1 8在彼此間沒有干 擾下,而具有小的節距。 第3A至3D圖展示用於形成使用於製造第2圖之半導體 裝置的圖框基板之製程。第3A圖中,首先製備金屬板11 ,其中於其上以塗布形成光阻膜12,接著如第3B圖所示, 以形成圖案來形成負片型光阻圓案1 2,其相對於所希望之 互連圖案爲負片型。然後如第3C圖所示,形成金屬互連圖 案14於以電鍍技術曝光之金屬板11之表面,接著如第3D 圖所示,除去負片型光阻圖案12以獲得圖框基板,其中形 成金屬互連圖案14於金屬板11上》 第4A至4D圖展示另一個用於形成使用於製造第2圖之 半導體裝置的圖框基板之製程。第4A圖中,首先製備金屬 板1 1,接著於其上形成正片型光阻圖案1 2,其相對於所希 望之互連圖案爲正片型。然後如第4C圖所示,使用正片型 光阻圖案1 2作爲蝕刻遮罩來蝕刻金屬板1 1,接著從金屬板 1 1除去正片型光阻圖案1 2。因此,獲得圖框基板1 3,而其 中形成紋間表面圖案14作爲在金屬板11之頂層表面的金 屬互連圖案。 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) -----------1 i - ------- 訂-- ------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消費合作社印製 463272 A7 ___B7_ 五、發明說明(f ) 第5A至5G圖展示對於依據本發明之第一實例之半導體 裝置的製造製程。第5A圖中’以如第3A至3D圖所示之製 程,製備圖框基板(或可被稱爲暫時插入基板),其中形成 金屬圖案14於金屬板11上。如第5B圖所示,安裝其底層 塗接著劑20之半導體晶片]5於圖框基板上,並同時將半 導體晶片1 5之外部周圍置於圖框之金屬圖案1 4的內側上 。接著,如第5 C圖所示,半導體晶片1 5上之晶片電極2 6 電通連於以接合線1 6配置於金屬圖案1 4外側之縫合區域 1接著以使用模具樹脂1 7之轉移成型技術,密封半導體晶 片15於圖框基板之頂層表面上。 之後,如第5 E圖所示,以濕蝕刻或電漿蝕刻在底層表面 除去圖框基板之金屬板11,以在金屬互連圖案14之底層表 面上留下紋間表面圖案丨3 »無論於金屬互連圖案1 4之外側 或內側,均可輕易地形成紋間表面圖案1 3,因此可改善對 於紋間表面圖案13之位置的設計選擇。 在使金屬板1 1形成圖案之後,如第5F圖所示,塗絕緣 接著劑於已形成圖案之表面以彤成絕緣層1 9 1其中被紋間 表面圖案13上形成錫球18,獲得如第5G圖所示之結構。 在本實例中,交替地配置錫球18於金屬圖案14之內側 或外側。另一方面,可配置錫球1 8於底層表面之方格交錯 的圖案上。此表面配置使外部接頭被配置於半導體裝置之 大致上整個之底層區域,因而減小半導體裝置之平面尺寸 〇 -1 0- 本紙張尺度適用中國國家標準<CNS)A4規格(210 X 297公釐) I I I I I ,1— ill--I I 訂1 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 327 2 A7 _____B7 五、發明說明(?) 上述製程中,可由列舉之順序來對調塗布絕緣接著劑1 9 與形成錫球1 8之順序。此外,可忽略錫球]8,以利用其他 已知之技術,直接安裝電子裝置或零件之接頭於紋間表面 圖案1 3上。 於上述製程之改進中,可由CMP(化學機械硏磨)製程來硏 磨金屬板1 1而不留下紋間表面圓案1 3。於此情況下,可直 接於金屬互連圖案之底層表面上形成錫球18。 第6A至6G圖連續展示對於依據本發明之第二實例之半 導體裝置的其他製造製程,該製程包含形成圖框基板之步 驟。第6A圖中,以塗布形成絕緣接著層21於金屬板1]上 ’接著如第6B圖所示,形成圖案來形成接著層21中之開 口 2 2。於其內來接受錫球的開口 2 2則被排列成放置於半導 體晶片之外部周圍下的一排,另一排則位於安裝於半導體 晶片上之外側區域。配置二排開口 2 2成交錯排列。 之後’如第6C圖所示,黏著金屬膜23於絕緣接著層21 上’接著如第6D圖所示,於金屬膜23形成圖案,於其內 形成中央開口 24且形成金屬互連圖案。 然後塗絕膜接著劑2 5於中央開口 2 2中,以及放置具有 應用相同絕緣接著劑2 5於其上之底層的半導體晶片1 5於 金屬互連圖案23,以致於半導體晶片15之中央與中央開口 2 2之中央排成一列。在絕緣接著劑2 5硬化之後,如第6E 圖所示,半導體晶片15上之晶片電極26以接合線16電通 連於金屬互連圖案23。 -11 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1-------------------------j (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 327 2 A7 ______ ____B7____ 五、發明說明(p ) 之後’如第6F圖所示,密封半導體晶片1 5於金屬互連 圖案2 3之頂層及絕緣膜1 1上。然後,以如使用蝕刻劑之 化學蝕刻、電漿蝕刻、使用硏磨劑之化學機械硏磨(CMP )等 之蝕刻方式來去除金屬板11。進一步如第6G圖所示,經由 各個於金屬互連圖案2 3之底層上的開口 2 2來形成錫球1 8 。配置錫球18成交錯排列或交替地配置在金屬互連圖案 2 3之內側及外側》 上述實例中,相對於第一實例,可更輕易地進行經由開 口 22之錫球18的形成=此外,除去了在金屬板11之除去 後之絕緣接著層的形成步驟,減少了用於製造之步驟數目 。注意的是本發明之本實例中,錫球1 8的排列僅爲範例, 並可由此來修改。_ 第7A至7G圖連續展示對於依照本發明之第三實例之製 造半導體裝置的方法。第7A圓中,使金屬板或銅板51接 受頂層表面之蝕刻以形成互連圖案52,其中包含權充用於 支撐半導體晶片之支撐構件的圖案部份。該圖案部份位於 銅板5 1之中央區域" 接著,塗絕綠接著劑53於在中央圓案部份之銅板52的 頂層上,接著如第7B圖所示,安裝於半導體晶片54上並 黏著於其上。如第7C圖所示,半導體晶片54上之晶片電 極55以接合線56連接於互連圖案52。接著,如第7D圖所 示,使用模具樹脂5 7來進行轉移成形製程,密封半導體晶 片54以及接合線56於銅板51之頂層上。 * 12- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 裝--------訂---------線 (請先Μ讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 463272 A7 _______B7__ 五、發明說明(〆) 之後,如第7E圖所示,使銅板51接受於底層表面之硏 磨來除去部份銅板而非互連圖案52。然後黏著絕緣板58 於底層之互連圖案52上,接著如第7G圖所示,形成金屬 凸塊5 9於互連圖案5 2上,而金屬凸塊5 9於穿孔上穿透絕 緣板5 8。該金屬凸塊5 9則位於恰低於半導體晶片之周圍以 及半導體晶片5 4之外側。 上述實例中,直接由銅板51之頂層形成互連圖案52。在 另一方面,可由形成具有用於金屬板上之互連圖案的正片 型圖案之凹溝、並利用電鍍技術以金屬電鍍膜塡滿凹溝之 步驟來形成連圖案。稍後以於底層硏磨及選定之濕蝕刻來 除去金屬板。 第8 A至8 F圖連續展示對於依照本發明之第四實例之製 造半導體裝置的方法。本實例除了於本實例中僅使用金屬 圖案52之中央部份來支撐半導體晶片,以及使用金屬圖案 52作爲外部電極,及爲了於硏磨後之機械強度而具有稍微 較大之厚度之外,與第三實例相同。機械地表面配置金屬 圖案52之周圍部份,並使其在製造之最後步驟,於其上塗 布用於絕緣膜60之形成。使用周圍部份作爲外部引線。 第9A至9F圖連續展示對於依照本發明之第五實例之製 造半導體裝置的方法。第9A圖中,以蝕刻來形成互連圖案 52於金屬板51上。如第9B圖所示|安裝具有面朝下結構 之半導體晶片54於金屬板51上,並具有於與互連圖案52 接觸之半導體晶片54上的晶片電極55。在如第9C圖所示 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------I---- I i! (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消貲合作社印製 463272 A7 ____B7 _ 五、發明說明(P ) 之以利用模具樹脂5 7來密封金屬板5 ]上之半導體晶片5 4 之後,如第9 D圖所示,以機械硏磨來除去模具樹脂5 7之 頂層部份以及半導體晶片5 4之頂層部份。亦以機械硏磨來 除去金屬板51之底層而留下如第9E圖所示之互連圖案52 ,接著如第9F圖所示,黏著絕緣板5 S於互連圖案5 2之底 層上,並於其上形成金屬凸塊5 9。 第1 0A至1 OF圖連續展示對於依照本發明之第六實例之 製造半導體裝置的方法。本實例除了於本實例中使用互連 圖案5 2作爲外部接頭引線之外,與第四實例相同.。 第11A至11.D圖展示對於依照本發明之第七實例之製造 半導體裝置的方法。第七實例除了於本實例中在半導體晶 片54之晶片電極5 5上提供金屬凸塊61’用來連接金屬板 51上之互連圖案52之外,與第五實例類似。 第12A至1 2D圖連續展示對於依照本發明之第八實例之 製造半導體裝置的方法。本實例除了於本實例中在金屬板 51之中央形成注入孔62之外’與第六實例類似。在形成互 連圖案52之前或之後形成該注入孔62,並稍後使用於模具 樹脂之注入操作。 參考第13圖,依據本發明其他實例之半導體裝置,包含 安裝於互連圖案52之頂層之第一及第二半導體晶片54A及 5 4B,並以一般之模具樹脂5 7A來密封之。此外,相反於第 一半導體晶片54A,安裝第三半導體晶片54C於互連圖案 52之底部上。以其他模具樹脂57B來密封第三半導體晶片 -1 4 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------1!!訂 (請先Μ讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6327 2 A7 _____B7_ 五、發明說明(G ) 5 4C。相反於第二半導體晶片54B,相似於第三半導體晶片 5 4 C來安裝第四半導體晶片5 4D,並以模具樹脂5 7 C來密封 之。 於上述各個實例中,經由對金屬板5 1之頂層蝕刻以直接 於金屬板51上形成互連圖案52。對於金屬板5]在底層之 利用蝕刻技術的除去步驟中,可能發生過度蝕刻,其中金 屬互連圖案52亦被除去=因此,對於用於除去金屬板51 之蝕刻步驟,以由不同金屬製成金屬互連圖案52及金屬板 5 1爲佳。於此情況下,可由濕蝕刻選擇性地從金屬互連圖 案52除去金屬板51。在另一方面,對於由相同金屬製成金 屬板51與金屬互連圖案52,要額外加入金屬板51與金屬' 互連圖案52其中之一,以致於使兩者在蝕刻劑中具有不同 時刻速度。 參考第14圖,依據本發明其他實例之半導體裝置,包含 具有由第一金屬製成之底層51a及由第二金屬製成之頂層 51b的金屬板51。金屬互連圖案52亦由第一金屬製成。可 由不同蝕刻劑來触刻第一金屬及第二金屬。在以第一蝕刻 劑蝕刻底層5 1 a之後,以第二蝕刻劑從金屬互連圖案5 2來 選擇性地蝕刻頂層。金屬互連圖案52可於底層具有用於加 強剛性之其他金屬膜。 參考第15圓,改進自第丨4圖之實例的半導體裝置,包 含由第一金屬製成之單一金屬板51'包含由第二金屬製成 之薄底層52a及由第三金屬製成之厚頂層52b的金屬互連 -1 5 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 裝--------訂--------線 (請先閱讀背面之注意事項再填寫本頁) 4 6 3 2 7 2 A7 經濟部智慧財產局員工消費合作社印數 B7 五、發明說明(〆) 圖案52。以電鍍技術來形成第二及第三金屬。在最終薄膜 之較低的成本及較高不純度的觀點來看,電鍍技術優於非 電鍍技術。較高不純度提供較優異之連接能力。 第1 5圖中,可由化學蝕刻、物理(化學-機械)硏磨、機 械硏磨、機械剝離等來除去金屬板5 1。機械剝離可與具有 不同熱膨脹係數或不同熔點之不同金屬的提供結合在一起 上述之各個實例中,金屬板或層可例如由銅、鎳或鐵製 成。接著劑或模具樹脂則以包含熱可硬化之環氧樹脂作爲 主要成分爲佳。可使用包含錫或鉛作爲主要成分之錫球來 作爲外部接頭。 如果以電鍍技術來形成金屬互連圖案,使用於本發明之 實例中的圖框基板具有如以下所述之超越傳統插入基板的 優點。 一般以電鍍技術形成之金屬互連圖案具有較高之不純度 ,並達致優異之連接能力。於包含樹脂基板及金屬互連圖 案之傳統插入基板中,以利用形成於樹脂基板上之電極層 的電鍍技術來形成金屬互連圖案。在此情況下,爲了在電 鍍時提供電流,電極層必須延伸至樹脂基板之外部周圍》 因此,會在不需要互連圖案之周圍上形成金屬互連圖案。 可能在模具樹脂表面上,曝光形成於周圍上之金屬互連圖 案而使水分侵入。這樣會使最終半導體裝置中的金屬互連 圖案之絕緣特性或腐蝕惡化。在另一方面,可由電鍍技術 -1 6 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I---— I— --—!! t·!! — ·-- (諳先閲讀背面之注意事項再填寫本頁) 463272 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(K ) 於金屬板上所希望之位置形成本發明中之金屬互連圖案。 這樣避免了在傳統插入基板中所遭遇之劣化與腐蝕。 因爲以上所述實例僅爲舉例,所以本發明並不受限於上 述實例,並可輕易地由專精於此技術者由此進行各種的改 進與變化而不悖離本發明之範圍。 元件符號對照表 11 金 屬 板 12 光 阻 膜 13 紋 間 表 面 圓 案 14 金 屬 互 連 圖 案 15 半 導 體 晶 片 16 接 合 線 17 模 具 樹 脂 18 錫 球 1 9 絕 緣 接 著 層 20 接 著 劑 2 1 絕 緣 接 著 層 22 開 P 23 金 屬 互 連 圖 案 24 中 央 開 Π 25 絕 緣 接 著 劑 26 晶 片 電 極 31 半 導 體 晶 片 金屬膜圖案 -17- 私紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------ --裝 ----— —訂- ------1·線 Ί (請先閲讀背面之注意事項再填寫本頁) 463272 A7 B7 五、發明說明(μ ) 經濟部智慧財產局員工消費合作社印製 3 2 33 34 3 5 36 37 3 8 39 40 4 1 5 1 5 1a 5 1b 52 52a 52b 53 54 54A 5 4B 54C 5 5 56 插入基板 接合劑 接合腳位I金屬互連圖案 縫合區域 紋間表面區域 有機絕緣體 錫球,外部接頭 鋁晶片電極 拉合線 模具樹脂 金屬或銅板 金屬板5 1之底層 金屬板5 1之頂層 金屬互連圖案 金屬互連圖案5]之薄底層 金屬互連圖案51之厚頂層 絕緣接著劑 半導體晶片 半導體晶片 半導體晶片 半導體晶片 晶片電極 接合線 -18- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I I-- ----ί — 訂-- - ----- (請先閱讀背面之注意事項再,填寫本頁) 4 6 32 7 2 A7 B7 五、發明說明 57 模 具 樹 脂 57A 模 具 樹 脂 57B 模 具 樹 脂 57C 模 具 樹 脂 58 絕 緣 板 59 金 屬 凸 塊 60 絕 緣 膜 61 金 屬 凸 塊 62 注 入 孔 53 半 導 體 晶 t------——訂----1 I---線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -19 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 463272 Λ8 B8 C8 DS 六1申請專利範圍 轉"-部智慧时4^:^工消费合作社印製 體頂互並面連膜 半樹 安 '體, 部 部 接部 連 導之屬面表互之 他具 括片導' 外 外 部餘 互 半片金表層屬片 其模 包晶半 該 該 外其 屬 之晶該層底金晶 裝該 步體他 少 少 該之 金 極體成底該該體 安以 一導其 至 至 中頭 該 電導形之之於導 中並 進半該 中 中 其接 中 片半少案案及半 其面 其他封 其。其 β - 部 其 晶該至圖圖以該 ,表 ,其密 ,片,側置外 , 有撐術連連、封 置層 置的上 置晶置外裝該 置 具支技互互頭密 裝頂 裝面面 裝ita裝之體且 裝 上與鍍屬該接上 體該 體表表 體導體片導而。體 其極電金於部膜 導之 導層層 導^.導晶半,則導 於電以該、外緣 半案 半底底 半 ^ 半 I 之片^1半 括片、蓋膜個絕 之圖 之該之 之 i 之導項晶 Μ 之 包晶案覆緣數該 項連 項之案。項低項半1體片項 其該圖、絕複及 1互 1案圖脂1恰1該第導晶1 ’於連份之成面 第屬 第圖連樹第於第於圍半體第 置接互部孔形表 圍金 圍連5具圍位圍位範該導圍 裝連屬層穿內層 範該 範互屬模範份範份利於半範 體有金頂有孔頂 利於 利屬金他利部利部專低該利 導具的之具穿該。專片。專金該其專一專一請恰於專 半 '面案中該之脂請晶封請該於的請之請之申於位請 種片表圖其於案樹申體密申於及片申頭申頭如位則申 1 晶層連於上圖具如導脂如裝以晶如接如接該頭份如 . . . . . . 1 2 3 4 5 6 7 ^---------^------‘玎----一----0 (請先閱讀背面之注意事項再填鳥本頁) 本紙乐尺度適用中國國家標嗥(CNS ) Λ4規格(210x 297公釐〉 2 3 6 4 2 U0 8 8 8 ABCD 7T、申請專利範圍 圖案具有下面層及頂層之電鍍層。 8 .如申請專利範圍第I項之半導體裝置,其中以接合線連 接該晶片電極與該金屬互連圖案。 9 .如申請專利範圍第1項之半導體裝置,其中直接連接該 晶片電極與該金屬互連圖案。 連 互 屬 金 該 。 中中 其近 , 附 置的 裝圍 體周 導之 4^- 旨 At 之樹 項具 1 模 第該 圍於 範置 利配 專不 請並 申案 如圖 封板 密屬 具金 模有 成具 形成 於形 用有 種驟 一 步 之 裝 體 導 半 法 方 的 及 的上 括面 包表 其 層 頂 板 屬 金 該 於 成 形 連上 互板 該基 於框 片圖 晶該 體於 導片 半晶 裝體 安導 、 半 板該 基封 框密 圖 旨 月 的樹 案具 圖模 連以 互、 屬上 金案 之圖 少 至 以 板 屬 金 該 之 面 表 層案 底圖 在連 J互 部屬 一金 去該 除之 少份 至部 及 I 以光 、 曝 少 至 術 技 鍍 電 以 中 其 。 , 份 法部 方層 之頂 項一 1之 1 案 第圖 圍連 範互 利屬 專金 請該 申成 如形 板 屬 金 該 刻 蝕 以 中 其 法 方 之 項。 1案 I 圖 第連 圍互 範屬 利金 專該 請成 申形 如來 --:---------裝------訂------線 (請先閲讀背面之注意事項再蜂爲本頁) 經..Ji·.':'1耶智龙时Η工消骨合作社印絮 達 互 屬 金 該 著 黏 中 其 ο 法上 方面 之表 項層 1頂 1 該 第之 圍板 範屬 利金 專該 請至 申案 如圖 下 留 驟 步 去 除 該 中 其 。 , 案 法圖 方面 之表 頁間 II紋 1 爲 第作 圍板 範屬 利金 專該 請份 申部 如一 具 模 。 該孔 入射 注注 了之 爲中 中板 其屬 , 金 法該 方於 之成 項形 1用 1 第驟 圍步 範封 利密 專該 請 ’ 申脂 如樹 木紙乐尺度逋用中國國家標準 ( CNS ) Α4規格(210Χ297公釐) A8 B8 C8 D8 463272 六、 申請專利範圍 1 7 .如申請專利範圍第1 1項之方法’其進一步包括黏著絕 緣膜於該金屬互連圖案之已曝光的表面上。 1 8 .如申請專利範圍第1 I項之方法,其中除去步驟至少包 含化學蝕刻' 化學機械硏磨、機械硏磨及機械剝離中的 一種。 1 9 ·如申請專利範圍第1 1項之方法,其中該除去步驟包含 與利用熱膨脹係數差異或熱熔點寒異結合之機械剝離 〇 20.如申請專利範圍第11項之方法’其進—步包括的步驟 爲以硏磨除去該模具樹脂及該半蹲體晶片之頂層部份 —^---------装------.订------線‘ (請先閲請背面之注意事項再姨寫本筲) 經濟部晳&5:4功-^工消費合作社印製 本紙任尺度適用中國國家標嗥(CNS)八4現格(2iox 297公着)
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JP4110992B2 (ja) * | 2003-02-07 | 2008-07-02 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004259886A (ja) * | 2003-02-25 | 2004-09-16 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004281818A (ja) * | 2003-03-17 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、キャリア基板の製造方法、半導体装置の製造方法および電子デバイスの製造方法 |
JP4069771B2 (ja) * | 2003-03-17 | 2008-04-02 | セイコーエプソン株式会社 | 半導体装置、電子機器および半導体装置の製造方法 |
JP2004281920A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
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2000
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- 2000-09-15 KR KR10-2000-0054182A patent/KR100383112B1/ko not_active IP Right Cessation
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- 2000-09-18 US US09/664,061 patent/US6611063B1/en not_active Expired - Fee Related
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SG97935A1 (en) | 2003-08-20 |
GB0202655D0 (en) | 2002-03-20 |
KR100383112B1 (ko) | 2003-05-12 |
GB2360629B (en) | 2002-04-24 |
KR20010030395A (ko) | 2001-04-16 |
US6611063B1 (en) | 2003-08-26 |
GB2369245B (en) | 2002-11-20 |
GB0022745D0 (en) | 2000-11-01 |
CN1289147A (zh) | 2001-03-28 |
JP2001156212A (ja) | 2001-06-08 |
GB2360629A (en) | 2001-09-26 |
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