TW373235B - Method for fabricating a semiconductor device using lateral gettering - Google Patents
Method for fabricating a semiconductor device using lateral getteringInfo
- Publication number
- TW373235B TW373235B TW086113689A TW86113689A TW373235B TW 373235 B TW373235 B TW 373235B TW 086113689 A TW086113689 A TW 086113689A TW 86113689 A TW86113689 A TW 86113689A TW 373235 B TW373235 B TW 373235B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- gettering
- semiconductor
- semiconductor device
- section
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 6
- 238000005247 gettering Methods 0.000 title abstract 4
- 238000000034 method Methods 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/740,580 US5753560A (en) | 1996-10-31 | 1996-10-31 | Method for fabricating a semiconductor device using lateral gettering |
Publications (1)
Publication Number | Publication Date |
---|---|
TW373235B true TW373235B (en) | 1999-11-01 |
Family
ID=24977163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086113689A TW373235B (en) | 1996-10-31 | 1997-09-20 | Method for fabricating a semiconductor device using lateral gettering |
Country Status (5)
Country | Link |
---|---|
US (1) | US5753560A (zh) |
EP (1) | EP0840367A3 (zh) |
JP (1) | JPH10135226A (zh) |
KR (1) | KR100326694B1 (zh) |
TW (1) | TW373235B (zh) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19538005A1 (de) * | 1995-10-12 | 1997-04-17 | Fraunhofer Ges Forschung | Verfahren zum Erzeugen einer Grabenisolation in einem Substrat |
US5899732A (en) * | 1997-04-11 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device |
US6033974A (en) * | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US5985742A (en) | 1997-05-12 | 1999-11-16 | Silicon Genesis Corporation | Controlled cleavage process and device for patterned films |
US20070122997A1 (en) | 1998-02-19 | 2007-05-31 | Silicon Genesis Corporation | Controlled process and resulting device |
US6548382B1 (en) * | 1997-07-18 | 2003-04-15 | Silicon Genesis Corporation | Gettering technique for wafers made using a controlled cleaving process |
AU5474299A (en) * | 1998-08-10 | 2000-03-06 | Memc Electronic Materials, Inc. | Process for preparation of silicon on insulator substrates with improved resistance to formation of metal precipitates |
JP2000323484A (ja) * | 1999-05-07 | 2000-11-24 | Mitsubishi Electric Corp | 半導体装置及び半導体記憶装置 |
US6500732B1 (en) | 1999-08-10 | 2002-12-31 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
EP1939932A1 (en) * | 1999-08-10 | 2008-07-02 | Silicon Genesis Corporation | A substrate comprising a stressed silicon germanium cleave layer |
US6263941B1 (en) | 1999-08-10 | 2001-07-24 | Silicon Genesis Corporation | Nozzle for cleaving substrates |
US6368938B1 (en) | 1999-10-05 | 2002-04-09 | Silicon Wafer Technologies, Inc. | Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate |
US6544862B1 (en) | 2000-01-14 | 2003-04-08 | Silicon Genesis Corporation | Particle distribution method and resulting structure for a layer transfer process |
TWI301907B (en) * | 2000-04-03 | 2008-10-11 | Semiconductor Energy Lab | Semiconductor device, liquid crystal display device and manfacturing method thereof |
US9177828B2 (en) | 2011-02-10 | 2015-11-03 | Micron Technology, Inc. | External gettering method and device |
US7045444B2 (en) * | 2000-12-19 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device that includes selectively adding a noble gas element |
US6858480B2 (en) * | 2001-01-18 | 2005-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
JP4712197B2 (ja) * | 2001-01-29 | 2011-06-29 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6444534B1 (en) * | 2001-01-30 | 2002-09-03 | Advanced Micro Devices, Inc. | SOI semiconductor device opening implantation gettering method |
JP2002231725A (ja) * | 2001-01-30 | 2002-08-16 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2002231627A (ja) * | 2001-01-30 | 2002-08-16 | Semiconductor Energy Lab Co Ltd | 光電変換装置の作製方法 |
JP4939690B2 (ja) * | 2001-01-30 | 2012-05-30 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6376336B1 (en) | 2001-02-01 | 2002-04-23 | Advanced Micro Devices, Inc. | Frontside SOI gettering with phosphorus doping |
US6670259B1 (en) * | 2001-02-21 | 2003-12-30 | Advanced Micro Devices, Inc. | Inert atom implantation method for SOI gettering |
JP4718700B2 (ja) * | 2001-03-16 | 2011-07-06 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6958264B1 (en) * | 2001-04-03 | 2005-10-25 | Advanced Micro Devices, Inc. | Scribe lane for gettering of contaminants on SOI wafers and gettering method |
JP2002343799A (ja) * | 2001-05-17 | 2002-11-29 | Nec Corp | Soi基板及び半導体装置の製造方法 |
US6534371B2 (en) | 2001-06-11 | 2003-03-18 | International Business Machines Corporation | C implants for improved SiGe bipolar yield |
JP2003045880A (ja) * | 2001-07-31 | 2003-02-14 | Mitsubishi Electric Corp | 半導体装置及び半導体装置の製造方法 |
US6635517B2 (en) | 2001-08-07 | 2003-10-21 | International Business Machines Corporation | Use of disposable spacer to introduce gettering in SOI layer |
US6617209B1 (en) * | 2002-02-22 | 2003-09-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US6506654B1 (en) * | 2002-03-26 | 2003-01-14 | Advanced Micro Devices, Inc. | Source-side stacking fault body-tie for partially-depleted SOI MOSFET hysteresis control |
JP4115158B2 (ja) * | 2002-04-24 | 2008-07-09 | シャープ株式会社 | 半導体装置およびその製造方法 |
US6890807B2 (en) * | 2003-05-06 | 2005-05-10 | Intel Corporation | Method for making a semiconductor device having a metal gate electrode |
US6806146B1 (en) | 2003-05-20 | 2004-10-19 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US6939815B2 (en) * | 2003-08-28 | 2005-09-06 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US7037845B2 (en) * | 2003-08-28 | 2006-05-02 | Intel Corporation | Selective etch process for making a semiconductor device having a high-k gate dielectric |
US7129182B2 (en) * | 2003-11-06 | 2006-10-31 | Intel Corporation | Method for etching a thin metal layer |
US6974764B2 (en) * | 2003-11-06 | 2005-12-13 | Intel Corporation | Method for making a semiconductor device having a metal gate electrode |
US7160767B2 (en) * | 2003-12-18 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US20050255677A1 (en) * | 2004-05-17 | 2005-11-17 | Weigold Jason W | Integrated circuit with impurity barrier |
KR100654354B1 (ko) * | 2005-07-25 | 2006-12-08 | 삼성전자주식회사 | 게더링 기능을 가지는 저결함 에피택셜 반도체 기판, 이를이용한 이미지 센서 및 이의 제조 방법 |
US7737004B2 (en) * | 2006-07-03 | 2010-06-15 | Semiconductor Components Industries Llc | Multilayer gettering structure for semiconductor device and method |
US7811900B2 (en) * | 2006-09-08 | 2010-10-12 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a thick layer transfer process |
US9362439B2 (en) | 2008-05-07 | 2016-06-07 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
US8293619B2 (en) | 2008-08-28 | 2012-10-23 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled propagation |
US8993410B2 (en) | 2006-09-08 | 2015-03-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
JP2008108915A (ja) * | 2006-10-25 | 2008-05-08 | Denso Corp | 半導体装置の製造方法 |
JP2010508676A (ja) * | 2006-11-02 | 2010-03-18 | アイメック | 半導体デバイス層からの不純物の除去 |
CN101681843B (zh) * | 2007-06-20 | 2012-05-09 | 株式会社半导体能源研究所 | 半导体装置的制造方法 |
US7795111B2 (en) * | 2007-06-27 | 2010-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate and manufacturing method of semiconductor device |
US7977798B2 (en) * | 2007-07-26 | 2011-07-12 | Infineon Technologies Ag | Integrated circuit having a semiconductor substrate with a barrier layer |
US8330126B2 (en) | 2008-08-25 | 2012-12-11 | Silicon Genesis Corporation | Race track configuration and method for wafering silicon solar substrates |
US8329557B2 (en) | 2009-05-13 | 2012-12-11 | Silicon Genesis Corporation | Techniques for forming thin films by implantation with reduced channeling |
US8017998B1 (en) * | 2009-09-08 | 2011-09-13 | T-Ram Semiconductor, Inc. | Gettering contaminants for integrated circuits formed on a silicon-on-insulator structure |
JP5568054B2 (ja) * | 2011-05-16 | 2014-08-06 | トヨタ自動車株式会社 | 半導体素子の製造方法 |
JP5520911B2 (ja) * | 2011-10-12 | 2014-06-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP5568580B2 (ja) * | 2012-02-22 | 2014-08-06 | 株式会社半導体エネルギー研究所 | 光電変換装置の作製方法 |
CN102637592A (zh) * | 2012-04-20 | 2012-08-15 | 中国科学院微电子研究所 | 一种半导体结构的制造方法 |
US9231020B2 (en) | 2014-01-16 | 2016-01-05 | Tower Semiconductor Ltd. | Device and method of gettering on silicon on insulator (SOI) substrate |
US10522388B1 (en) | 2018-08-24 | 2019-12-31 | Tower Semiconductor Ltd. | Method of forming high-voltage silicon-on-insulator device with diode connection to handle layer |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4249962A (en) * | 1979-09-11 | 1981-02-10 | Western Electric Company, Inc. | Method of removing contaminating impurities from device areas in a semiconductor wafer |
US5453153A (en) * | 1987-11-13 | 1995-09-26 | Kopin Corporation | Zone-melting recrystallization process |
JPH01181473A (ja) * | 1988-01-11 | 1989-07-19 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5194394A (en) * | 1989-10-23 | 1993-03-16 | Mitsubishi Denki Kabushiki Kaisha | Thyristor and method of manufacturing the same |
JPH04266047A (ja) * | 1991-02-20 | 1992-09-22 | Fujitsu Ltd | 埋め込み層形成に相当するsoi型半導体装置の製造方法及び半導体装置 |
JPH04286123A (ja) * | 1991-03-15 | 1992-10-12 | Fujitsu Ltd | 半導体装置の製造方法 |
US5244819A (en) * | 1991-10-22 | 1993-09-14 | Honeywell Inc. | Method to getter contamination in semiconductor devices |
US5372952A (en) * | 1992-04-03 | 1994-12-13 | National Semiconductor Corporation | Method for forming isolated semiconductor structures |
JP2773611B2 (ja) * | 1993-11-17 | 1998-07-09 | 株式会社デンソー | 絶縁物分離半導体装置 |
-
1996
- 1996-10-31 US US08/740,580 patent/US5753560A/en not_active Expired - Fee Related
-
1997
- 1997-09-20 TW TW086113689A patent/TW373235B/zh not_active IP Right Cessation
- 1997-10-08 JP JP9293562A patent/JPH10135226A/ja active Pending
- 1997-10-15 EP EP97117873A patent/EP0840367A3/en not_active Withdrawn
- 1997-10-31 KR KR1019970057049A patent/KR100326694B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH10135226A (ja) | 1998-05-22 |
KR100326694B1 (ko) | 2002-08-08 |
EP0840367A2 (en) | 1998-05-06 |
KR19980033385A (ko) | 1998-07-25 |
EP0840367A3 (en) | 1998-09-30 |
US5753560A (en) | 1998-05-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |