CN102637592A - 一种半导体结构的制造方法 - Google Patents

一种半导体结构的制造方法 Download PDF

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CN102637592A
CN102637592A CN2012101189399A CN201210118939A CN102637592A CN 102637592 A CN102637592 A CN 102637592A CN 2012101189399 A CN2012101189399 A CN 2012101189399A CN 201210118939 A CN201210118939 A CN 201210118939A CN 102637592 A CN102637592 A CN 102637592A
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layer
semiconductor structure
monocrystalline silicon
top layer
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毕津顺
罗家俊
韩郑生
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Institute of Microelectronics of CAS
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Priority to US14/395,444 priority patent/US20150170915A1/en
Priority to PCT/CN2012/081785 priority patent/WO2013155818A1/zh
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Abstract

本发明提供一种半导体结构的制造方法，其特征在于，包括以下步骤：提供用于形成半导体结构的SOI衬底，所述SOI衬底包括单晶硅顶层，氧化物埋层和支撑衬底；在所述单晶硅顶层中将要形成半导体结构的沟道区的区域之外的区域形成非晶区。本发明提供的方法能够有效提高在SOI衬底上形成的栅极介质层的可靠性。

Description

一种半导体结构的制造方法
技术领域
本发明涉及半导体的制造领域，尤其涉及一种半导体结构的制造方法。
背景技术
绝缘体上硅(Silicon-On-Insulator，SOI)技术是指在一层绝缘层(氧化物埋层，BOX)上的硅膜上制作器件和电路，它与普通的直接在半导体衬底上制造器件和电路的体硅技术的不同在于实现了器件之间完全的介质隔离。因此，SOI-CMOS集成电路从本质上避免了体硅CMOS电路的闩锁效应。另外，SOI器件的短沟道效应较小，能自然形成浅结，泄露电流较小，具有优良的亚阈值特性。无闩锁、高速度、低电源电压、低功耗、抗辐照和耐高温特色的SOI-CMOS集成电路具有非常广泛的应用前景。
但是，在硅晶体生长及后序制备过程中会产生的各种杂质，这些杂质会明显降低器件的栅极介质层可靠性。这些杂质可以被分为两类：(1)参与扩展晶格缺陷集结的杂质，例如：氧(O)、碳(C)；(2)因施杂作用而预先存在于扩展晶格缺陷中的杂质，例如：铜(Cu)、镍(Ni)、金(Au)、铁(Fe)等。金属性杂质有较高的流动性，在中等温度下便可以在晶格中扩展很长距离，因此这些杂质很有可能会流动到有扩展缺陷的地方，并被它们吸收。而这种杂质的扩展缺陷所具有的电活性可以引起漏电流的增大和击穿电压的降低，进而使器件退化。
通过吸杂的方法可以把缺陷中吸收的杂质移走，这样，剩余杂质中被施杂的可能性会明显的减少。吸杂的过程主要分为三步：(1)杂质释放出来并溶解在晶体中；(2)杂质在晶体中扩散；(3)杂质离开器件所在区域，被扩散缺陷(位错或沉积)吸收，防止其在后序热处理过程中再被释放到有源区。通常，过渡金属杂质能够均匀快速地分散到整个硅片中。在现有技术中，常用的吸杂方法有两个。
第一种方法是在硅片背面进行特殊处理以产生损伤或应力，然后由其来完成对金属杂质的吸收。采用研磨、刻槽或砂磨产生机械损伤的方式能够在硅片背面产生应力场，再经过退火过程，即会产生能释放这些应力的位错，继而使用位错的方式进行吸杂。但是，为了产生应力场而出现在这些硅片上的微疵点和位错会降低硅片的机械强度，使硅片在热处理中易产生翘曲。另外，硅片中产生的微粒很难再进行移动的，而且损伤程度也难以控制，一旦出现损失将很难弥补。
第二种方法是在硅片背面淀积厚度在1.2～1.5μm范围内的多晶硅层。由于多晶硅里含有大量的晶粒间界和晶格混乱，其可作为沉陷流动性杂质的点。但是，当该硅片经过1150度的氧化环境处理后，这种吸杂方法几乎完全失效。因为在高温处理下，晶粒间界大量减少，而且在晶粒的重整的同时，晶格的混乱得以修复。
此外，上述两种常用的吸杂方式并不适用于SOI结构。在SOI结构中，由于BOX的存在，使得顶层硅膜中的晶格缺陷集结的杂质和过渡金属杂质无法扩散到硅片背面的吸杂区域，从而在顶层硅膜中聚集，最终影响了器件栅极介质层的可靠性。目前需要一种能够在SOI结构中进行有效吸杂的方法。
发明内容
本发明提供一种半导体结构的制造方法，用于提高的问题。
根据本发明的一个方面，提供一种半导体结构的制造方法，其特征在于，包括以下步骤：
a)提供用于形成半导体结构的SOI衬底，所述SOI衬底包括单晶硅顶层，氧化物埋层和支撑衬底；
b)在所述单晶硅顶层中将要形成半导体结构的沟道区的区域之外的区域形成非晶区。
本发明提供的半导体结构的制造方法，通过在SOI衬底表面生成牺牲层之后，进行局部的Si离子注入，使得SOI衬底的顶层硅膜(即单晶硅顶层)中将要形成半导体结构的沟道区的区域之外的区域完全非晶化。但是由于氧化物埋层(BOX层)不能提供重结晶所需的晶体种子，因此在垂直方向不能够重结晶。在后续的高温的制程中，未被非晶化的将要形成半导体结构的沟道区的区域将作为重结晶所需要的晶体种子，使得周围的非晶区域沿水平方向部分形成单晶，避免了器件漏电。同时，水平方向的非晶区域也将起到明显的吸杂作用。该方法有效提高了之后形成的栅极介质层的可靠性。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图；
图2至图7是根据本发明的一个具体实施方式按照图1示出的流程制造半导体结构过程中该半导体结构各个制造阶段的剖视结构示意图；
图8为在SOI器件上使用和未使用本发明提供的方法以及体硅上的栅极介质层的击穿电压对比图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
请参考图1，图1是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图，该方法包括：
步骤S101，提供用于形成半导体结构的SOI衬底，所述SOI衬底包括单晶硅顶层，氧化物埋层和支撑衬底；
步骤S102，在单晶硅顶层中将要形成半导体结构的沟道区的区域之外的区域形成非晶区。
下面结合图2至图7对步骤S101至步骤S102进行说明，图2至图7是根据本发明的一个具体实施方式按照图1示出的流程制造半导体结构过程中该半导体结构各个制造阶段的剖视结构示意图。需要说明的是，本发明各个实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
执行步骤S101，提供用于形成半导体结构的SOI衬底，所述SOI衬底包括单晶硅顶层100，氧化物埋层110和支撑衬底130。
所述SOI衬底至少具有三层结构，分别是：支撑衬底130(图2中只示出部分所述支撑衬底130)、支撑衬底130之上的氧化物埋层110，以及覆盖在氧化物埋层110之上的单晶硅顶层100。其中，所述氧化物埋层110的材料通常选用SiO2，氧化物埋层110的厚度通常大于100nm；单晶硅顶层100的材料是单晶硅、Ge或III-V族化合物(如SiC、砷化镓、砷化铟或磷化铟等)，本具体实施方式中选用的单晶硅顶层100的厚度为10nm～10μm，例如：10nm，50nm或10μm。
接着，执行步骤S102，在单晶硅顶层100中将要形成半导体结构的沟道区的区域之外的区域形成非晶区。
首先，参考图2，在单晶硅顶层上形成牺牲层200。牺牲层200形成于单晶硅顶层100上，其厚度为20nm～200nm，例如：20nm，110nm或100nm。牺牲层200由氧化物材料制成。
接着，可选的，在牺牲层200上形成图形化的注入掩蔽层300，该注入掩蔽层300至少覆盖将要形成半导体结构的沟道区的区域。
在牺牲层200上形成注入掩蔽层300，所述注入掩蔽层300的材料可以是光刻胶、有机聚合物、氧化硅、氮化硅、硼硅玻璃、硼磷硅玻璃及其组合。所述注入掩蔽层300为光刻胶时，可以通过旋涂、喷胶的方法形成在所述牺牲层200上，并通过曝光、显影进行图形化。所述注入掩蔽层300为有机聚合物时，可以通过旋涂、升华的方法形成在所述牺牲层200上；而当所述注入掩蔽层300为氧化硅、氮化硅、硼硅玻璃、硼磷硅玻璃时，可以通过化学气相淀积、溅射等合适的方法形成在所述牺牲层200上，然后，再沉积光刻胶作为掩膜，通过干法刻蚀或湿法腐蚀进行图形化，如图3所示。
之后进行Si离子注入，在单晶硅顶层100中未被注入掩蔽层300覆盖的区域形成非晶区域。对SOI衬底的单晶硅顶层100进行Si离子注入。在本实施例中，Si离子的注入能量为50～300keV，注入剂量为1E15～5E15/cm2。采用Si离子注入可以精确地控制离子的注入深度。通过在单晶硅顶层100中进行Si离子注入，可以使Si注入区的单晶硅顶层100完全非晶化，形成非晶化区140，在沟道区存在金属杂质150，如图5所示。
进行Si离子注入之后，可以移除所述牺牲层200，如图6所示。图6还示出沟道区中的金属杂质150被非晶化区140吸收了。
进一步地，可以在单晶硅顶层100中形成隔离区(图中未示出)，用于将所述单晶硅顶层100分割为独立的区域，用于后续加工形成晶体管结构所用，隔离区的材料是绝缘材料，例如可以选用SiO2、Si3N4或其组合，隔离区的宽度可以视半导体结构的设计需求决定。
参考图7，之后可以在所述SOI衬底上形成栅极介质层400。所述栅极介质层400可以是热氧化层，包括氧化硅、氮氧化硅也可为高K介质，例如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON中的一种或其组合。栅极介质层400的厚度可以为1nm～20nm，例如1nm、5nm或20nm。可以采用热氧化、化学气相沉积(CVD)、原子层沉积(ALD)等工艺来形成栅极介质层400。在700℃～1000℃的温度下形成栅极介质层400，例如：700℃、890℃或1000℃。
下面以一个具体实施例对本发明的方法进行阐释。
提供一单晶硅顶层100厚度为100nm的SOI衬底，并在该衬底上形成厚度为150nm的牺牲层200。接下来在牺牲层200上形成注入掩蔽层300，并用栅光刻版曝光显影图形化。之后进行Si离子注入，注入剂量为5E15/cm2，能量为135～175keV。经Si离子注入后，Si离子注入区的单晶硅顶层100完全非晶化，形成非晶化区140。而单晶硅顶层100下部的氧化物埋层110不能提供重结晶所需要的晶体种子，因此在垂直方向不能够重结晶。随着温度的升高，沟道区将作为重结晶所需要的晶体种子，使得周围的非晶化区140沿水平方向部分形成单晶，避免了器件漏电。同时，水平方向的非晶化区140将起到明显的吸杂作用。进一步的，移除上述步骤形成的注入掩蔽层300和牺牲层200，在900℃的温度下在SOI衬底上形成厚度为10.5nm的栅极介质层400。
栅极介质层400的质量可以用击穿电压的统计来横量，击穿电压定义为电流密度为300mA/cm2时对应的栅电压。
采用本发明提供的方法，可以有效提高SOI衬底上栅极介质层的击穿电压，即提高所述栅极介质层的可靠性。如图8所示，无论是对于NMOS器件还是PMOS器件，未采用本发明提供的方法时，SOI衬底上的栅极介质层的击穿电压无论是NMOS还是PMOS的平均值都明显小于体硅技术，同时批次内和批次间的波动很大；而采用本发明提供的方法后，SOI衬底上栅极介质层的击穿电压无论是NMOS还是PMOS的平均值都得到了明显的提高，接近体硅技术，同时统计波动明显减少。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (10)

1.一种半导体结构的制造方法，包括：
a)提供用于形成半导体结构的SOI衬底，所述SOI衬底包括单晶硅顶层，氧化物埋层和支撑衬底；
b)在所述单晶硅顶层中将要形成半导体结构的沟道区的区域之外的区域形成非晶区。
2.根据权利要求1所述的方法，其中形成非晶区的步骤包括：
在所述单晶硅顶层上形成牺牲层(200)；
在所述牺牲层(200)上形成图形化的注入掩蔽层(300)，该注入掩蔽层(300)至少覆盖将要形成半导体结构的沟道区的区域；
进行Si离子注入，在所述单晶硅顶层中未被注入掩蔽层(300)覆盖的区域形成非晶区域。
3.根据权利要求2所述的方法，其特征在于，所述注入掩蔽层(300)的厚度为1μm～2μm。
4.根据权利要求2所述的方法，其特征在于，所述注入掩蔽层(300)的材料包括光刻胶、有机聚合物、氧化硅、氮化硅、硼硅玻璃、硼磷硅玻璃或其组合。
5.根据权利要求1所述的方法，其特征在于，还包括步骤：
在所述SOI衬底上形成栅极介质层(400)。
6.根据权利要求5所述的方法，其特征在于，所述栅极介质层(400)的厚度为1nm～20nm。
7.根据权利要求1所述的方法，其特征在于，所述单晶硅顶层的厚度为10nm-10μm。
8.根据权利要求1所述的方法，其特征在于，所述氧化物埋层的厚度为20nm～200nm。
9.根据权利要求2所述的方法，其特征在于，所述Si离子注入的能量为50～300keV。
10.根据权利要求2所述的方法，其特征在于，所述Si离子注入的剂量为1E15～5E15/cm2。
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