TW347591B - Process for producing field effect devices - Google Patents

Process for producing field effect devices

Info

Publication number
TW347591B
TW347591B TW085105964A TW85105964A TW347591B TW 347591 B TW347591 B TW 347591B TW 085105964 A TW085105964 A TW 085105964A TW 85105964 A TW85105964 A TW 85105964A TW 347591 B TW347591 B TW 347591B
Authority
TW
Taiwan
Prior art keywords
forming
field effect
trench
effect transistor
etching
Prior art date
Application number
TW085105964A
Other languages
Chinese (zh)
Inventor
Horng-Huei Tseng
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW085105964A priority Critical patent/TW347591B/en
Application granted granted Critical
Publication of TW347591B publication Critical patent/TW347591B/en

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A process for producing a field effect transistor, which comprises the following steps: forming an oxide layer required for isolating a field effect transistor on a silicon semiconductor wafer; forming a gate oxide layer of the field effect transistor; forming a polysilicon layer and a first dielectric layer, and etching off the first dielectric layer by using photolithography and etching techniques thereby forming a trench, the region of the trench being to be used as the gate of the field effect transistor; using the polysilicon layer and the first dielectric layer as the protective mask of ion implantation, and using an ion implantation technique for performing a channel doping which comprises forming a doping region only on the surface of the silicon semiconductor wafer in the trench; selectively growing a metal on the surface of the polysilicon layer in the trench; removing the first dielectric layer; using the metal as the etching protective mask, etching off the polysilicon layer thereby forming a recessed metal-polycide gate; and forming the source/drain.
TW085105964A 1996-05-20 1996-05-20 Process for producing field effect devices TW347591B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW085105964A TW347591B (en) 1996-05-20 1996-05-20 Process for producing field effect devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW085105964A TW347591B (en) 1996-05-20 1996-05-20 Process for producing field effect devices

Publications (1)

Publication Number Publication Date
TW347591B true TW347591B (en) 1998-12-11

Family

ID=58263993

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085105964A TW347591B (en) 1996-05-20 1996-05-20 Process for producing field effect devices

Country Status (1)

Country Link
TW (1) TW347591B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7157322B2 (en) 1999-02-09 2007-01-02 Nec Electronics Corporation Semiconductor device and method for manufacturing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7157322B2 (en) 1999-02-09 2007-01-02 Nec Electronics Corporation Semiconductor device and method for manufacturing same

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees