TW429485B - Metal oxide semiconductor field effect transistor with buried contact short channel recessed gate - Google Patents

Metal oxide semiconductor field effect transistor with buried contact short channel recessed gate

Info

Publication number
TW429485B
TW429485B TW88119239A TW88119239A TW429485B TW 429485 B TW429485 B TW 429485B TW 88119239 A TW88119239 A TW 88119239A TW 88119239 A TW88119239 A TW 88119239A TW 429485 B TW429485 B TW 429485B
Authority
TW
Taiwan
Prior art keywords
layer
gate
region
opening
implanted
Prior art date
Application number
TW88119239A
Other languages
Chinese (zh)
Inventor
Shie-Lin Wu
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW88119239A priority Critical patent/TW429485B/en
Application granted granted Critical
Publication of TW429485B publication Critical patent/TW429485B/en

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

The method of forming transistor can include the following procedures. Pad insulation-layer is formed and stacked layer is formed. The stacked layer is patterned to define the openings of gate insulation region and separation region. Gate insulation layer and field oxide separation region are formed. After that, stacked layer is removed. The first type ion is implanted to form lightly doped region and the pad layer is stripped. Silicon layer is formed on substrate. Part of the silicon layer is removed to define the first opening. Sidewall structure is formed inside the first opening. Sidewall structure is used as mask to remove part of gate insulation layer in order to form a gate opening. The second type ion is implanted to form tunneling-resist region. After that, the first dielectric layer is formed. Gate is then formed inside the gate opening. Part of the first dielectric layer that is not covered by gate is stripped. The third type ion is implanted to form junction region. The second insulation layer is formed. Thermal treatment is then performed. Finally, the metallization process of connecting conduction wire is performed so as to complete the fabrication of transistor.
TW88119239A 1999-11-04 1999-11-04 Metal oxide semiconductor field effect transistor with buried contact short channel recessed gate TW429485B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88119239A TW429485B (en) 1999-11-04 1999-11-04 Metal oxide semiconductor field effect transistor with buried contact short channel recessed gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88119239A TW429485B (en) 1999-11-04 1999-11-04 Metal oxide semiconductor field effect transistor with buried contact short channel recessed gate

Publications (1)

Publication Number Publication Date
TW429485B true TW429485B (en) 2001-04-11

Family

ID=21642892

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88119239A TW429485B (en) 1999-11-04 1999-11-04 Metal oxide semiconductor field effect transistor with buried contact short channel recessed gate

Country Status (1)

Country Link
TW (1) TW429485B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI404170B (en) * 2006-05-12 2013-08-01 Vishay Siliconix Power mosfet contact metallization

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI404170B (en) * 2006-05-12 2013-08-01 Vishay Siliconix Power mosfet contact metallization

Similar Documents

Publication Publication Date Title
KR940006702B1 (en) Manufacturing method of mosfet
US4443931A (en) Method of fabricating a semiconductor device with a base region having a deep portion
US5270232A (en) Process for fabricating field effect transistor
JPS62287670A (en) Manufacture of double diffusion metal oxide semiconductor transistor
TW332924B (en) Semiconductor
JPH06350090A (en) Manufacture of semiconductor device
KR0140719B1 (en) Favrication method of mosfet
KR100272051B1 (en) Process for manufacture of a p-channel mos gated device with base implant through the contact window
US5073506A (en) Method for making a self-aligned lateral bipolar SOI transistor
CN105118857A (en) Method for manufacturing trench type MOSFET (metal-oxide-semiconductor field-effect transistor)
KR950008257B1 (en) Mos fet and its making method
TW429485B (en) Metal oxide semiconductor field effect transistor with buried contact short channel recessed gate
CA1142270A (en) Self-alignment method of depositing semiconductor metallization
KR100320436B1 (en) Method for manufacturing mosfet
JPH0434942A (en) Manufacture of semiconductor device
JPS5575238A (en) Method of fabricating semiconductor device
JPH07273329A (en) Semiconductor device and its manufacture
JP3714396B2 (en) Manufacturing method of semiconductor device
KR940010568B1 (en) Mosfet and manufacturing method thereof
KR100947746B1 (en) Semiconductor device and method for fabricating the same
JPS63142866A (en) Manufacture of insulated gate field-effect transistor
KR100368971B1 (en) Gate of soi device and method for fabricating the same
KR100260366B1 (en) Method for fabricating semiconductor device
JPS59132677A (en) Manufacture of thin film transistor
KR100201775B1 (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent