JPS59132677A - Manufacture of thin film transistor - Google Patents

Manufacture of thin film transistor

Info

Publication number
JPS59132677A
JPS59132677A JP795183A JP795183A JPS59132677A JP S59132677 A JPS59132677 A JP S59132677A JP 795183 A JP795183 A JP 795183A JP 795183 A JP795183 A JP 795183A JP S59132677 A JPS59132677 A JP S59132677A
Authority
JP
Japan
Prior art keywords
film
wiring
polycrystalline
oxide film
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP795183A
Other languages
Japanese (ja)
Inventor
Toshihiko Mano
真野 敏彦
Hiroyuki Oshima
弘之 大島
Toshimoto Kodaira
小平 寿源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP795183A priority Critical patent/JPS59132677A/en
Publication of JPS59132677A publication Critical patent/JPS59132677A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the deterioration of gate withstand voltage by uniformly forming a gate insulation film and eliminate the possibility of disconnections of a wiring metal at the stepwise difference in a flat structure by covering an active element region with a selective oxide film. CONSTITUTION:A polycrystalline Si 302 is deposited on an insulation substrate 301, and then an oxide film 303 is formed by thermal oxidation. Next, after forming and processing the polycrystalline Si serving as a gate electrode 304, an oxide film 305 is formed by thermal oxidation. Then, an Si nitride film 306 is formed at the active element region, and processed, element isolation is performed by selectively oxidizing the polycrystalline 302 with the film as a mask, and then the Si nitride film 306 is removed. Thereafter, the source and drain regions 308 are formed by ion-implanting boron, etc. Finally, a contact hole for leading out the wiring is formed after depositing an NSG film serving as an interlayer insulation film 309, or a PSG film over the entire surface, and the wiring metal 310 such as Al is wiring-formed.

Description

【発明の詳細な説明】 本発明ば、多結晶シリコンを用いfC薄膜トランジスタ
(以下TPTと略す)に関するもので、特注の向上、製
造プロセスの安定化を図つ7ζものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an fC thin film transistor (hereinafter abbreviated as TPT) using polycrystalline silicon, and is a 7ζ device that aims to improve customization and stabilize the manufacturing process.

第1凶に従来の多結晶シリコン7川いたTFTを示す。The first culprit is the conventional polycrystalline silicon TFT.

ここで101は絶線基板、102は多結晶シリコン薄膜
、105μゲート絶縁膜、104汀ゲート電惨、105
μソース・ ドレイン拡散l曽、106μ虐間肥縁膜、
107が配線用金部である。
Here, 101 is a disconnected substrate, 102 is a polycrystalline silicon thin film, 105μ gate insulating film, 104 is a gate electric current, 105
μ source/drain diffusion, 106 μ source/drain diffusion,
107 is a metal part for wiring.

即ち、絶縁基板101に多結晶シリコンをテポ後ffr
定のパターンに形成加工する、し刀)る後にゲート杷縁
膜103’i、OVD法、あるいに熱酸化法により形成
する。ゲート成憧となる多結晶シリコン104を形成、
加工しり体、リン、ヒ素、ボロン等ケイオン注入するこ
とにより、ソース・ドレイン拡散層1057形成する。
That is, after depositing polycrystalline silicon on the insulating substrate 101, ffr
After forming and processing into a certain pattern, a gate edge film 103'i is formed by an OVD method or a thermal oxidation method. Forming polycrystalline silicon 104, which will become the gate.
A source/drain diffusion layer 1057 is formed by implanting silicon ions such as phosphorus, arsenic, and boron into the processed material.

、増111杷縁膜となるN2O族あるいにPE1G膜全
全曲にデボした後、配線引き出し用のコンタクトホール
ケ形成シ、最後KA[! 、 AN−Eli等の配線用
金鵬ケ配線形成する。
After debossing the entire N2O group or PE1G film, which will become the 111-layer film, contact holes for wiring are formed, and finally KA[! , Form a metal wire for wiring such as AN-Eli.

以上の製造方法により、第1図のTPTが形成される。By the above manufacturing method, the TPT shown in FIG. 1 is formed.

上述した従来の構造會肩するTPTによれば以下のよう
な欠点がある。即ち、ゲート絶縁膜を形成した時、多結
晶シリコン薄膜の側面の絶縁基板に近い部分のゲート絶
縁膜が博くなるために、ゲート耐圧の劣化がおこること
。筐り、素子の段差が大きいことから、配線用金属の断
線の恐れがあることである。以上の欠点全改善する構造
としては、第2図に示すように、能動素子領域を選択酸
化法により形成する方法がある。第2図で201は絶縁
基板、202は多結晶シリコン薄膜、203はゲート絶
縁膜、204はゲート電極、205は選択酸化膜、20
6はソース・ドレイン領域、207は層間絶縁膜、20
8は配線用金属である。
The conventional structural TPT described above has the following drawbacks. That is, when a gate insulating film is formed, the portion of the gate insulating film on the side surface of the polycrystalline silicon thin film close to the insulating substrate becomes wide, resulting in deterioration of gate breakdown voltage. Because of the large steps between the housing and the elements, there is a risk of the metal wiring breaking. As a structure that can overcome all of the above drawbacks, there is a method in which the active element region is formed by selective oxidation, as shown in FIG. In FIG. 2, 201 is an insulating substrate, 202 is a polycrystalline silicon thin film, 203 is a gate insulating film, 204 is a gate electrode, 205 is a selective oxide film, 20
6 is a source/drain region, 207 is an interlayer insulating film, 20
8 is a wiring metal.

第2図のように能動素子領域を選択酸化により形成して
やれば、上述した欠点は克服できる。
If the active element region is formed by selective oxidation as shown in FIG. 2, the above-mentioned drawbacks can be overcome.

本発明の目的とするところは上述した構造を提供できる
TPTの製造方法である。
The object of the present invention is a method of manufacturing TPT that can provide the above-described structure.

以下@5図に従って、不発明の実施例を工程断面図によ
って説明する。
Hereinafter, an embodiment of the invention will be described with reference to process cross-sectional diagrams according to Figure @5.

第5図(a)で、絶縁基板301に多結晶シリコン30
2&−デボし、表面を熱酸化することにより酸化膜50
5を形成する。この酸化膜はゲート絶縁膜を兼る。次に
ゲート電極となる多結晶シリコン504を形成加工しf
c後、熱酸化により該ゲート電極上に酸化膜305を形
成する。次に同図(b)のように、能動素子領域にシリ
コン窒化膜306ケ形成、加工する。
In FIG. 5(a), polycrystalline silicon 30 is placed on an insulating substrate 301.
2&- debo and thermally oxidize the surface to form an oxide film 50.
form 5. This oxide film also serves as a gate insulating film. Next, polycrystalline silicon 504 that will become the gate electrode is formed and processed.
After c, an oxide film 305 is formed on the gate electrode by thermal oxidation. Next, as shown in FIG. 4B, a silicon nitride film 306 is formed and processed in the active element region.

前記シリコン窒化膜をマスクとして、多結晶シリコンを
選択的に醸化することにより素子分離全行い、シリコン
家化膜全除去恢、リン、ヒ素、ポロン等ケイオン注入す
ることにより、ソース・ドレイン領域308を形成した
のが同図(c)である、最恢に1−聞納縁膜となるN8
G膜、あるいriPSG膜309全309デボした恢、
配線引き出し用のコンタクトホールを形成し、成・MS
i等の配線用金属を配線形成したのが同図(a)である
Using the silicon nitride film as a mask, polycrystalline silicon is selectively grown to completely isolate the elements, the silicon nitride film is completely removed, and silicon ions such as phosphorus, arsenic, and poron are implanted to form the source/drain regions 308. N8, which ultimately becomes the 1-Bonno lamina (see figure (c)), was formed.
G film, or riPSG film 309 with all 309 debossed,
A contact hole is formed for drawing out the wiring, and the formation/MS
The same figure (a) shows wiring formed by wiring metal such as i.

以上の製造方法によれば、能動素子領域が選択酸化膜で
おおわれている為、ゲート絶縁膜は均一に形成でき、従
ってゲート耐圧の劣化はない、また平坦化された構造に
なる為に、段差部での配線用金属の曲縁の恐れはない。
According to the above manufacturing method, since the active element region is covered with a selective oxide film, the gate insulating film can be formed uniformly, so there is no deterioration in gate breakdown voltage, and since the structure is flattened, there are no steps. There is no risk of curved edges of the wiring metal at the parts.

以上のようIc不発明j[、TPTの特性の向上及び、
製造プロセスの安定化を図った構造を提供する製造方法
である。
As described above, improvements in the characteristics of Ic and TPT, and
This is a manufacturing method that provides a structure that stabilizes the manufacturing process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来方法により製造された構造断面図であり、
第2図が不発明による製造された構造断面図である。 第3図は本発明による製造方法を示す工程断面図である
。 301・・・絶縁基板  302・・・多結晶シリコン
303・・・酸化膜(ゲート絶縁膜を乗る)304・・
・ゲート電極    305・・・熱酸化膜506・・
・シリコン窒化膜  307・・・選択酸化膜308・
・・ソース・ドレイン領域 309・・・層間絶縁膜    310・・・配線用金
属以   上 出願人 株式会社諏訪稍工舎 代理人 弁理士 最 上  務  5− 翼 第2図 第3図 −391−
FIG. 1 is a cross-sectional view of a structure manufactured by a conventional method.
FIG. 2 is a cross-sectional view of a structure manufactured according to the invention. FIG. 3 is a process sectional view showing the manufacturing method according to the present invention. 301...Insulating substrate 302...Polycrystalline silicon 303...Oxide film (covering gate insulating film) 304...
・Gate electrode 305...thermal oxide film 506...
・Silicon nitride film 307...Selective oxide film 308・
...Source/drain region 309...Interlayer insulating film 310...Metal for wiring and above Applicant Suwa Kenkosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami 5- Wing Figure 2 Figure 3-391-

Claims (1)

【特許請求の範囲】[Claims] 半導体母材となる多結晶シリコンを選択酸化により素子
分離する薄膜トランジスタに於いて、ゲート電極である
多結晶シリコンの表面に酸化膜勿形収する工程と、シリ
コン窒化膜全能@領域のパターンに形成加工する工程と
、前記シリコン屋化膜オマスクとして選択戚化七行う工
程とを含むことを%徴とする薄膜トランジスタの製造方
法、
In thin film transistors in which elements are separated by selective oxidation of polycrystalline silicon, which is the semiconductor base material, there is a process of forming an oxide film on the surface of polycrystalline silicon, which is the gate electrode, and a process of forming a silicon nitride film into a pattern of omnipotent @ region. A method for manufacturing a thin film transistor, the method comprising: a step of performing selective oxidation as the silicon film mask;
JP795183A 1983-01-20 1983-01-20 Manufacture of thin film transistor Pending JPS59132677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP795183A JPS59132677A (en) 1983-01-20 1983-01-20 Manufacture of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP795183A JPS59132677A (en) 1983-01-20 1983-01-20 Manufacture of thin film transistor

Publications (1)

Publication Number Publication Date
JPS59132677A true JPS59132677A (en) 1984-07-30

Family

ID=11679796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP795183A Pending JPS59132677A (en) 1983-01-20 1983-01-20 Manufacture of thin film transistor

Country Status (1)

Country Link
JP (1) JPS59132677A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425179A (en) * 1990-05-21 1992-01-28 Seiko Instr Inc Semiconductor device
WO1997048136A1 (en) * 1996-06-14 1997-12-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having soi structure and method for manufacturing the device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128023A (en) * 1981-01-30 1982-08-09 Nec Corp Manufacture of semiconductor device
JPS57208124A (en) * 1981-06-18 1982-12-21 Fujitsu Ltd Manufacture of semiconductor device
JPS5895814A (en) * 1981-11-30 1983-06-07 Mitsubishi Electric Corp Preparation of semiconductor device
JPS58192381A (en) * 1982-05-06 1983-11-09 Mitsubishi Electric Corp Manufacture of mos field effect transistor
JPS59108360A (en) * 1982-12-14 1984-06-22 Mitsubishi Electric Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128023A (en) * 1981-01-30 1982-08-09 Nec Corp Manufacture of semiconductor device
JPS57208124A (en) * 1981-06-18 1982-12-21 Fujitsu Ltd Manufacture of semiconductor device
JPS5895814A (en) * 1981-11-30 1983-06-07 Mitsubishi Electric Corp Preparation of semiconductor device
JPS58192381A (en) * 1982-05-06 1983-11-09 Mitsubishi Electric Corp Manufacture of mos field effect transistor
JPS59108360A (en) * 1982-12-14 1984-06-22 Mitsubishi Electric Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425179A (en) * 1990-05-21 1992-01-28 Seiko Instr Inc Semiconductor device
WO1997048136A1 (en) * 1996-06-14 1997-12-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having soi structure and method for manufacturing the device
US6225663B1 (en) 1996-06-14 2001-05-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having SOI structure and method of fabricating the same
US6509211B2 (en) 1996-06-14 2003-01-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having SOI structure and method of fabricating the same

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