AU5474299A - Process for preparation of silicon on insulator substrates with improved resistance to formation of metal precipitates - Google Patents

Process for preparation of silicon on insulator substrates with improved resistance to formation of metal precipitates

Info

Publication number
AU5474299A
AU5474299A AU54742/99A AU5474299A AU5474299A AU 5474299 A AU5474299 A AU 5474299A AU 54742/99 A AU54742/99 A AU 54742/99A AU 5474299 A AU5474299 A AU 5474299A AU 5474299 A AU5474299 A AU 5474299A
Authority
AU
Australia
Prior art keywords
silicon
formation
preparation
improved resistance
metal precipitates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU54742/99A
Inventor
Robert A. Craven
Robert J. Falster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SunEdison Inc
Original Assignee
SunEdison Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SunEdison Inc filed Critical SunEdison Inc
Publication of AU5474299A publication Critical patent/AU5474299A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
AU54742/99A 1998-08-10 1999-08-10 Process for preparation of silicon on insulator substrates with improved resistance to formation of metal precipitates Abandoned AU5474299A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9587898P 1998-08-10 1998-08-10
US60095878 1998-08-10
PCT/US1999/018085 WO2000010195A2 (en) 1998-08-10 1999-08-10 Preparation of metal-precipitates permeable insulator for soi substrate

Publications (1)

Publication Number Publication Date
AU5474299A true AU5474299A (en) 2000-03-06

Family

ID=22254002

Family Applications (1)

Application Number Title Priority Date Filing Date
AU54742/99A Abandoned AU5474299A (en) 1998-08-10 1999-08-10 Process for preparation of silicon on insulator substrates with improved resistance to formation of metal precipitates

Country Status (2)

Country Link
AU (1) AU5474299A (en)
WO (1) WO2000010195A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7987716B2 (en) * 2008-03-26 2011-08-02 Endevco Corporation Coupled pivoted acceleration sensors

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860697A (en) * 1981-09-30 1983-04-11 Nec Corp Forming method of silicon single crystal film
JPS60144949A (en) * 1984-01-06 1985-07-31 Nec Corp Manufacture of semiconductor device
JPH02237121A (en) * 1989-03-10 1990-09-19 Fujitsu Ltd Manufacture of semiconductor device
JPH05129309A (en) * 1991-10-31 1993-05-25 Nec Corp Pasted substrate
US5840590A (en) * 1993-12-01 1998-11-24 Sandia Corporation Impurity gettering in silicon using cavities formed by helium implantation and annealing
US5498898A (en) * 1993-12-28 1996-03-12 Nippon Steel Corporation Semiconductor device using element isolation by field shield
US5757063A (en) * 1994-03-25 1998-05-26 Kabushiki Kaisha Toshiba Semiconductor device having an extrinsic gettering film
JP2755185B2 (en) * 1994-11-07 1998-05-20 日本電気株式会社 SOI substrate
JP2874618B2 (en) * 1995-11-22 1999-03-24 日本電気株式会社 Silicon semiconductor substrate and method of manufacturing the same
US5753560A (en) * 1996-10-31 1998-05-19 Motorola, Inc. Method for fabricating a semiconductor device using lateral gettering
JPH1126735A (en) * 1997-07-04 1999-01-29 Texas Instr Japan Ltd Bonded soi wafer

Also Published As

Publication number Publication date
WO2000010195A2 (en) 2000-02-24
WO2000010195A3 (en) 2000-05-18

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase