TW367501B - Synchronous semiconductor memory device - Google Patents

Synchronous semiconductor memory device

Info

Publication number
TW367501B
TW367501B TW086106708A TW86106708A TW367501B TW 367501 B TW367501 B TW 367501B TW 086106708 A TW086106708 A TW 086106708A TW 86106708 A TW86106708 A TW 86106708A TW 367501 B TW367501 B TW 367501B
Authority
TW
Taiwan
Prior art keywords
clock signal
internal clock
status
pulse span
memory device
Prior art date
Application number
TW086106708A
Other languages
English (en)
Inventor
Seiji Sawada
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW367501B publication Critical patent/TW367501B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
TW086106708A 1997-02-18 1997-05-20 Synchronous semiconductor memory device TW367501B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9033836A JPH10228772A (ja) 1997-02-18 1997-02-18 同期型半導体記憶装置

Publications (1)

Publication Number Publication Date
TW367501B true TW367501B (en) 1999-08-21

Family

ID=12397583

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086106708A TW367501B (en) 1997-02-18 1997-05-20 Synchronous semiconductor memory device

Country Status (6)

Country Link
US (1) US5808961A (zh)
JP (1) JPH10228772A (zh)
KR (1) KR100254071B1 (zh)
CN (1) CN1135566C (zh)
DE (1) DE19738963C2 (zh)
TW (1) TW367501B (zh)

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KR100230407B1 (ko) * 1997-02-17 1999-11-15 윤종용 반도체장치의 클럭 발생회로 및 클럭발생방법
KR100301036B1 (ko) * 1997-06-26 2001-09-03 윤종용 데이터입출력마스크입력버퍼의전류소모를감소시키기위한제어부를구비하는동기식반도체메모리장치
US6215725B1 (en) * 1997-07-23 2001-04-10 Sharp Kabushiki Kaisha Clock-synchronized memory
JP3152174B2 (ja) * 1997-07-29 2001-04-03 日本電気株式会社 半導体記憶装置
KR100274602B1 (ko) * 1997-11-20 2000-12-15 윤종용 동기형 메모리 장치
US6078547A (en) * 1998-05-12 2000-06-20 Mosys, Inc. Method and structure for controlling operation of a DRAM array
JP3178423B2 (ja) * 1998-07-03 2001-06-18 日本電気株式会社 バーチャルチャネルｓｄｒａｍ
JP3087734B2 (ja) 1998-10-09 2000-09-11 日本電気株式会社 クロック信号生成回路
JP4034886B2 (ja) * 1998-10-13 2008-01-16 富士通株式会社 半導体装置
JP3266127B2 (ja) * 1999-01-25 2002-03-18 日本電気株式会社 同期式半導体記憶装置
KR100304705B1 (ko) * 1999-03-03 2001-10-29 윤종용 포스티드 카스 레이턴시 기능을 가지는 동기식 반도체 메모리 장치 및 카스 레이턴시 제어 방법
US6195309B1 (en) * 1999-05-26 2001-02-27 Vanguard International Semiconductor Corp. Timing circuit for a burst-mode address counter
KR100311974B1 (ko) * 1999-06-15 2001-11-02 윤종용 동기타입 반도체 메모리 디바이스용 내부클럭 발생회로 및 내부클럭 발생방법
JP3703655B2 (ja) * 1999-08-11 2005-10-05 株式会社東芝 タイミング信号発生回路
JP3558564B2 (ja) * 1999-10-21 2004-08-25 株式会社 沖マイクロデザイン データ転送回路及びデータ転送回路を搭載するマイクロコンピュータ
JP3535788B2 (ja) * 1999-12-27 2004-06-07 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
KR100374637B1 (ko) * 2000-10-24 2003-03-04 삼성전자주식회사 Ｊｅｄｅｃ 규격의 포스티드 카스 기능을 가지는 동기식반도체 메모리 장치
US6529425B2 (en) * 2000-11-13 2003-03-04 Kabushiki Kaisha Toshiba Write prohibiting control circuit for a semiconductor device
JP4712183B2 (ja) * 2000-11-30 2011-06-29 富士通セミコンダクター株式会社 同期型半導体装置、及び試験システム
KR100400770B1 (ko) * 2000-12-30 2003-10-08 주식회사 하이닉스반도체 데이터 출력회로
JP4263374B2 (ja) * 2001-01-22 2009-05-13 株式会社ルネサステクノロジ 半導体集積回路
KR100445062B1 (ko) * 2001-11-02 2004-08-21 주식회사 하이닉스반도체 반도체메모리장치의 클럭발생회로
KR100476892B1 (ko) * 2002-04-29 2005-03-17 삼성전자주식회사 데이터의 부정조작을 방지하는 방법 및 그것을 이용한데이터 처리 시스템
KR100475054B1 (ko) * 2002-05-09 2005-03-10 삼성전자주식회사 비트 구성에 상관없이 데이터 출력시간이 일정한 동기식반도체 장치 및 데이터 출력시간 조절 방법
JP3800164B2 (ja) * 2002-10-18 2006-07-26 ソニー株式会社 情報処理装置、情報記憶装置、情報処理方法、及び情報処理プログラム
KR100500411B1 (ko) * 2003-06-18 2005-07-12 주식회사 하이닉스반도체 내부 클럭 신호 생성 회로 및 방법
KR100546215B1 (ko) * 2003-12-05 2006-01-24 주식회사 하이닉스반도체 펄스 폭 제어 회로
KR100567532B1 (ko) * 2003-12-10 2006-04-03 주식회사 하이닉스반도체 펄스 폭 제어 회로 및 그 방법
US7250800B2 (en) 2005-07-12 2007-07-31 Hewlett-Packard Development Company, L.P. Clock pulse width control circuit
KR100753036B1 (ko) * 2005-09-29 2007-08-30 주식회사 하이닉스반도체 펄스 제어 장치
JP4267006B2 (ja) * 2006-07-24 2009-05-27 エルピーダメモリ株式会社 半導体記憶装置
KR100845135B1 (ko) * 2006-12-22 2008-07-09 삼성전자주식회사 불휘발성 메모리 장치에서의 프로그램 방법 및 이를 위한불휘발성 메모리 장치
JP2012108979A (ja) 2010-11-17 2012-06-07 Elpida Memory Inc 半導体装置
JP2012203970A (ja) * 2011-03-28 2012-10-22 Elpida Memory Inc 半導体装置及び半導体装置の制御方法
KR101997226B1 (ko) * 2013-05-29 2019-07-08 에스케이하이닉스 주식회사 반도체장치
US9036434B1 (en) * 2013-10-31 2015-05-19 Nanya Technology Corporation Random access memory and method of adjusting read timing thereof
CN112054783A (zh) * 2019-06-06 2020-12-08 中国科学院苏州纳米技术与纳米仿生研究所 触发器及具有扫描端的触发器

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Publication number Priority date Publication date Assignee Title
US5120987A (en) * 1991-01-31 1992-06-09 Wong Robert C Tunable timer for memory arrays
JPH07201175A (ja) * 1993-12-28 1995-08-04 Hitachi Ltd 半導体装置
GB9417244D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Integrated circuit device and test method therefor
JP3591887B2 (ja) * 1994-09-12 2004-11-24 富士通株式会社 半導体記憶装置
JP2697634B2 (ja) * 1994-09-30 1998-01-14 日本電気株式会社 同期型半導体記憶装置
JPH08180677A (ja) * 1994-12-26 1996-07-12 Hitachi Ltd 半導体装置
US5666321A (en) * 1995-09-01 1997-09-09 Micron Technology, Inc. Synchronous DRAM memory with asynchronous column decode
US5666324A (en) * 1996-03-15 1997-09-09 Mitsubishi Denki Kabushiki Kaisha Clock synchronous semiconductor memory device having current consumption reduced

Also Published As

Publication number Publication date
CN1191371A (zh) 1998-08-26
DE19738963A1 (de) 1998-08-27
US5808961A (en) 1998-09-15
DE19738963C2 (de) 2003-10-23
CN1135566C (zh) 2004-01-21
KR19980069829A (ko) 1998-10-26
JPH10228772A (ja) 1998-08-25
KR100254071B1 (ko) 2000-04-15

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