TW317648B - - Google Patents

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TW317648B
TW317648B TW085115749A TW85115749A TW317648B TW 317648 B TW317648 B TW 317648B TW 085115749 A TW085115749 A TW 085115749A TW 85115749 A TW85115749 A TW 85115749A TW 317648 B TW317648 B TW 317648B
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

317648 A7 B7 經濟部中央揉準局貝工消費合作社印製 五、發明説明（1 ) 本發明係有關於一種半導體裝置，包括：具有鄰表面之p 型表面範圍的矽半導體主體，並提供具有絕緣閘極和η型 源極及汲極區域（在表面範困内）之η型通道場效電晶禮，並 利用鄰表面之通道範圍將源極及汲極區域隔開，在距雜表 面下一小距離處提供一埋藏式ρ型摻雜區域，其掺雜濃度 大於通道範圍，該裝置如美國專利1^-八5，166,765號案所 知〇 在通道内之電荷載子之移動率（以"表示之，單位爲(；1112 /伏特（V))，在其通道尺寸爲深次微米範圍（例如，〇丨微 米）之MOS電晶體而言’爲一重要參數，影響電晶體之電 容和傳導電流’移動率大大地視在通道内之電場之値而定 ，至少視橫向傳到表面之電場之分力而定，通常，移動率 随場加強而減少，因此在通道内之摻雜濃度應非常低，以 得到高的移動率，例如摻雜濃度約爲1 〇 1 5原子/ c m 3 (本質 梦）。對於如此低的摻雜階是不可能的，因爲以該摻雜，在 非常低汲極電壓·，會發生電荷穿透到源極，除此，低通道 捧雜階並結合非常小尺寸（例如：通道表面區域爲〇·1微米 X 0.1微米）時，將引起閥電壓之主要擾動，由於在摻雜暗 態的擾動，而特別不適合在較低階提供電壓，這些問題的 解決’如美國第5,166,765專利案所述，在所知的電晶II内 ，其通道範圍包括··鄰表面之本質表面範圍，其厚度約爲 數十分之一奈米（nm)’並鄰具有高濃度硼離子之ρ型層， 例如濃度約爲1 0 1 8 /立方公分，利用該方法所製造的電晶. 體具有電荷載子高移動率，高穿透電壓，和好的閥電壓， -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公着) (請先W讀背面之注意事項再填寫本寊 -裝- >tr 線 經濟部中央標準局貝工消費合作社印«. 317648 A7 ________B7 五、發明説明（2 ) 對極小的尺寸而言，再以該方法生產，則很難製造出如此 的電晶體。此外’利用光罩遮住通道範圍内之本質梦，對 電晶體之通道範圍分開植入砷離子和硼離子是需要的。無 論如何，利用在通道内植入砷，對於電荷載子移動和製程 控制是無利的，例如考慮閥電壓V τ。 本發明之主要目的在於提供一種裝置，該裝置利用開放 圖示描述，並以可依和重復製造之方法製造之，本發明之 目的係在於提供一種裝置，其中，並不需要各別將砷植入 -本質-通道範圍内，借由植入雜質，在通道内之移動率並 無不利的效應產生。 依照本發明，以開放圖示描述之半導體裝置，其特徵在 其表面範圍内，通道範圍下，増加一埋藏式層（ 稱之SiGe層）’ X爲Ge之莫耳分數，在鄰表面之較弱摻雜 通道範園和較強摻雜埋藏式p型區域之間形成擴散阻隔。 本發明係基於解決埋藏式p型區域之淺深度，而造成硼原· 子擴教到表面之問題，特別是在成長閘氧化物期間而引起 在晶格内之空位’會増強硼原子之擴散。本發明利用 層減少其擴散加速率，其SiGe層厚度小於晶格距離，其方 向至少平行表面，等於或至少實質等於矽晶體中之晶格常 數。在SiGe層上經本質矽長晶有可能形成一通道範_，下 一步驟可能形成閘氧化物，期間利用S i G e層使硼原子擴散 減速® 値得注意的是，製造以下之SiGe層，必需瞭解包括所有-層，其S i被G e取代數個晶體之晶格點，除了 G e，亦可能 -5- 木紙張尺度適用中國困家標牟（CNS ) A4%格（210X297公釐） ----------&------1T------^ »- (請先閲讀背面之注意Ϋ項再填寫本頁) 317648 Μ濟部中央標準局貝工消費合作社印装 A7 B7 五、發明説明（） 包含其它基板，例如碳，只要該層爲導電性，擴散一阻隔 ’和單晶，則本質碎·層長成在該層上。利用植入G e到梦晶 内而形成SiGe層，當Ge之含量愈大時，會引起晶體内之 破壞，例如X約爲0.3時。依照本發明之主要實施例半導鱧 裝置’其中S i G e層的成份具有寬的限制，此外可利用長晶 層形成SiGe層和鄰表面之通道範園》 傳統利用長成厚場氧化物之分離技術，可在半導體主禮 内形成活動區域邊界’由於熱處理爲長時間，較不希望在 提供SiGe層和本質層之後做，最好是先提供場氧化物，之 後再利用選擇性長晶在活動範圍内沉積S i G e層和本質層。 一實施例係由於形成邊界並不需要長時間的高溫步驟，因 此可在沉積SiGe層之後再提供邊界，該邊界之特徵係在半 導體主體内經製造凹槽而形成其邊界，凹槽内可以或不填 充材料，由凹槽之表面到半導鳢主體内部之深度比其源極 和汲極區域還深。 本發明亦可利用在不含η通道場效電晶體之積體電路，積 體電路之重要種類包括：互補式場效電晶趙（CMOS)具有ρ 通道電晶·趙和η通道電晶體，一合併本發明關點之半導體 裝置’其特徵在鄰半導體主體表面之η型表面範園的區域 ’提供一具有絕緣閘極之ρ通道場效電晶體和在η型表面範 圍内提供ρ型源極和汲極區域，並利用通道範園將源極和 没極分開，在η型表面範圍之通道範圍下提供一埋藏式η型 區域’該區域植入As或Sb雜質，其植入濃度比鄰表面之通-道範圍和埋藏式Sii_xGex層之植入濃度高。本發明之關點 -6- 不紙度適用中國國家標準（CNS )八4規格（2丨〇;<297公釐） ----------1-- • (請先閲讀背面之注意事項再填寫本頁) .π 線 317648 A7 B7 4 五、發明説明（ 係期望在p通道電晶體，在表面數十分之一奈米（nm)之距 離下提供一強摻雜n型層，對n通道電晶體而言亦有類似的 原因，無論如何，對n型雜質而言SiGe層無法形成擴散陣 礙，因此，當使用P時，在通道範圍内將形成強摻雜之埋 藏層，具有B的擴散常數。利用選擇11型摻雜物As或Sb， 則其As原子或Sb原子之擴散在SiGe層和所上所述之本質 通道範圍之間的孝界上停止，因此通道範圍之表面仍然維 持本質。 參考以下實施例，將更詳細的説明本發明，圖示説明如 下： 圖1係爲本發明之半導體裝置橫截面示意圖。 圖2至圖6係爲製造裝置之步驟橫截面示意圖a. 圖7至圖11係爲本發明第二個實施例之製造半導禮裝置 之步驟橫截面示意囷。 圖12至圖14係爲本發明第三個實施例之製造半導趙裝置. 之步驟橫截面示意圖。 値得注意的是圖中所示的尺寸均不是眞實的尺寸，並且 ’在圖中垂直方向放大的程度比其它方向放大的程度大。 如圖1所示之半導體裝置爲一獨立的電晶體，在半導體裝 置上，沒有更進一步的提供活動電路單元，本發明對於非 常小尺寸的電晶體是很重要的，特別是在深次微米範圍内 ’如圖1所示的裝置將成爲一具有大量電路單元之積禮電 路的一部份。該裝置包括：一具有p型面範圍3和鄰面2之 故半導體主體1，該半導體主體1具有雜質植入，遍及具有 7 用中國國家標準（CNS ) A4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) •11 經濟部中央棣丰局貝工消費合“ 經濟部中央樣準局負工消费合作社印装 五、發明説明（ 雜質濃度的面範圍3之整個均勻厚度上3在另一個實施例 中如囷1所不，在具較強植入p型雜質的基板4上形成一 較弱雜資植入疋膜層以形成p型區域，提供半導趙主禮― 絕緣-閘極n通道場效電晶禮或MOST，該電晶體包括兩個 王要電極區域5和6,該電極區域形成在⑼表面區域内， 7區域形成電晶禮的源極和没極，利用—介於其間之通道 範圍7，其連接表面2，而將區域5和6分開，且其長度爲深 次微米範園内，例如018微米。通道區域的表面被閉極介 电層所覆蓋（例如：厚爲4 nm之氧化層8)，並將通道區域 與閘電極9隔開。比起其它區域或範圍而言，摻雜在範圍7 之雜質濃度是非常低的，如此，通道範圍7在後續將被認 爲成本彦發區域β面範圍3内提供一埋藏式p型區域1〇，以 非4小的距離位在通道範園下，即：從面2算起，僅數 十nm的距離，埋藏式區域之雜質摻雜濃度較高，至少比通 道範圍7超過數個數量級，使得在運作期間，可視區域1〇 爲一等位平面或接地平面。 依照本發明，面範圍3亦包括其Si原子部份被Ge原子取 代的埋藏式膜層"，該膜層以SiixGex表示卜爲（)6之莫 耳分數），亦簡化成SiGe ’除了在Si晶格内加入Ge外，亦 可以加在其它原素内例如碳（c) ’來自強摻雜層1〇乏硼择 散經由SiGe層11之阻隔而禁止進到本質範圍7,由此，並 不需要植入砷（As)到範圍7，即可維持表面電子之高移動 率’ SiGe層的厚度約爲20nm，其中Ge之X約爲0.3，對於-膜層11之厚度仍可滿足成爲擴散障礙層，在以（^層11内 -8- 本纸張尺度適用中國國家搮準（CNS ) A4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 線 • n· n n^— In . A7 B7 6 五、發明説明（ 之晶格距離，在平行面2之方向其等於或小於Si。此即説 明利用簡單的長晶控制即可提供本質範圍7。 從由2延伸的源極和汲極區域5，6將強摻雜區域1〇埋入 弱掺雜面範圍3内’而使得該區域相鄭之寄生電容較低， 利用區域5和6提供之延申12，13(其厚度小於區域5和6) 部份，在閘電極9和源極和汲極之間得到一控制重吞。 在本實施例内之半導體主體内的活動範園之側邊界包括 •一深入半導趙主趙，比源極和没極區域更深的凹槽14， 其内充入氧化物或其它適當的材料或復合材料，在形成 ’ 11，7等結構後，再形成凹橫14，並且該凹槽之形成不 經高溫步驟以免干擾到膜層結構。 圖2到圖4係爲製造如圖1之電晶體的數個步驟示意圖， 其中’面範園3係爲一在方向爲（1〇〇)之強摻雜p型基板上 之弱掺雜p型長晶層，其摻雜原子濃度爲1〇17原子/立方 公分，厚度約爲1至3微米之間，沉積sii、〇^層η，χ約 爲0.3 ’厚度約爲2〇 ηιη，該膜層11爲本質層，即ρ型或η型 接雜濃度儘可能的低，而後在SiGe層11上提供一本質梦 層7 ’以形成通道範圍，該裝置之製程步驟説明如囷2所示 ’在下一步驟，定義活動範圍，利用蝕刻光軍15復蓋在面 (囷3)上’以非等向性蝕刻形成凹槽14，凹槽Η特初的寬 度，例如0.25微米，在凹槽内填入氧化物以得到實物之平 面’拿掉光罩15後，植入硼離子以形成埋藏層1〇，其濃度 爲1〇13原子/平方公分，植入能量爲25 keV(如圖4 )，因-此’可植入雜質濃度約爲10!8硼原子/立方公分以得到強 •9 — H II I I I —裝— II I I I 訂— I I I I I 線 (讀先Μ讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 5 」 ί ΙΓ IT,1 * 公 7 9 2 B7 五、發明説明（） 摻雜P型層，經由快速熱退火（RTA)以消除晶格破壞，例 如加熱到950 C持續2 5秒，經熱氧化過程（例如85〇 eC )以形 成閘極氧化層8，其厚度約爲4 nm，如圖4所示。 經濟部中夬揉準局負工消費合作社印製 在上述RTA步骤和氧化步骤期間，在埋藏層1〇内之硼傾 向擴散到表面，但無論如何，經由SiGe層可有效阻隔硼擴 散，因此在通道範圍内之8濃度仍然很低，通道範圍仍被 涊定爲本質區域，亦無As植入，經由硼擴散siGe層可能 變成弱P型摻雜，在下一步驟，如圖5所示，沉積一複晶矽 或非晶矽層，厚度約爲〇·2微米，並制圖以得到閘電極9， 閘電極之長度，例如〇·職米，植人圖號係以箭號16表示 之，以形成砷摻雜範園17,加熱後產生源極/汲極延伸部 分12和13，該植入濃度，例如：1〇u原予/平方公分， 植入能量约爲IGkeV’得到該區域之深度，並以此能量植 入’與閘極9有很小的重吞處，該有效通道長度係與開電 極長度比較而言，在植入雜質時閘電極9亦可能同時被植 入雜質’在閘電極9兩旁形成側壁子18(如圖6)，側壁子18 的形成係，經由先沉積氧切或氮切層，再進行非等向性 蝕刻’然後，再一次植入砷離子以得到一具有侧壁子以之 深源極和没極區域5和6，其植人能量，例如爲MM，植 入漢度爲4X 1()15原子/平方公分，在此步驟同時，亦有 可邊植人以極9,而後做线理步驟，以消除在做砰離 子植入時所引起的晶趙破壞，最好再做一次rta As的㈣。 限制 在下—個步驟中將提供接觸，_如形成夺化物接觸19，' -10- 本紙铁尺度it财) A4mr ""(2丨OX297公釐了 經濟部中央搮準局負工消費合作社印製 317648 A7 五、發明説明（8 ) — —— 再沉積厚30腿的Ti層，之後，將裝置放入氮氣中做熱處 理，石夕化物（厚度約爲50nm，局部KTasi接觸，選擇 性的拿掉局部的氮化鈦，而得到如囷丨所示之裝置。 囷11係依照本發明之cM〇ST橫截面*意圖，該裝置基本 包括η通道電晶體Tl和一互補電晶體丁2，即p通道電晶體 ，電晶髏T i之建構係相當符合本實施例和依照所给的一些 參考値所製造的電晶體，該電晶體包括：一本質通道範圍 7,同之前所述的例子，通道範圍7經由“(^層11的隔阻 與強摻雜P型接地平面層10分開，其p_逋道場效電晶體、 包括一 η型#23，其内有p -型源極和没極區域25和μ，在 源極和汲極之間的通道27,同通道範圍7,具有非常低的 摻雜濃度，可被視爲本質半導體範圍，在通道2 7上提供一 閘電極29，提供離表面非常近的接地平面範圍，係形成一 薄’埋在本質範圍27下並穿過Si Ge層31之強摻雜η-型區 域：>0 ’通常SiGe具有加速!!型雜質之擴散以取代減速之特 性，在此方案中以硼爲雜質，此即利用坤離子爲η型接地 平面30之摻雜的原因，在各種製程步驟期間，坤將以一加 速率擴散到SiGe層3 1，使得層3 1成爲相對較強的η型摻雜 ’無論如何，砷在矽中之擴散率非常低，而使得擴散在 SiGe層3 1和本質通道2 7之間界線停止。 參考囷7到圖10爲製造圖Η之裝置的數個製造步驟示意 圖’開始在強摻雜p型矽基板40上長一層較弱的掺雜p型看 4 1，其濃度係1 〇 Η到丨〇 15原子/立方公分，値得注意的. 是僅如圖7所示之低-歐姆基板4〇，而非圖8至圖1〇，在如 -11 - 本紙法尺度適用中國國家揉準（CNS > A4规格（210X297公釐） ----------^------ΐτ------^ (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央棣率局MC工消費合作社印«. 五、發明説明（9) 上所述之半導體主體1上形成一P型#3之η通道電晶體和一 η型#42之ρ通道電晶體，（如圖7所示），ρ#3和η#42之厚 度約爲1至3微米左右，平均摻雜濃度約爲1〇17原子/cm3 ，如圖8所示在本實施例所描述的主體上，長成一厚約2〇 nm的SiGe層1 1和厚約30 nm本質Si層7，在本實施例中可 能需選擇Si Ge層11的組份，在範圍3和42之間形成凹槽14 ，並將本質Si層7和SiGe層分成數個部份，（如圖9所示）。 請參考圖10，經由連續的光軍植入步驟，在SiGe層1 1 底下形成強摻雜p型層10和強摻雜η型層30，該層1〇之厚 度約爲30 nm ’植入離子爲硼離子，植入能量約爲25 keV ，植入劑量約爲1013原子/ cm2，利用植入砷（As)離子以 形成η型接地平面3 0，其植入能量約爲丨5〇 keV，劑量約爲 1〇13原子/cm2，植入步驟之後，做RTA處理，其溫度約 爲950°C持續2 5秒，以活化硼和砷原子並修護晶髋内之破 壞，閘氧化8在後續的氧化步驟中形成（形成方式可參照前. 述之實施例所述者），在熱處理步驟期間，經由s丨〇 e層1 1 的阻隔’來自強掺雜層1〇之8原子的擴散減速，而使得通 道範圍7之掺雜仍維持非常低，在p通道m〇ST之強摻雜層 30的As原子擴散到SiGe層，因此，在電晶體丁2内形成相 對強摻雜η型SiGe層3 1，由於在Si内之As擴散率非常低， 因此As在SiGe層31和Si層7之間的邊界停止擴散，由此，在 P通道電晶體之通道範圍濃度仍維持非常低，且在n通道電 晶體内之接地平面有利组份亦在p通道電晶體T 2内得到β 元成閘氧化8之後’形成τ〖之閘極9和Τ 2之2 9，沉積一 (請先閲讀背面之注意事項再填寫本頁) 裝- 訂
317648 Α7
經濟部申央橾準局貝工消费合作社印裝 播摻雜多層，再經連續蝕刻和植入步驟，形成11通道電晶 體Ltn型源極和及極區域5和6，和p通道電晶禮、之卩型 源極和汲極區域25和26，利用與前述實施例之相同之 摻雜之劑量和植入能量値，以蝕刻n通道電晶體之源極 和汲極區域，經由植入BF2離子以形成p通道電晶體、之 源極和汲極區域25，26，其植入劑量約爲5>< 1〇η離子/ cm2和能量約爲5 keV。經由植入BF2形成深區域，其植入 劑量約爲2.5 X 1 0 1 3離子/ cm2和能量約爲2〇 keV，閘極 29可能單獨或同時植入p型摻雜，在RT A處理之後，則儘 可能快速以阻止雜質之擴散，如前所述，在源極和汲極和 閘電極上形成矽化物接觸，之後，再製造絕緣層和金屬線 0 如前所述之活動範圍的邊界上形成凹槽，並充滿適當的 物質以得到平面，囷1 2到圈1 4係爲實施例之橫楗面囷，其 中，經由如前所述之LOCOS製程方法得到傳統場氧化物以· 區分活動範圍，圖1 2所示之半導體主體上提供矽氧化物的 圖案3j ’其厚度約爲〇.3微米’利用光軍氧化物之方法在 其表面上形成場氧化物，和用離子植入，以提供P型#3和η 型#23 ’如囷13所示’在氡化層33之間的活動範園内沉積 SiGe層11和本質Si層7’其SiGe層11之厚度和组威，和 本質層7之厚度與本發明第一個實施例同，在下列一連串 步樣中，離表面不遠並且在SiGe層11下提供強摻雜η型接 地平面30和ρ型接地平面10，如圖14所示，如前實施例所-述，繼續長成閘氧化層，接下來形成如前所述的閘電極和 -13- 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） nlli— n n n n n I ^ n n n I I n ϋ ϋ I— n n I ^ * (請先閱讀背面之注意事項再填寫本頁) 317648 A7 _ B7 五、發明説明（11 ) 源極和汲極區域。 本發明利用實施例之描述而非限制本發明，且利用本發 明範園内之技術可得到更多的變化，例如，在所描述的例 子中，可能改變其各種製造步驟的順序，例如，可以先植 入接地平面’之後再長成SiGe層和本質層，假如選擇性的 成長SiGe層和本質層，有可能局部的光軍半導體主體蝕刻 成長層，該成長層並不-定必要，例如，在局部的雙極= ^ — .*- (請先閲讀背面之注意事項再填寫本頁) 訂------線 經濟部中央揉準局貝工消-f合作社印装 -14- 本紙張尺度適用中國國家標準（CNS_) A4規格（210X297公釐） 317648 吖 il 州) 18 9 19 8 18
10 11
11 7 10

Claims (1)

  1. 申請專利範圍 1. 一種半導禮裝置’包括：一碎半導禮主體，具有一 p型 面範圍，並提供具有絕緣閘極之n型通道場效電晶體， 和在面範園内提供η型源極和汲極區域，利用都面之通 道範圍將其分開，在離面不遠的通道範圍下，提供一埋 藏式Ρ型掺雜區域，該區域比通道範圍具有較高的摻雜 濃度，在面範圍内之特性，係增加一埋藏式s i 1 - X G e X層 (稱SiGe層），χ爲Ge的莫耳分數，在鄰面之相士弱摻雜 通道範園和相對強摻雜埋藏式ρ型區域之間，在通道範 圍下形成一擴散障礙。 2. 根據申請專利範圍第丨項之半導體裝置，其特徵，利用 長晶層形成Si Ge層和鄰面之通道範圍。 3. 根據中請專利範圍〇第@之半導體裝置，其特徵， 從半導體主體表面延伸往下的n型源極和没極區域，其 深度化埋藏式ρ型區域和SiGe層深》 4-根據申請專利範園第1項之半導體裝置，.其特徵，在半 導雜主趙内利用在電晶雜兩側形成凹稽以分界，凹槽 可以填充或不填充材料，該凹槽從表面到半導统主體 内之深度大於源極和没極。 5.根據_請專利範囷第丨項之半導體裝置’其特徵，提供 鄭半導體主體表面之η型面範圍區域，提供具有絕緣閉 極和具有ρ型源極和汲極區域之ρ通道場效電晶體，其 Ρ型源極和汲極區域係在η型表面範園内並經通道範圍 分開，在η型表面範圍内之通道範圍下，提供一埋藏式 型區域，該區域摻雜As或Sb雜質濃度比鄰面之通道範園 裝 訂 線 中 而 η 本紙裇从通用中國园家標準（CNS )从祕（ -15
    和埋藏式SihxG%層之摻雜濃度高。 •根據申請專利範固第5項之半導鱧裝置，其特徵二表面 到埋藏式η型區域之距離等於表面和埋藏式SiGe層之間 的距離。 ， 7·根據申請專利範圍第〖項之半導髏裝置，其特徵，埋藏 式SiGe層厚度至大爲50 nm。 8·根據申請專利範園第7項之半導體裝置，其特徵，埋藏 式SiGe層之厚度上限範圍爲30nm且下限範圍爲2〇nm。 9·根，申請專利範圍第你第分之半導體裝置，其特徵， 埋藏式之莫耳ϋχ値约爲〇 3。 ------1-----^------1Τ------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央榡準局貝工消費合作社印裝 1 16 - 本紙張尺度通用中國囷家標準（CNS > Α4ΪΙ格（210X297公釐）
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Families Citing this family (144)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19720008A1 (de) * 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
CA2295069A1 (en) 1997-06-24 1998-12-30 Eugene A. Fitzgerald Controlling threading dislocation densities in ge on si using graded gesi layers and planarization
US6821710B1 (en) * 1998-02-11 2004-11-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US6143655A (en) * 1998-02-25 2000-11-07 Micron Technology, Inc. Methods and structures for silver interconnections in integrated circuits
US6121126A (en) * 1998-02-25 2000-09-19 Micron Technologies, Inc. Methods and structures for metal interconnections in integrated circuits
US6492694B2 (en) 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US6815303B2 (en) * 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
FR2790598B1 (fr) * 1999-03-01 2001-06-01 St Microelectronics Sa NOUVEAU TRANSISTOR A IMPLANTATION D'INDIUM DANS UN ALLIAGE SiGe ET PROCEDES DE FABRICATION
FR2791178B1 (fr) * 1999-03-19 2001-11-16 France Telecom NOUVEAU DISPOSITIF SEMI-CONDUCTEUR COMBINANT LES AVANTAGES DES ARCHITECTURES MASSIVE ET soi, ET PROCEDE DE FABRICATION
US7297990B1 (en) * 1999-05-07 2007-11-20 The Ohio State University Si/SiGe interband tunneling diode structures including SiGe diffusion barriers
FR2795555B1 (fr) 1999-06-28 2002-12-13 France Telecom Procede de fabrication d'un dispositif semi-conducteur comprenant un empilement forme alternativement de couches de silicium et de couches de materiau dielectrique
US6426279B1 (en) * 1999-08-18 2002-07-30 Advanced Micro Devices, Inc. Epitaxial delta doping for retrograde channel profile
EP1102327B1 (en) * 1999-11-15 2007-10-03 Matsushita Electric Industrial Co., Ltd. Field effect semiconductor device
KR100429869B1 (ko) * 2000-01-07 2004-05-03 삼성전자주식회사 매몰 실리콘 저머늄층을 갖는 ｃｍｏｓ 집적회로 소자 및기판과 그의 제조방법
US6633066B1 (en) 2000-01-07 2003-10-14 Samsung Electronics Co., Ltd. CMOS integrated circuit devices and substrates having unstrained silicon active layers
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
AU2001263211A1 (en) * 2000-05-26 2001-12-11 Amberwave Systems Corporation Buried channel strained silicon fet using an ion implanted doped layer
KR100495912B1 (ko) * 2000-06-27 2005-06-17 주식회사 하이닉스반도체 숏채널효과를 방지하기 위한 반도체소자 및 그의 제조 방법
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US7064399B2 (en) * 2000-09-15 2006-06-20 Texas Instruments Incorporated Advanced CMOS using super steep retrograde wells
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
FR2818012B1 (fr) 2000-12-12 2003-02-21 St Microelectronics Sa Dispositif semi-conducteur integre de memoire
US6495402B1 (en) * 2001-02-06 2002-12-17 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
EP1294016A1 (en) * 2001-09-18 2003-03-19 Paul Scherrer Institut Formation of self-organized stacked islands for self-aligned contacts of low dimensional structures
US6831292B2 (en) 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
WO2003067666A1 (fr) * 2002-02-07 2003-08-14 Matsushita Electric Industrial Co., Ltd. Dispositif a semi-conducteur et son procede de production
US7060632B2 (en) 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
CN100399576C (zh) * 2002-03-28 2008-07-02 先进微装置公司 于沟道区域中具有退化掺杂分布的半导体组件及用于制造该半导体组件的方法
US6667205B2 (en) * 2002-04-19 2003-12-23 International Business Machines Machines Corporation Method of forming retrograde n-well and p-well
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
AU2003274922A1 (en) 2002-08-23 2004-03-11 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
CN1286157C (zh) * 2002-10-10 2006-11-22 松下电器产业株式会社 半导体装置及其制造方法
US9673280B2 (en) * 2003-06-12 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Cobalt silicidation process for substrates comprised with a silicon-germanium layer
US7057216B2 (en) * 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
KR101068135B1 (ko) * 2003-11-21 2011-09-27 매그나칩 반도체 유한회사 반도체소자의 제조방법
JP3884439B2 (ja) * 2004-03-02 2007-02-21 株式会社東芝 半導体装置
WO2005101477A1 (ja) * 2004-04-14 2005-10-27 Fujitsu Limited 半導体装置及びその製造方法
WO2005117104A1 (en) * 2004-05-25 2005-12-08 Koninklijke Philips Electronics N.V. Semiconductor device and method of manufacturing such a device
US7491988B2 (en) * 2004-06-28 2009-02-17 Intel Corporation Transistors with increased mobility in the channel zone and method of fabrication
US7071103B2 (en) * 2004-07-30 2006-07-04 International Business Machines Corporation Chemical treatment to retard diffusion in a semiconductor overlayer
US7268049B2 (en) * 2004-09-30 2007-09-11 International Business Machines Corporation Structure and method for manufacturing MOSFET with super-steep retrograded island
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
WO2006061731A1 (en) * 2004-12-06 2006-06-15 Koninklijke Philips Electronics N.V. Method of producing an epitaxial layer on a semiconductor substrate and device produced with such a method
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP5481067B2 (ja) 2005-07-26 2014-04-23 台湾積體電路製造股▲ふん▼有限公司 代替活性エリア材料の集積回路への組み込みのための解決策
US7638842B2 (en) 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
JP2007158295A (ja) * 2005-11-10 2007-06-21 Seiko Epson Corp 半導体装置および半導体装置の製造方法
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7348629B2 (en) * 2006-04-20 2008-03-25 International Business Machines Corporation Metal gated ultra short MOSFET devices
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
WO2008039495A1 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
US7902569B2 (en) * 2007-07-17 2011-03-08 The Ohio State University Research Foundation Si/SiGe interband tunneling diodes with tensile strain
US8344242B2 (en) 2007-09-07 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-junction solar cells
JP2009158853A (ja) * 2007-12-27 2009-07-16 Toshiba Corp 半導体装置
JP5173582B2 (ja) * 2008-05-19 2013-04-03 株式会社東芝 半導体装置
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
EP2335273A4 (en) 2008-09-19 2012-01-25 Taiwan Semiconductor Mfg FORMATION OF EQUIPMENT BY EXCESSIVE GROWTH OF THE EPITAXIAL LAYER
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US20100181626A1 (en) * 2009-01-21 2010-07-22 Jing-Cheng Lin Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates
US8247285B2 (en) * 2008-12-22 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. N-FET with a highly doped source/drain and strain booster
DE102008063402B4 (de) * 2008-12-31 2013-10-17 Advanced Micro Devices, Inc. Verringerung der Schwellwertspannungsfluktuation in Transistoren mit einer Kanalhalbleiterlegierung durch Verringern der Abscheideungleichmäßigkeiten
JP5350815B2 (ja) * 2009-01-22 2013-11-27 株式会社東芝 半導体装置
JP5705207B2 (ja) 2009-04-02 2015-04-22 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． 結晶物質の非極性面から形成される装置とその製作方法
EP2267782A3 (en) 2009-06-24 2013-03-13 Imec Control of tunneling junction in a hetero tunnel field effect transistor
US8298882B2 (en) * 2009-09-18 2012-10-30 International Business Machines Corporation Metal gate and high-K dielectric devices with PFET channel SiGe
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
CN102640269B (zh) * 2009-09-30 2015-08-12 苏沃塔公司 电子装置和系统及其制造和使用方法
KR101746887B1 (ko) * 2009-11-17 2017-06-27 엠아이이 후지쯔 세미컨덕터 리미티드 전자 장치 및 시스템과, 그 제조 및 사용 방법
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) * 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8466473B2 (en) * 2010-12-06 2013-06-18 International Business Machines Corporation Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
KR20130118103A (ko) * 2012-04-19 2013-10-29 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
CN103545200B (zh) * 2012-07-12 2015-12-09 中芯国际集成电路制造(上海)有限公司 晶体管和晶体管的形成方法
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9431068B2 (en) 2012-10-31 2016-08-30 Mie Fujitsu Semiconductor Limited Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
CN103855020B (zh) * 2012-12-04 2016-06-29 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9972524B2 (en) * 2013-03-11 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a semiconductor device
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
CN104124170A (zh) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US10103064B2 (en) 2014-05-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor structure including epitaxial channel layers and raised source/drain regions
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
CN116632062A (zh) * 2022-02-14 2023-08-22 联华电子股份有限公司 中压晶体管及其制作方法
CN116314339B (zh) * 2023-05-23 2023-09-12 合肥晶合集成电路股份有限公司 一种集成半导体器件及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848936A (ja) * 1981-09-10 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
US5241210A (en) * 1987-02-26 1993-08-31 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
US5298435A (en) * 1990-04-18 1994-03-29 National Semiconductor Corporation Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon
US5166765A (en) * 1991-08-26 1992-11-24 At&T Bell Laboratories Insulated gate field-effect transistor with pulse-shaped doping
JP3146045B2 (ja) * 1992-01-06 2001-03-12 株式会社東芝 半導体装置及びその製造方法
US5242847A (en) * 1992-07-27 1993-09-07 North Carolina State University At Raleigh Selective deposition of doped silion-germanium alloy on semiconductor substrate
KR960008735B1 (en) * 1993-04-29 1996-06-29 Samsung Electronics Co Ltd Mos transistor and the manufacturing method thereof
US5298457A (en) * 1993-07-01 1994-03-29 G. I. Corporation Method of making semiconductor devices using epitaxial techniques to form Si/Si-Ge interfaces and inverting the material
US5792679A (en) * 1993-08-30 1998-08-11 Sharp Microelectronics Technology, Inc. Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
US5500391A (en) * 1994-08-09 1996-03-19 At&T Corp. Method for making a semiconductor device including diffusion control

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