CN103855032A - 半导体器件的制造方法和用于半导体器件的装置 - Google Patents
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Abstract
本发明涉及半导体器件的制造方法和用于半导体器件的装置。该方法包括：在块体衬底上的埋入氧化物层上形成拉伸SSOI层；在SSOI层中形成多个翅片；去除翅片的一部分；将翅片的剩余部分退火以松弛翅片的拉伸应变；和合并翅片的剩余部分。
Description
技术领域
本发明的示例性实施例一般涉及半导体器件，更特别地，涉及具有应变绝缘体上硅衬底的互补金属氧化物半导体器件。
背景技术
互补金属氧化物半导体器件（CMOS）使用配置于硅或绝缘体上硅（SOI）衬底上的p型和n型金属氧化物半导体场效应晶体管（MOSFET）的互补和对称取向对。用于放大或切换用于逻辑功能的电子信号的MOSFET具有通过沟道连接的源极区域和漏极区域。源极区域是多数电荷载流子（即，电子或空穴）的形式的电流通过其进入沟道的端子，并且，漏极区域是多数电荷载流子的形式的电流通过其离开沟道的端子。在p型MOSFET（以下，称为“PFET”）中，多数电荷载流子是流过沟道的空穴，并且，在n型MOSFET（以下，称为“NFET”）中，多数电荷载流子是流过沟道的电子。栅极与沟道重叠并控制源极区域与漏极区域之间的电流的流动。沟道可由提供多于一个的表面的薄“翅片（fin）”限定，通过该薄“翅片”，栅极控制电流的流动，由此使得PFET和NFET为“finFET”器件。一般地，翅片的长度比宽度大几个数量级。
在PFET和NFET的制造中使用的衬底可包含应变的绝缘体上硅（SSOI）衬底。这种衬底一般具有几吉帕斯卡（GPa）的固有拉伸应力，这一般提高电子迁移率，由此提高器件性能。这些衬底中的应变允许提高器件的性能，使得即使在沟道的长度和宽度与典型的平面MOSFET相比较短的短沟道finFET器件中，也没有静电特性的劣化。
但是，当SSOI衬底中的全局固有应力超过预定的最大值（例如，大于约1GPa）时，PFET finFET器件的性能会折衷8～15%。当在SSOI衬底中存在拉伸应力时，这是空穴迁移率劣化的结果。因此，希望松弛PFET器件的沟道中的拉伸应力并将它们的性能提高/恢复到SOI衬底水平。如果可以实现这一点，那么可在不使互补PFET器件劣化的情况下制成具有较高性能的NFET器件。
发明内容
在一个示例性方面中，方法包括：在块体衬底上的埋入氧化物层上形成拉伸SSOI层；在SSOI层中形成多个翅片；去除翅片的一部分；将翅片的剩余部分退火以松弛翅片的拉伸应变；和合并翅片的剩余部分。
在另一方面中，方法包括：将拉伸SSOI层附到衬底的第一表面上；在SSOI层中形成多个翅片；形成横穿多个翅片的栅极；通过使用蚀刻技术去除翅片的至少一部分；使翅片的剩余部分经受升高的温度以松弛翅片的拉伸应变；通过利用翅片上的Si和SiGe中的至少一种的外延生长来合并栅极的源极侧的翅片的剩余部分，以形成合并的源极区域；和通过利用翅片上的Si和SiGe中的至少一种的外延生长来合并栅极的漏极侧的翅片的剩余部分，以形成合并的漏极区域。
在另一示例性方面中，装置包括：具有拉伸SSOI层的衬底；在SSOI层上形成并且从衬底垂直延伸并相互平行的多个翅片，翅片具有松弛的拉伸应变；位置横穿翅片延伸的栅极，栅极的第一侧的翅片与源极连通并且栅极的第二侧的翅片与漏极连通；合并栅极的第一侧的翅片的源极区域；和合并栅极的第二侧的翅片的漏极区域。源极区域和漏极区域包含通过Si和SiGe中的至少一种的外延生长形成的层。
附图说明
结合附图阅读以下的详细描述，可以更容易地理解示例性实施例的以上和其它方面，其中，
图1A是衬底上的PFET和NFET的一个示例性实施例的与栅极平行（与翅片垂直）的断面图，PFET和NFET的翅片被合并以形成合并的源极区域和合并的漏极区域；
图1B是图1A的断面图，该断面图与栅极垂直（与翅片平行），并且表示PFET衬底区域；
图2是图1A和图1B的衬底的断面图；
图3A是上面形成有翅片的图2的衬底的断面图，该示图与翅片垂直；
图3B是图3A的衬底的顶视图；
图4A是PFET衬底区域的断面图，该断面图与翅片平行，并且表示跨着翅片形成的栅极区域；
图4B是与图4A的栅极区域平行的PFET衬底区域和NFET衬底区域的断面图；
图5A是与栅极垂直的PFET衬底区域的断面图，该栅极具有第一隔板和任选的注入扩展；
图5B是与PFET衬底区域和NFET衬底区域的翅片垂直并与栅极区域和第一隔板平行的断面图；
图6A是与翅片平行的PFET衬底区域的断面图，表示设置在栅极的任一侧的第一隔板和第二隔板；
图6B是与栅极和隔板平行的PFET衬底区域和NFET衬底区域的断面图，使得NFET衬底区域被掩蔽；
图7A是与栅极垂直的PFET衬底区域的断面图，表示回蚀刻的翅片；
图7B是与翅片垂直的断面图，表示回蚀刻的PFET衬底区域的翅片和掩蔽的NFET衬底；
图8A是与栅极垂直的断面图，表示PFET衬底区域上的合并的源极区域和合并的漏极区域；
图8B是与翅片垂直的断面图，表示PFET衬底区域上的合并的源极区域和合并的漏极区域，并且表示掩蔽的NFET衬底区域。
具体实施方式
在本发明的示例性实施例中，通过使用固有拉伸应力被松弛的应变绝缘体上硅（SSOI）层，制成半导体器件。拉伸应力的松弛提高PFET半导体器件的性能。虽然半导体器件在以下被称为PFET，但半导体器件不限于此并且可包含NFET。
在PFET的制造中，从应变绝缘体上硅（SSOI）衬底形成翅片，并且，在翅片上形成栅极叠层和隔板。翅片的多个部分被去除，并且，通过在一个时间段使翅片经受升高的温度（“预烘焙”），翅片的剩余材料的单轴拉伸应变得到松弛。硅或锗化硅（SiGe）在翅片的露出面上外延生长以合并源极区域和漏极区域。薄金属层沉积于外延生长的硅或SiGe上，并且，实施低温退火处理以在硅或SiGe上形成硅化物。在这里公开的示例性实施例适于单个翅片或多翅片的配置。
如图1A所示，CMOS器件的一个示例性实施例统一由附图标记90表示并且以下称为“器件90”。器件90可包含在衬底120上形成的PFET100和NFET500。PFET100可包含取向相互平行并且合并在一起以限定栅极区域130的一侧的源极区域190的多个翅片110和取向相互平行并且合并在一起以限定栅极区域130的相对侧的漏极区域200（图1B）的多个翅片110。栅极区域130横穿翅片110并且包含单层或多层栅极150和栅极150的相对两侧的第一隔板250和第二隔板280。在使用多层栅极150的实施例中，栅极150可包含设置在衬底120上和各翅片110上的高k电介质材料。如后面描述的那样，硅化物盖子180沉积于栅极150的顶部和翅片110的顶部。如图所示，可通过使用栅极－第一集成方案限定栅极150。但应理解，关于栅极150描述的示例性实施例也适用于替代金属栅极（RMG）技术。
现在参照图2-8B，表示制造PFET100的一种示例性方法。如图2所示，衬底120可包含上面具有二氧化硅（SiO2）的埋入氧化物层210的块体硅材料125。从中形成翅片110的SSOI层220被附到埋入氧化物层210上。SSOI层220一般通过使用利用热激活过程的层转印技术被附到埋入氧化物层210上，其中，施主衬底晶片被水平切割并且来自施主衬底晶片的薄层被置于新衬底（在这种情况下为埋入氧化物层210）上并与其接合。可以使用的一种示例性层转印技术是可从Grenoble,France的S.O.I.TEC,S.A.得到的SMART CUT。但是，由于其它的形成SSOI层的其它方法是可行的，因此这里描述的示例性实施例不限于通过层转印技术附着SSOI层220。
现在参照图3A和图3B，通过使用光刻并且将SSOI层220向下蚀刻到埋入氧化物层210，在SSOI层220中形成翅片110。如图所示，翅片110部分地限定PFET100以及相邻的NFET500。当形成时，如图3B所示，示例性的翅片110的厚度T为约7nm～约20nm，并且，高度h为约20nm～约30nm。翅片的长度范围可以为约100nm～几微米。但是，栅极间隔可以为60nm～500nm。可通过使用干蚀刻技术（例如，诸如反应离子蚀刻（RIE）等的等离子干蚀刻或使用例如含氟气体的非等离子蚀刻技术）等，蚀刻SSOI层220。
参照图4A～6B，PFET100和NFET500中的每一个上的栅极区域由横穿翅片110层叠的一个或更多个层限定。在如图4A和图4B所示的那样形成PFET100的栅极区域130和NFET的栅极区域530时，在翅片110之间和上面沉积多晶硅或金属层（连同未示出的任何希望的电介质层），并然后通过使用光刻法和蚀刻步骤将其构图，以限定横穿翅片110延伸的栅极叠层（例如，NFET500的栅极150和栅极550）。
在任何示例性实施例中，栅极叠层因此被构图。为了在允许翅片110上的外延生长的同时禁止栅极150（或栅极550）上的Si或SiGe的外延生长，硬掩模材料的氮化物盖子230在栅极层的顶部通过使用低压化学气相沉积（LPCVD）沉积，并在栅极150（和栅极550）限定中被构图。可形成氮化物盖子230的硬掩模材料可以是包含但不限于SiN、Si3N4、氮化硅碳和以上材料的组合等的任何基于氮化物的电介质材料。
如图5A所示，在PFET100的栅极150的相对两侧形成第一隔板250。通过在栅极叠层和氮化物盖子230侧沉积硬掩模材料并通过使用干蚀刻处理（例如，反应离子蚀刻（RIE））去除硬掩模材料的多个部分以形成第一隔板250的形状，形成第一隔板250。形成第一隔板的硬掩模材料可以是包含但不限于SiN、Si3N4、SiO2和氮化硅碳等的任何电介质材料。
一旦形成第一隔板250，就在第一隔板250下注入掺杂剂离子，以形成源极扩展区域和漏极扩展区域。可通过使用任意适当的离子注入技术注入掺杂剂离子以形成扩展区域。可在PFET100中注入以形成扩展区域的离子包含但不限于硼和二氟化硼（BF2）等。如图5B所示，可在NFET500的栅极区域530的相对侧形成第一隔板550（与第一隔板250类似）。
如图6A所示，可然后通过在第一隔板250侧沉积硬掩模材料并通过使用RIE蚀刻硬掩模材料，在PFET100的第一隔板250上形成第二隔板280。与第一隔板250同样，形成第二隔板280的硬掩模材料可以是包含但不限于SiN、Si3N4、SiO2和氮化硅碳等的任何电介质材料。
也可在NFET500的第一隔板550上形成第二隔板。但是，在在PFET100的第一隔板250上且不在NFET500的第一隔板550上形成第二隔板280的实施例中，如图6B所示，可在NFET500的第一隔板550上沉积掩模555，由此允许仅在PFET100的第一隔板250且不在NFET500的第一隔板550上沉积第二隔板280。
如图7A和图7B所示，PFET100的翅片110被回蚀刻到约2nm～5nm的高度，以为通过使用Si或SiGe外延合并翅片110做准备。翅片110通过使用任何适当的各向同性蚀刻技术（例如，诸如RIE等的等离子干蚀刻）被回蚀刻。如图7B所示，掩模555保持于NFET500上。
在翅片回蚀刻处理中，衬底120、翅片110的剩余部分和栅极叠层经受称为外延预烘焙的原位预外延退火。该步骤被用于获得用于外延生长的没有氧化物的硅/半导体表面。SSOI/外延界面上的污染物可导致高密度的外延缺陷，这会导致较高的器件泄漏电流，这又会损害PFET100的产量。在约700～900℃的温度下在氢气气氛中实施外延预烘焙约2～30分钟。优选地，在约800℃的温度下实施预烘焙约2分钟。在预烘焙步骤中，源极、漏极和沟道区域中的翅片110处于栅极下的部分松弛到栅极限定之前的应力水平的约10%，这足以不导致PFET100的空穴迁移率和性能的劣化。
如图8A和图8B所示，使用外延生长处理以在翅片110的剩余部分的露出110和100晶面上生长Si或SiGe。Si或SiGe在这些面的外延生长将栅极区域130的一侧的PFET110的翅片110合并到源极区域190中。栅极区域130的另一侧的PFET100的翅片110也合并到漏极区域200中。翅片110上的Si或SiGe的生长温度为约500～约850℃（优选约800℃），时间为约20～40分钟，以进一步松弛拉伸应变。通过Si或SiGe的外延生长形成的源极区域190和漏极区域200（如图8A和图8B所示）的合并的翅片结合翅片110的松弛的拉伸应变抑制完成的PFET100的性能的劣化。
源极区域190和漏极区域200可掺杂有受主掺杂剂。掺杂可任意地通过原位外延或诸如磷或硼的离子注入。任选地，可在PFET100上实施源极/漏极离子注入处理。
重新参照图1A和图1B，NFET500上的掩模555可被去除，并且，栅极150（和栅极550，如图4B所示）上的氮化物盖子230可通过使用氢氟酸（HF）和磷酸（H3PO4）中的一种或更多种的湿蚀刻技术被去除。一旦氮化物盖子230被去除，就可在栅极150和栅极550的任意侧的第一隔板250之间的栅极150和栅极550上以及在源极区域190和漏极区域200的合并的翅片的顶部表面上形成硅化物盖子180。在形成硅化物盖子180时，在栅极150和合并的翅片上沉积适当的金属的薄层（5～15nm）。可然后通过在低温下退火，形成硅化物盖子180。可形成硅化物的示例性金属包含但不限于铂、钛、钴、镍、钽、钨和钼。
任选地，PFET100可被掩蔽，并且，NFET500的源极区域/漏极区域中的翅片110也可通过上述的外延被合并。也可原位实施NFET500的外延的掺杂。并且，可在NFET500的掺杂源极/漏极区域中实施离子注入（同时PFET100被掩蔽）。另外，可对于PFET100和NFET100施加热退火步骤以扩散和激活任何施加的掺杂剂。
在这里使用的术语仅出于描述特定的实施例目的，并且不意在限制本发明。如这里使用的那样，除非在上下文中另外明显指出，否则单数形式“一种”、“一个”和“该”意在也包括多数形式。还应理解，在本说明书中使用的术语“包括”和/或“包含”规定陈述的特征、整数、步骤、动作、要素和/或部件的存在，但不排除存在或添加一个或更多个其它的特征、整数、步骤、动作、要素、部件和/或它们的组。
已出于解释和描述的目的给出本发明的描述，但是，该描述意图不在于详尽或者限于公开的形式。在不背离本发明的实施例的范围和精神的情况下，许多修改和变更对于本领域技术人员来说是十分明显的。为了最好地解释本发明的原理和实际的应用并使得本领域技术人员能够理解具有适于设想的特定的用途的各种的修改的各种实施例的发明配置，选择和描述了实施例。
Claims (24)
1.一种制造半导体器件的方法，包括：
在块体衬底上的埋入氧化物层上形成拉伸SSOI层；
在SSOI层中形成多个翅片；
去除翅片的一部分；
将翅片的剩余部分退火以松弛翅片的拉伸应变；和
合并翅片的剩余部分。
2.根据权利要求1的方法，其中，在块体衬底上的埋入氧化物层上形成SSOI层包含从施主衬底切割SSOI层并使SSOI层与埋入的氧化物层接合。
3.根据权利要求1的方法，其中，将翅片的剩余部分退火包含使SSOI层经受升高的温度。
4.根据权利要求3的方法，其中，使SSOI层经受升高的温度包含在约700℃至约900℃的温度将SSOI层预烘焙约2分钟至约30分钟。
5.根据权利要求3的方法，其中，使SSOI层经受升高的温度包含在约800℃的温度将SSOI层预烘焙约2分钟。
6.根据权利要求1的方法，其中，合并翅片的剩余部分包含在翅片上外延生长Si和SiGe中的至少一种。
7.根据权利要求6的方法，其中，在翅片上外延生长Si和SiGe中的至少一种包含在翅片上沉积Si和SiGe中的至少一种和将翅片加热到约500℃至约850℃的温度约20分钟至约40分钟。
8.根据权利要求1的方法，其中，在SSOI层中形成多个翅片包含蚀刻SSOI层。
9.一种制造半导体器件的方法，包括：
将拉伸SSOI层附到衬底的第一表面上；
在SSOI层中形成多个翅片；
形成横穿多个翅片的栅极；
通过使用蚀刻技术去除翅片的至少一部分；
使翅片的剩余部分经受升高的温度以松弛翅片的拉伸应变；
通过利用翅片上的Si和SiGe中的至少一种的外延生长来合并栅极的源极侧的翅片的剩余部分，以形成合并的源极区域；和
通过利用翅片上的Si和SiGe中的至少一种的外延生长来合并栅极的漏极侧的翅片的剩余部分，以形成合并的漏极区域。
10.根据权利要求9的方法，其中，将SSOI层附到衬底的第一表面上包含从施主衬底去除SSOI层并使SSOI层与衬底的第一表面接合。
11.根据权利要求9的方法，其中，在SSOI层中形成多个翅片包含蚀刻SSOI层。
12.根据权利要求9的方法，其中，使翅片经受升高的温度包含使翅片经受约700℃至约900℃的温度约2分钟至约30分钟。
13.根据权利要求9的方法，其中，使翅片经受升高的温度包含使翅片经受约800℃约2分钟。
14.根据权利要求9的方法，还包括在栅极下面形成源极扩展区域和漏极扩展区域。
15.根据权利要求14的方法，其中，通过离子注入在栅极下面形成源极扩展区域和漏极扩展区域。
16.根据权利要求9的方法，还包括用磷和硼中的一种或更多种掺杂合并的源极区域和合并的漏极区域。
17.根据权利要求9的方法，还包括在合并的源极区域和合并的漏极区域的上表面上形成硅化物盖子。
18.根据权利要求9的方法，其中，通过利用翅片上的Si和SiGe中的至少一种的外延生长来合并栅极的源极侧的翅片的剩余部分以形成合并的源极区域和通过利用翅片上的Si和SiGe中的至少一种的外延生长来合并栅极的漏极侧的翅片的剩余部分以形成合并的漏极区域，包含在翅片上沉积Si和SiGe中的至少一种并将翅片加热到约500℃至约850℃约20分钟至约40分钟。
19.一种用于半导体器件的装置，该装置包括：
具有拉伸SSOI层的衬底；
在SSOI层上形成并且从衬底垂直延伸并相互平行的多个翅片，翅片具有松弛的拉伸应变；
位置横穿翅片延伸的栅极，栅极的第一侧的翅片与源极连通并且栅极的第二侧的翅片与漏极连通；
合并栅极的第一侧的翅片的源极区域；和
合并栅极的第二侧的翅片的漏极区域，
其中，源极区域和漏极区域包含通过Si和SiGe中的至少一种的外延生长形成的层。
20.根据权利要求19的装置，还包含在源极区域的翅片的至少一部分、漏极区域的翅片的至少一部分和栅极的至少一部分上的硅化物盖子。
21.根据权利要求19的装置，还包含在栅极下面的源极扩展区域和漏极扩展区域。
22.根据权利要求19的装置，其中，衬底包含SSOI层附到其上的埋入氧化物层。
23.根据权利要求19的装置，其中，源极区域和漏极区域中的至少一个掺杂有磷和硼中的至少一种。
24.根据权利要求19的装置，其中，SSOI层包含具有基本上单轴取向的拉伸应变。
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| CN105870061B (zh) * | 2015-02-10 | 2018-10-12 | 国际商业机器公司 | 用于绝缘体上应变硅晶片上双重隔离的方法和装置 |
| CN110310925A (zh) * | 2015-05-06 | 2019-10-08 | 意法半导体公司 | 以鳍式fet技术实现的集成式拉伸性应变硅nfet和压缩性应变硅锗pfet |
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Also Published As
| Publication number | Publication date |
|---|---|
| US8963248B2 (en) | 2015-02-24 |
| CN103855032B (zh) | 2016-08-17 |
| US20140151802A1 (en) | 2014-06-05 |
| US8946063B2 (en) | 2015-02-03 |
| US20140151806A1 (en) | 2014-06-05 |
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