CN105870061A - 用于绝缘体上应变硅晶片上双重隔离的方法和装置 - Google Patents

用于绝缘体上应变硅晶片上双重隔离的方法和装置 Download PDF

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CN105870061A
CN105870061A CN201610076671.5A CN201610076671A CN105870061A CN 105870061 A CN105870061 A CN 105870061A CN 201610076671 A CN201610076671 A CN 201610076671A CN 105870061 A CN105870061 A CN 105870061A
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effect transistor
transistor region
silicon
type field
layer
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CN105870061B (zh
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B.B.多里斯
何虹
A.卡基菲鲁兹
王俊利
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International Business Machines Corp
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Abstract

描述了一种在包括p型场效应晶体管(pFET)装置和n型场效应晶体管(nFET)装置的双重隔离互补金属氧化物半导体(CMOS)装置中形成鳍的方法以及具有双重隔离的CMOS装置。所述CMOS装置包括n型场效应晶体管(nFET)区域，所述nFET区域包括由应变硅构成的一个或多个鳍，所述nFET区域中的所述一个或多个鳍形成在绝缘体上。所述CMOS装置还包括p型场效应晶体管(pFET)区域，所述pFET区域包括在外延生长的硅上的、由硅(Si)或硅锗(SiGe)构成的一个或多个鳍，并且所述pFET区域包括浅沟道隔离(STI)填充以使所述pFET区域中的所述一个或多个鳍彼此隔离。

Description

用于绝缘体上应变硅晶片上双重隔离的方法和装置
技术领域
本发明涉及互补金属氧化物半导体(CMOS)，并且更具体地，涉及绝缘体上应变硅(SSOI)晶片上的双重隔离。
背景技术
鳍式场效应晶体管(finFET)是一种金属氧化物半导体FET(MOSFET)，其中导电沟道由硅鳍包覆。finFET装置可为包括形成在基板上的p型金属氧化物半导体(pMOS)finFET装置或pFET以及n型金属氧化物半导体(NMOS)finFET装置或nFET的互补金属氧化物半导体(CMOS)。绝缘体上硅(SOI)晶片包括具有含中性硅晶格的硅层的基板。当硅晶格大于中性硅晶格时，所述硅被称为是处于拉伸应变下。这通常是SSOI晶片中经受的应变。当所述硅晶格小于中性硅晶格时，所述硅被称为是处于压缩应变下。如所示，finFET(例如，CMOS装置)可包括分别具有硅(Si)鳍和硅锗(SiGe)鳍的n-沟道区域(nFET)和p-沟道区域(pFET)。虽然SSOI基板可改进nFET中的性能，但拉伸应变的SSOI基板可能引起pFET沟道区域中的迁移率衰减(mobility degradation)。
发明内容
根据本发明的一实施例，一种在包括p型场效应晶体管(pFET)装置和n型场效应晶体管(nFET)装置的双重隔离互补金属氧化物半导体(CMOS)装置中形成鳍的方法，包括：在pFET区域和nFET区域中均形成绝缘体上应变硅(SSOI)层，该SSOI层包括设置在设置于块状基板上的绝缘体上的应变硅层；仅在所述pFET区域中刻蚀所述应变硅层、所述绝缘体以及所述块状基板的一部分，以露出所述块状基板；仅在所述pFET区域中从所述块状基板外延生长硅(Si)；仅在所述pFET区域中在所述硅上外延生长额外的半导体材料；在所述pFET区域中由所述块状基板上生长的所述硅的一部分和所述额外的半导体材料形成一个或多个鳍；在所述pFET区域中由所述绝缘体上的所述应变硅层形成一个或多个鳍；以及在所述pFET区域中执行浅沟道隔离(STI)填充，以使所述pFET区域中的所述一个或多个鳍彼此隔离。
根据另一实施例，具有双重隔离的互补金属氧化物半导体(CMOS)装置包括n型场效应晶体管(nFET)区域，所述nFET区域包括由应变硅构成的一个或多个鳍，所述nFET区域中的所述一个或多个鳍形成在绝缘体上；以及p型场效应晶体管(pFET)区域，所述pFET区域包括由在外延生长的硅上的硅(Si)或硅锗(SiGe)构成的一个或多个鳍，并且所述pFET区域包括浅沟道隔离(STI)填充以使所述pFET区域的所述一个或多个鳍彼此隔离。
额外的特征和优势通过本发明的教导实现。在此详细描述了本发明的其它实施例和方面，并且其应被视为是所请求保护的发明的一部分。参见说明书和附图以更好地理解本发明的优势和特征。
附图说明
在文字部分最后的权利要求书中具体地指明并且清楚地请求了被视为本发明的保护主题。通过以下结合附图的详细说明，本发明的上述以及其它特征和优势将清楚可见，附图中：
图1至图13示出了在nFET区域中的绝缘体上形成Si鳍以及在pFET区域中的硅上形成SiGe鳍的工艺中涉及的中间结构的横截面视图，其展示了根据本发明一实施例的双重隔离，其中：
图1示出了在本实施例形成任何鳍之前的起始SSOI晶片；
图2示出了在图1的SSOI晶片上沉积硬掩模层、垫层(under layer)以及图案化的光刻胶层的中间结构；
图3示出了在pFET区域中刻穿包括基板的一部分的层的中间结构；
图4示出了在pFET区域中从基板外延生长Si并且随后外延生长SiGe层的中间结构；
图5示出了从图4所示结构的nFET区域剥离硬掩模层的中间结构；
图6示出了在pFET区域和nFET区域中均沉积硬掩模层的中间结构；
图7示出了在硬掩模层之上沉积芯层(mandrel layer)和图案化的光刻掩模的中间结构；
图8示出了使用图案化的光刻掩模图案化芯层以及在图案化的芯层之上沉积间隔体材料的中间结构；
图9示出了刻蚀间隔体材料的水平沉积部分的中间结构；
图10示出了从图9所示的结构中抽出图案化的芯层留下间隔体的中间结构；
图11示出了使用间隔体刻蚀pFET区域和nFET区域中的鳍的中间结构；
图12示出了沉积STI填充的中间结构；
图13示出了回刻STI并且剥离硬掩模的结构；
图14至图22示出了在nFET区域中绝缘体上形成Si鳍以及在pFET区域中硅上形成SiGe鳍的工艺中涉及的中间结构的横截面视图，其展示了根据本发明另一实施例的双重隔离，其中：
图14示出了在本实施例形成任何鳍之前的起始SSOI晶片；
图15示出了在图14的SSOI晶片上沉积硬掩模层、垫层和图案化的光刻胶层的中间结构；
图16示出了在pFET区域中刻穿包括基板的一部分的层的中间结构；
图17示出了在pFET区域中从基板外延生长硅、并且随后外延生长SiGe层的中间结构；
图18示出了从图17所示结构的nFET区域中剥离硬掩模层的中间结构；
图19示出了在pFET区域和nFET区域中均沉积硬掩模层的中间结构；
图20示出了在pFET区域和nFET区域中刻蚀鳍的中间结构；
图21示出了沉积STI填充的中间结构；
图22示出了回刻STI并且剥离硬掩模的结构。
具体实施方式
如上所示，SSOI晶片或者包括应变硅(通常是拉伸应变的硅)的晶片可改进nFET装置的优势，但会降低pFET沟道区域的性能。在此详细描述的各系统和方法的实施例涉及pFET沟道应变的释放并且同时维持nFET区域中的(拉伸)应变的SOI。此外，在此详细描述的实施例展示了双重隔离，使得nFET和pFET区域彼此隔离，并且使得pFET区域和nFET区域中每一区域内的鳍彼此隔离。
图1至图13示意了根据一实施例、在nFET区域中由绝缘体上(拉伸)应变硅形成Si鳍以及在pFET区域中在Si上形成SiGe鳍所涉及的工艺。图1是根据以下详细描述的实施例的、用于定义pFET区域和nFET区域的SSOI晶片100的横截面视图。该SSOI晶片100包括绝缘体120(例如，埋设氧化物(BOX))上的应变硅层110。该SSOI晶片100可通过已知的制造方法获得，该方法包括，例如，在Si晶片上生长梯度SiGe层以形成松弛SiGe层，以及在该SiGe层之上外延生长Si层。由于该松弛SiGe层的晶格大于Si晶体(中性)的晶格，该外延生长的Si层将是拉伸应变的。可形成具有BOX(即，埋设氧化物)的另一Si晶片并且(例如，通过晶片粘合技术)将其与BOX上的应变Si/SiGe/Si基板晶片粘合在一起。然后，可使用氢离子(H+离子)注入，以通过例如智能切割技术来切割SiGe和Si基板，并且可刻蚀掉应变Si上的任何剩余SiGe层以形成该SSOI晶片100。该绝缘体120形成在块状基板130上。
图2示出了在该SSOI晶片100的该应变硅层110上沉积硬掩模层115之后沉积垫层125和图案化的光刻胶层135的中间结构200。该硬掩模层115可由例如硅氮化物(SiN)构成。该垫层125可包括有机电介质层(ODL)和含硅的抗反射涂层(SiARC)。该光刻胶层135被图案化以覆盖nFET区域102中的垫层125并且同时使pFET区域101中的垫层125露出。图3示出了随后刻蚀图2所示结构200的中间结构300。nFET区域102中的垫层125和光刻胶层135被刻穿。基于该光刻胶层135的图案化并且通过选择性地控制刻蚀工艺的深度，露出区域(pFET区域101)的所有层被刻穿，只留下该基板130的一部分。nFET区域102中的SSOI晶片100和硬掩模层115保持完整。
图4示出了在pFET区域101中由剩余基板130之上外延生长的硅(130)和硅锗(SiGe)层140的中间结构400。如所示出的，硅从基板130开始外延生长。然后，在该外延生长的Si 130上外延生长该SiGe层140。可替换地，可外延生长额外的Si而不是该SiGe层140，从而在pFET区域101和nFET区域102中形成Si鳍。然而，pFET区域中外延生长的硅将不具有应变(从而形成pFET区域101中的中性鳍)。该SiGe层140可为中性的或具有压缩应变。控制Si从基板130的外延生长，使其大约具有与绝缘体120相同的高度。控制随后的SiGe层140(或额外的Si)的外延生长，使该额外的Si或SiGe层140大约具有与nFET区域102中的应变硅层110相同的高度。从该nFET区域102剥离该硬掩模层115，从而得到如图5所示的中间结构500。图6示出了通过在pFET区域101和nFET区域102上均沉积另一硬掩模层115而形成的中间结构600。
图7至图11示出了在pFET区域101和nFET区域102中形成鳍所涉及的一些工艺。图7所示的该中间结构700包括沉积在硬掩模层115上的芯层145以及在该芯层145之上被图案化的光刻掩模150。该芯层145可为例如非晶碳或非晶硅。该光刻掩模150可由例如SiARC、光平坦化层和光刻胶层构成。图8示出了使用该光刻掩模150图案化该芯层145、并且之后在图案化的芯层145之上沉积间隔体材料155的中间结构800。图9示出了通过各向异性(定向)反应离子刻蚀(RIE)工艺将图8结构800中所示的该间隔体材料155的水平沉积部分刻蚀为用于该图案化的芯层145的侧壁间隔体的结构900。从图9的结构900中抽出该芯层145，得到图10所示的中间结构1000。剩余的间隔体材料155充当图案以刻蚀nFET区域102中的硬掩模层115和SSOI晶片100以及pFET区域101中的硬掩模层115、SiGe层140和基板130，得到图11所示的结构1100。该刻蚀通过RIE工艺完成，所得到的Si鳍1110和SiGe鳍1120如图11所示。
如图11所指示的，Si鳍1110包括应变硅层110(该SSOI晶片100)，而SiGe鳍1120不包括任何应变硅层110。而且，该Si鳍1110形成在绝缘体120层上，而该SiGe鳍1120形成在从基板130生长的硅鳍上。结果，该Si鳍1110彼此隔离，但该SiGe鳍1120彼此不隔离。这是因为，在nFET区域102中，绝缘体120(例如，BOX)充当待形成的金属栅极的阻挡物。在pFET区域101中，形成有金属栅极于其上的高介电常数(高k)电介质可一直延续至基板130。图12示出了通过浅沟道隔离(STI)160填充和化学机械平坦化(CMP)工艺得到的中间结构1200。该STI 160被回刻并且该硬掩模层115被剥离以得到图13所示的结构1300。剥离该硬掩模层115的鳍显形(fin reveal)工艺可包括使用热磷酸(H3PO4)(例如，160摄氏度)以及控制刻蚀速率和刻蚀时间以选择性地刻蚀该硬掩模层115并且使该Si鳍1110和SiGe鳍1120显形。该STI 160隔离pFET区域101中的SiGe鳍1120。结果，基于额外的工艺而最终制成的CMOS将包括双重隔离(pFET区域101和nFET区域102之间的隔离，以及每一区域102、101中鳍1110、1120间的隔离)。
图14至图22示意了根据另一实施例的在nFET区域中由绝缘体上的(拉伸)应变硅形成Si鳍以及在pFET区域中在Si上形成SiGe鳍所涉及的工艺。由图14至图22示出的实施例涉及SSOI内较厚的绝缘体层，使得nFET区域中的Si鳍形成在由该绝缘体层形成的、在该绝缘体层之上延伸的鳍上。也就是，鳍刻蚀不完全延伸穿过该绝缘体层的整个厚度，使得该绝缘体层成为nFET区域中鳍结构的一部分并且成为鳍结构的基部。通常，厚度为100纳米(nm)或更小(例如，20nm)的绝缘体(例如，BOX)可被视为是“薄的”，而更厚的绝缘体(例如，140nm至200nm)可被视为是“厚的”。图1至图13涉及具有“薄的”绝缘体的实施例，而图14至图22涉及具有“厚的”绝缘体的实施例。
图14示出了SSOI晶片1400。与图1所示的SSOI晶片100相同，图14中的该SSOI晶片1400包括绝缘体120上的应变硅层110，该绝缘体设置在块状基板130上。图14所示SSOI晶片1400的绝缘体120比图1所示SSOI晶片100的绝缘体120厚。这导致了所形成的Si鳍2010的差异，下面将参照图20进行描述。
图15示出了在该SSOI晶片100的应变硅层110上沉积硬掩模层115之后沉积垫层125和图案化的光刻胶层135的中间结构1500。如参照图2所示，在nFET区域102中该图案化的光刻胶层135覆盖该垫层125，但在pFET区域101中该图案化的光刻胶层135不覆盖该垫层125。执行刻蚀以移除pFET区域101中的所有层，包括基板130的一部分，从而得到图16所示的结构1600。该光刻胶层135防止刻蚀该nFET区域102中的层。图17示出了在pFET区域101中从基板130外延生长硅之后，外延生长SiGe层140(可替换地，其可为额外的Si)的结构1700。如上文参照图4所述，可控制该外延生长以使得Si生长至大约该绝缘体120的高度并且使SiGe层140(或额外的Si)生长至大约该nFET区域102中该应变硅层110的高度。图18示出了从该nFET区域102剥离该硬掩模层115的结构1800。图19示出了在pFET区域101和nFET区域102之上均沉积硬掩模层115的结构1900。
执行类似于参照图7至图11所示出并讨论的鳍刻蚀工艺以获得图20所示的结构2000。图20显示了pFET区域101和nFET区域102中每一区域中的四个鳍2010、2020。鳍的数量可为1或任意数，由用于图案化该鳍(参照例如图10)的间隔体的数量决定。图11与图20的比较显示了根据图14至图22所示的实施例的绝缘体120的额外的厚度。再一次地，进行STI 160填充之后执行CMP工艺以提供图21所示的结构2100，并且在鳍显形工艺中回刻该STI 160并剥离该硬掩模层115(例如，使用热磷酸溶液，如参照图13所讨论过的)以提供图22所示的结构2200。在这一阶段，执行已知的工艺来完成CMOS的制造。与参照图1至图13讨论过的实施例相同，本实施例在pFET区域101中形成不包括应变硅层110的鳍2020，而在nFET区域102中形成包括应变硅层110和SSOI晶片1400的鳍2010。而且，基于STI 160填充，在pFET区域101和nFET区域102之中以及之间获得双重隔离。
在此使用的技术术语仅用于描述具体实施例的目的，并非旨在限定本发明。除非在上下文中另外明确指明，在此使用的单数形式的“一”、“一个”和“该”意在也包括复数形式。还应理解的是，当在说明书和权利要求书中使用术语“包括”和/或“包含”时，该术语指明了所阐述的特征、整数、步骤、操作、元件和/或组件的存在，但不排除额外的一个或更多个特征、整数、步骤、操作、元件、组件和/或其组合的存在。
下方权利要求书中的所有装置或步骤外加功能元件的对应结构、材料、动作和等同物旨在包括用于与其他特别声明请求保护的元件结合执行该功能的任意结构、材料或动作。已出于示意性和描述的目的呈现了本发明的说明书，但其不旨在穷举或限于以所描绘的形式存在的本发明。在不脱离本发明的范围和精神的前提下，许多修改和变型对于本领域技术人员而言是显而易见的。所选择并描述的实施例用于最好地解释本发明的原理和实际应用，并且使得本领域其他普通技术人员能够理解到本发明可具有可预见到的适用于具体应用的各种不同修改的各种不同实施例。
在此描绘的流程图仅为示例。在不脱离本发明精神的前提下，针对在此描述的该流程图或该步骤(或操作)可存在许多变型。例如，可以以不同的顺序执行该步骤，或者可以增加、删除或修改步骤。所有这些变型都应被视为是所请求保护的反明的一部分。
虽然已描述了本发明的优选实施例，但应理解的是，本领域技术人员不管在此时还是将来都可作出各种不同改进和强化，这些改进和强化落入随后权利要求书的范围内。这些权利要求书应被解释为维持初始描述的本发明的适当范围。
已出于示意性目的呈现了本发明的各种不同实施例的说明，但其不旨在穷举或限于在此描述的实施例。在不脱离在此描述的各实施例的范围和精神的前提下，许多修改和变型对于本领域技术人员而言将是显而易见的。所选择的在此使用的技术术语用于最好地解释各实施例的原理、实际应用或者相较于市场上已知技术的技术性改进，或者使得本领域其他普通技术人员能够理解在此描述的各实施例。

Claims (20)

1.一种在包括p型场效应晶体管装置和n型场效应晶体管装置的双重隔离互补金属氧化物半导体装置中形成鳍的方法，所述方法包括：
在p型场效应晶体管区域和n型场效应晶体管区域中均形成绝缘体上应变硅层，所述绝缘体上应变硅层包括设置于块状基板上的绝缘体上的应变硅层；
仅在所述p型场效应晶体管区域中刻蚀所述应变硅层、所述绝缘体以及所述块状基板的一部分以露出所述块状基板；
仅在所述p型场效应晶体管区域中从所述块状基板外延生长硅；
仅在所述p型场效应晶体管区域中在所述硅上外延生长额外的半导体材料；
在所述p型场效应晶体管区域中由所述块状基板上生长的所述硅的一部分和所述额外的半导体材料形成一个或多个鳍；
在所述n型场效应晶体管区域中由所述绝缘体上的所述应变硅层形成一个或多个鳍；以及
在所述p型场效应晶体管区域中执行浅沟道隔离填充，以使所述p型场效应晶体管区域中的所述一个或多个鳍彼此隔离。
2.如权利要求1所述的方法，其中所述仅在所述p型场效应晶体管区域中刻蚀所述应变硅层、所述绝缘体以及所述块状基板的所述部分包括使用包括有机电介质层和含硅的抗反射涂层的垫层以及使用仅覆盖所述n型场效应晶体管区域的图案化的光刻胶层。
3.如权利要求1所述的方法，其中所述外延生长硅包括控制生长的尺寸以保持所述p型场效应晶体管区域中生长的所述硅处于或低于所述n型场效应晶体管区域中所述绝缘体的高度。
4.如权利要求1所述的方法，其中在所述p型场效应晶体管区域中外延生长额外的半导体材料包括控制生长的尺寸以保持所述额外的硅或硅锗与所述n型场效应晶体管区域中所述应变硅层高度相同。
5.如权利要求1所述的方法，其中在所述p型场效应晶体管区域中形成所述一个或多个鳍以及在所述n型场效应晶体管区域中形成所述一个或多个鳍包括图案化所述p型场效应晶体管区域中所述额外的半导体材料之上以及所述n型场效应晶体管区域中所述应变硅层之上的硬掩模层上的间隔体材料。
6.如权利要求5所述的方法，其中在所述p型场效应晶体管区域中形成所述一个或多个鳍还包括：根据所述间隔体材料的图案，刻蚀所述p型场效应晶体管区域中所述硬掩模层和所述额外的半导体材料以及生长的所述硅的一部分。
7.如权利要求5所述的方法，其中在所述n型场效应晶体管区域中形成所述一个或多个鳍还包括：根据所述间隔体材料的图案，刻蚀所述n型场效应晶体管区域中所述绝缘体上的所述硬掩模层和应变硅层。
8.如权利要求1所述的方法，其中在所述p型场效应晶体管区域中执行所述浅沟道隔离填充包括执行化学机械平坦化工艺。
9.如权利要求1所述的方法，其中所述外延生长额外的半导体材料包括从所述块状基板生长额外的硅。
10.如权利要求1所述的方法，其中所述外延生长额外的半导体材料包括生长硅锗。
11.一种具有双重隔离的互补金属氧化物半导体装置，所述装置包括：
n型场效应晶体管区域，所述n型场效应晶体管区域包括由应变硅构成的一个或多个鳍，所述n型场效应晶体管区域中的所述一个或多个鳍形成在绝缘体上；和
p型场效应晶体管区域，所述p型场效应晶体管区域包括在外延生长的硅上的、由硅或硅锗构成的一个或多个鳍，并且所述p型场效应晶体管区域包括浅沟道隔离填充以使所述p型场效应晶体管区域中的所述一个或多个鳍彼此隔离。
12.如权利要求11所述的装置，其中所述外延生长的硅是从块状基板生长的。
13.如权利要求12所述的装置，其中所述硅是额外的外延生长的硅。
14.如权利要求13所述的装置，其中所述额外的外延生长的硅在所述p型场效应晶体管区域中生长至与所述n型场效应晶体管区域中所述应变硅相同的高度。
15.如权利要求11所述的装置，其中所述外延生长的硅在所述p型场效应晶体管区域中生长至处于或低于所述n型场效应晶体管区域中所述绝缘体的高度。
16.如权利要求11所述的装置，其中所述硅锗是外延生长的硅锗。
17.如权利要求16所述的装置，其中所述硅锗在所述p型场效应晶体管区域中外延生长至与所述n型场效应晶体管区域中所述应变硅相同的高度。
18.如权利要求11所述的装置，其中所述浅沟道隔离填充是通过化学机械平坦化工艺而平坦化的。
19.如权利要求11所述的装置，其中所述n型场效应晶体管区域中的所述一个或多个鳍设置在绝缘体层上。
20.如权利要求11所述的装置，其中所述n型场效应晶体管区域中的所述一个或多个鳍设置在块状基板上。
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